;
>
> *From: *gem5-users on behalf of Timon
> Evenblij
> *Reply-To: *gem5 users mailing list
> *Date: *Monday, 6 August 2018 at 06:56
> *To: *gem5 users mailing list
> *Subject: *Re: [gem5-users] Cache Management
>
>
>
> Hi Abishek,
>
>
>
> Everything
second request with the first and
> will service both of them at once when the response arrives to L1.
>
>
>
> Nikos
>
>
>
> *From: *gem5-users on behalf of Timon
> Evenblij
> *Reply-To: *gem5 users mailing list
> *Date: *Monday, 6 August 2018 at 06:56
> *To
Timon Evenblij
Reply-To: gem5 users mailing list
Date: Monday, 6 August 2018 at 06:56
To: gem5 users mailing list
Subject: Re: [gem5-users] Cache Management
Hi Abishek,
Everything is possible, it all depends on the cache policy. I think the default
behavior in gem5 is a write-back cache, and I
Hi Abishek,
Everything is possible, it all depends on the cache policy. I think the
default behavior in gem5 is a write-back cache, and I am not sure if any
other policies are implemented (Can someone else confirm?). A write-back
cache only writes the data back upon eviction, unlike a write-trough
Hi Timon,
I had one question eviction of write back.
What happens when a dirty block is evicted from L1 cache. Does it check L2
cache updates the content of that block in L2 and then goes to memory and
update contents in memory ?
On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij
wrote:
> Hi Abishek,
Hi Abishek,
No, for this case, MSHRs (miss status handling registers) exists. These are
registers that keep track of missed cache accesses (in your case packet 1
that misses in L1), so the cache can be freed to reply to other accesses
(packet 2) while waiting for the answer of the miss (packet 1 g
My question is simple if there are two packets wants to access L1 cache in
a system of 2 level cache and cpu is o3. Will packet 2 has to wait for
packet 1 to get its response(packet 1) from L2 in case of L1 cache miss and
L2 cache hit?
What happen if its L2 miss?
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