[gem5-users] How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

[Khan Shaikhul Hadi via gem5-users]

In my code I'll have a simobject which has its own cache. As classical
cache use CpuSidePort and MemSidePort to receive and respond to request, I
want to create some internal CpuSidePort and MemSidePort in my simobject
like below

> class SimObject : public ClockedObject
> {
>  Cache cache;
> CpuSidePort  cacheMemSidePortConnection;
> MemSidePort cacheCpuSidePortConnection;


> // CpuSidePort and MemSidePort class could follow same structure as
> BaseCache CpuSidePort and MemSidePort


> ...
> ...
> ...
> }

My question is how could I connect this ports with cache such that when I
schedule some request pkt using cacheCpuSidePortConnection, cache's
cpuSidePort will catch that packet, when cache's memSidePort schedule some
req pkt, cacheMemSidePort will catch that pkt.
In the front end, I could see in the library, we could do that using param
( cache.cpu_side_port = cpu.mem_side_port). But could not find any
reference that connects to port within a simobject.
Any suggestions  or resources which I could follow ?


Best
Shaikhul

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