Hello All, I am trying to model a deeper O3 pipeline as suggested in https://gem5-users.gem5.narkive.com/LNMJQ1M5/model-deeper-pipeline-in-x86 but I keep running into some assertion failures related to the time buffers and skid buffers even though that patch mentioned in the previous link is already added in my gem5 version.
Is there any relation between the different pipeline delay values, widths, forward and backward communication sizes and any others parameter of the O3 cores that has to be maintained to avoid running into problems? For reference, these are the assertion failures I a facing depending on the values I choose: /cpu/timebuf.hh:54: void TimeBuffer<T>::valid(int) const [with T = DefaultRenameDefaultIEW<O3CPUImpl>]: Assertion `idx >= -past && idx <= future' failed. cpu/o3/decode_impl.hh:425: void DefaultDecode<Impl>::skidInsert(ThreadID) [with Impl = O3CPUImpl; ThreadID = short int]: Assertion `skidBuffer[tid].size() <= skidBufferMax' failed. Best Regards, Shehab
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
