Hi Volkan,
I've noticed that you've been working on RISC-V in gem5 and I'd like to ask you
some questions.
I've added custom instructions to the RISC-V ISA by modifying the contents
of/src/arch/riscv/ISA/decoder and it works properly. But I want to know how to
specify the operation time
Yeah, it does not seem like m5ops are implemented in RISC-V yet. I did not
see any RISC-V specific code in "util/m5/src/abi/". One workaround could be
to stop simulation at a particular instruction count (e.g. if you know at
what instruction number your function of interest starts and ends) from
Hi Ayaz,
Thank you so much for your answers, these definitely cleared things up a bit.
I'll try to look deeper in the code and see if I can navigate the Python
interface to adjust latencies. Also thanks for pointing out m5ops, I was not
aware. Though I wonder whether the documentation has not
Hi Volkan,
Following is my understanding of the issues you mentioned in your email (I
hope someone with more RISCV experience can augment/correct this):
1. Each functional unit can be responsible for execution of multiple
classes of instructions and you can configure the latency of each class of
