Hi,
I have a topology as follows:
ARM_CPU <-> L1_Data_Cache <-> L2_Coherent_Bus <-> L2_Cache <->
Memory_Coherent_Bus <-> My_Bridge
My_Bridge has a SimpleMemory to connect with Memory_Coherent_Bus.
If My_Bridge has to snoop into ARM_CPU, are these assumptions correct for a
Snoop Read transaction?:
1. Create a new Request object ( phy_addr, flags, master_ID )
a. Phy_addr is the address that I want to snoop
b. Flags: NO_ACCESS | any other applicable here? What exactly does
MEM_INHIBIT mean?
c. Master_ID: What range can I use?
2. Create a new Packet object ( RequestPtr, MemCmd )
a. ReadReq | ReadExReq
b. Set EXPRESS_SNOOP flag, NORMAL_SNOOP isn't allowed currently, right?
3. Call sendTimingSnoopReq() on CoherentBusMasterPort of Memory_Coherent_Bus
4. Expect a callback in recvTimingSnoopResp( PacketPtr Pkt ) in My_Bridge
a. Check on associated MemCmd
b. If HasData:
i. We can expect PacketDataPtr in
Pkt to be valid and of size equal to L1/L2 Cache-size
5. Are there any other things I need to do to complete a snoop transaction?
Thanks,
Uday
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
