There are a few things that I have identified that need to be implemented
or created, including memory attributes/protection and a kernel+boot image,
and a few more things that need to be tested somehow, including switching
privilege modes and interrupts. I think the most important issue is the
Hi Alec,
Thanks for welcoming me!
What is current status in the implementation RISC-V FS mode?
Also, what are the open issues and where are you tracking them?
For now, I will check the above files pointed by you.
Thanks and Regards,
Rishabh Jain
On Fri, Mar 8, 2019 at 8:17 PM Alec Roelke
The RISC-V CSRs are implemented as misc regs, which are the responsibility
of the ISA to maintain. ISA traits for RISC-V are implemented in
src/arch/riscv/isa.cc and .hh. The ISA object itself does not have any
references to CPUs or threads, so CSRs such as performance counters and
MHARTID can't
Hi Alec,
Thanks for the reply.
For the mhart id issue, could you please point out the file which
implements mhart id?
I will give a shot to understand the necessary files.
If you can let me know, I can send a pull request regarding the same which
you can check and merge.
Also, do you plan to
When gem5 runs in SE mode, it is intended to mainly run user-level code,
which higher-privilege code that executes during system calls offloaded to
the host. The privileged instructions do have definitions and at least
partial implementations, and you can run them in SE mode because privilege
Hi Alec,
Thanks for the reply.
First, I have a few queries (for RISCV ISA):
1. In which privilege mode does gem5 boot in? If it is supervisor mode or
user mode, then how do I run binaries in machine mode?
2. Can I use garnet2.0 and ruby model for riscv?
I applied the patch by updating the
Hi Rishabh,
You're right that mhartid should not be the same for every CPU. It looks
like you may have found a bug in RISC-V in that mhartid had not been
implemented yet. This is odd, though, because I thought I had implemented
it. In any case, try this patch (
Hi everyone,
I have started working with gem5 from past 2 weeks and am trying to
simulate a multi-core CPU system with RISC-V ISA on gem5.
I have written a C file where I use inline assembly snippet to grab the
value of mhartid (Hardware Thread id), marchid and mstatus.
I used this command to
