Hi Gabe,
I think answer to my last question was subsumed in your prior response itself.
Thanks for the clarifications.
Thanks,
Shyam
> On Aug 2, 2019, at 5:07 PM, Shyam Murthy wrote:
>
> Hi Gabe,
>
> I was reading through this today
> (https://www.intel.com/content/dam/www/public/us/en/doc
Hi Gabe,
I was reading through this today
(https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf#page=129).
Within gem5 however, for instructions MOVZX_B_R_M and MOVZX_W_R_M, the
translated microops are such that they entail partia
There is no way to disable that. The number and identity of the
instructions sources/destinations would need to change based on the operand
size, and that's not implemented. You could possibly add extra information
to the microops to help determine when that sort of thing is happening. All
the micr
Thanks Gabe, suppose I’m trying to carry out a data flow analysis on the
program, then quite often I rely on the source registers tagged by gem5. In
this process, would I not be tracking false dependencies? Is there a way I can
disable this?
Additionally, have you modelled the same only for LEA
The main reason I am asking is because I am trying to do some dependency
analysis in the programs, and false dependencies show up in the process
because architecture registers that are destination registers also get
populated as source registers (when there is no true dependency). Am I
understandin
Hi Gabe,
Why is that for some of the operations like ld and lea, the decoding logic
within *build/X86/arch/generated/decoder-ns.cc.inc, *the destination
register is also decoded as a src register?
Thanks,
Shyam
___
gem5-users mailing list
gem5-users@gem
