Patch Set 2: Code-Review+2
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Patch Set 2: Code-Review+1
Hmm.. I would prefer to add the comments in another patch. Try to keep patches
minimal and on a single topic.
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Patch Set 2: Code-Review+1
In two years we won't know what "latest Ubuntu" is. Always better to put a
version number in there. Stretch won't have it either.
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Patch Set 7:
(1 comment)
https://gerrit.osmocom.org/#/c/2286/7/openbsc/src/libcommon/gsm_data_shared.c
File openbsc/src/libcommon/gsm_data_shared.c:
Line 70: const struct value_string bts_variant_names[_NUM_BTS_VARIANT + 1] = {
BikeShedding:
* bts_variant.. they are all osmo-bts variants.
Harald Welte has submitted this change and it was merged.
Change subject: test: Add a manual test to simulate DTMF handling in
osmo-sip-connector
..
test: Add a manual test to simulate DTMF handling in osmo-sip-connector
Add
Patch Set 1: Code-Review+2 Verified+1
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Harald Welte has submitted this change and it was merged.
Change subject: mncc: Make it possible to build a MNCC server for testing
..
mncc: Make it possible to build a MNCC server for testing
For manual testing the
Patch Set 1: Verified+1
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Patch Set 1: Code-Review+2
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Patch Set 2:
> (1 comment)
No, of course. SSE3 support is mandatory for accelerated Viterbi
implementation only (viterbi_sse.c). If SSE3 isn't supported by
target CPU, then not-accelerated Viterbi implementation will be
used (viterbi_sse.c).
BTW: I forgot to change commit author :(
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Patch Set 2:
(1 comment)
https://gerrit.osmocom.org/#/c/2454/2//COMMIT_MSG
Commit Message:
Line 11: is the minimal requirement. SSE4.1 and AVX2 are used if available.
Do you mean this patch introduces a mandatory requirement for SSE3 capable
CPUs? if so, it is not acceptable.
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Patch Set 7: Code-Review+2
deferring to Tom's judgement here, but generally it looks fine to me, and if
there are issues remaining, they can be adressed later on.
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Hello Jenkins Builder,
I'd like you to reexamine a change. Please visit
https://gerrit.osmocom.org/2454
to look at the new patch set (#2).
core/conv: add x86 SSE support for Viterbi decoder
Fast convolutional decoding is provided through x86 intrinsic based
SSE operations. SSE3, found on
Review at https://gerrit.osmocom.org/2453
configure.ac: add SIMD detection capabilities
This change adds a new configure flag, which triggers a check
whether compiller supports some SIMD (Single Instruction,
Multiple Data) instructions. The check macro is based on
the AX_EXT from
Review at https://gerrit.osmocom.org/2454
core/conv: add x86 SSE support for Viterbi decoder
Fast convolutional decoding is provided through x86 intrinsic based
SSE operations. SSE3, found on virtually all modern x86 processors,
is the minimal requirement. SSE4.1 and AVX2 are used if
Patch Set 3: Code-Review+1
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Patch Set 3: Code-Review+1
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Patch Set 4: Code-Review+1
(2 comments)
https://gerrit.osmocom.org/#/c/2102/4/config/ax_ext.m4
File config/ax_ext.m4:
Line 22: # HAVE_MMX / HAVE_SSE / HAVE_SSE2 / HAVE_SSE3 / HAVE_SSSE3 /
HAVE_SSE4.1 / HAVE_SSE4.2 / HAVE_AVX
Now we have only HAVE_SSE3 and HAVE_SSE4.1, right?
So, it would
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