Torbjörn Granlund writes:
> This all means that on Risc V, multi-word subtraction could be made to
> at 2 cycles/word while multi-word addition is limited to 3 cycles/word,
> in both cases assuming a very wide super-scalar core. Remember that
> other concurrent CPUs do these in 1+epsilon cycles/
Marco Bodrato writes:
> While looking at this e-mail on gmp-bugs, I added DOS support and also
> reordered the branches around the exit code.
> Do you agree with those changes?
Looks reasonable to me. To be honest, it's a bit difficult to follow, it
seems I didn't document this that well when I
Ciao Niels,
you are the author of this code.
Il 2020-06-07 21:48 Idigger Lee ha scritto:
Please update addaddmul_1msb0.asm to support ABI in mingw64.
While looking at this e-mail on gmp-bugs, I added DOS support and also
reordered the branches around the exit code.
Do you agree with those c
