Torsten Mohr <[EMAIL PROTECTED]> writes:
> i use automatic dependency generation in a project. I'd like to
> speed things up and add a target that updates all the dependency
> files "in one step" and for that hand a list of source files
> to an external program for which there are no dependency f
Jonathan Baccash <[EMAIL PROTECTED]> writes:
> Some commands create more than one result, and make (3.81beta3)
> behaves funny when I try to account for this. For example:
>
> #-
> a: b
> touch a
>
> b: c
>
> c: d
> touch c
> touch b
> #-
There is nothin
Torsten Mohr <[EMAIL PROTECTED]> writes:
> LIST := abc.c # a plain C file
> LIST += def.cl # will be checked with LINT
> LIST += ghi.cm # file will be specially tested
> LIST += jkl.cr # file needs to be reviewed
> LIST += mno.clmr # all the above
>
> LIST_C = $(filter_for_c $(LIST))
> LIST_L = $
Boris Kolpackov wrote:
If you really need to update several targets at once (i.e., they cannot
be rewritten as separate rules) then you will need to use implicit rules
for this.
Often the need for multiple targets originates from attempts to
compile Java.
I'd be curious to know if the change
Alessandro Vesely <[EMAIL PROTECTED]> writes:
> I'd be curious to know if the changes done for 3.81, e.g. second
> expansion, made it easier or more difficult to possibly implement
> that feature.
I don't see how the second expansion would be useful in solving this.
The second expansion is used i
Boris Kolpackov wrote:
You probably mean *built-in* implicit rules here:
.SUFFIXES:
ifeq ($(filter -r,$(MAKEFLAGS)),)
MAKEFLAGS += -r
endif
That'll work but note that '-r' will not necessarily appear in MAKEFLAGS
because of the 'interesting' way in which MAKEFLAGS is created.
Consider for e
Torsten Mohr wrote:
i use automatic dependency generation in a project. I'd like to
speed things up and add a target that updates all the dependency
files "in one step" and for that hand a list of source files
to an external program for which there are no dependency files.
Is it possible to gen
Torsten Mohr wrote:
LIST := abc.c # a plain C file
LIST += def.cl # will be checked with LINT
LIST += ghi.cm # file will be specially tested
LIST += jkl.cr # file needs to be reviewed
LIST += mno.clmr # all the above
LIST_C = $(filter_for_c $(LIST))
LIST_L = $(filter_for_l $(LIST))
You could
Jonathan Baccash wrote:
Some commands create more than one result, and make (3.81beta3)
behaves funny when I try to account for this. For example:
#-
a: b
touch a
b: c
c: d
touch c
touch b
#-
Now, if file d exists, this works fine the first tim
%% Torsten Mohr <[EMAIL PROTECTED]> writes:
tm> Is it possible to generate a list of source files for which there
tm> are no dependency files?
Not sure exactly what you mean, but if you mean a list of make targets
for which there are no prerequisites defined in make, then no, there's
no way t
%% Torsten Mohr <[EMAIL PROTECTED]> writes:
tm> When i give the command line option "-r" this does not happen.
There are two types of predefined rules: traditional make suffix rules,
and GNU make pattern rules. The .SUFFIXES: empty target will get rid of
the traditional make suffix rules but d
Boris Kolpackov wrote:
Alessandro Vesely <[EMAIL PROTECTED]> writes:
I'd be curious to know if the changes done for 3.81, e.g. second
expansion, made it easier or more difficult to possibly implement
that feature.
I don't see how the second expansion would be useful in solving this.
I thoug
> > Some commands create more than one result, and make (3.81beta3)
> > behaves funny when I try to account for this. For example:
> >
> > #-
> > a: b
> > touch a
> >
> > b: c
> >
> > c: d
> > touch c
> > touch b
> > #-
>
> There is nothing funny about thi
%% Jonathan Baccash <[EMAIL PROTECTED]> writes:
jb> Ok, in my attempt to dumb down the example, I guess I dumbed it down a
jb> bit too much In reality, the command I'm running is lib.exe, which
jb> comes with the visual studio compiler. When I run lib /DEF:my.def,
jb> the outputs crea
Hi,
> I suggest you check out $(filter ) and $(filter-out ) built-in functions
> in the GNU make manual.
thanks for the hint. I know of these functions, but i can't use them
here:
LL := a.c b.cs c.ls
L_C := $(filter %.c,$(LL))
all:
echo $(L_C)
The Makefile above shows "a.c", but not
Hi,
> > Is it possible to generate a list of source files for which there
> > are no dependency files?
>
> Does your Makefile have the two lists (one of source files and one of
> dependency files)?
yes, the list of dependencies is generated from the list of source files
by changing the directory
Hi,
thanks for that hint, but:
> > LIST := abc.c # a plain C file
> > LIST += def.cl # will be checked with LINT
> > LIST += ghi.cm # file will be specially tested
> > LIST += jkl.cr # file needs to be reviewed
> > LIST += mno.clmr # all the above
> >
> > LIST_C = $(filter_for_c $(LIST))
> > LIS
Torsten Mohr wrote:
You could define LIST_C and LIST_L like this:
LIST_C = $(filter %.c,$(LIST))
LIST_L = $(filter %.l,$(LIST))
This does not work for me, %.c seems to only match a file name
that ends with a single "c". I'd like to also match "cl".
Well you could do
LIST_C = $(filter %.c %
%% John Graham-Cumming <[EMAIL PROTECTED]> writes:
jg> Torsten Mohr wrote:
>>> You could define LIST_C and LIST_L like this:
>>>
>>> LIST_C = $(filter %.c,$(LIST))
>>> LIST_L = $(filter %.l,$(LIST))
>>
>> This does not work for me, %.c seems to only match a file name
>> that end
Hello all,
I want to use the same rule for compiling both C and C++ files. Since I
have a compiler with some peculiarities I cannot get away with just
changing some variables and rely on the default rules.
Basically, instead of writing
%.o: %.c
%.o: %.cpp
I want to write some
On Wed, Oct 05, 2005 at 09:44:07PM +0200, Stefan Karlsson wrote:
> Hello all,
>
> I want to use the same rule for compiling both C and C++ files. Since I
> have a compiler with some peculiarities I cannot get away with just
> changing some variables and rely on the default rules.
>
> Basically,
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