Re: [Intel-gfx] [PATCH v2] drm/i915: Fix eDP blank screen after S3 resume on HP desktops

Am Donnerstag, den 21.06.2012, 15:30 +0200 schrieb Takashi Iwai: > This patch fixes the problem on some HP desktop machines with eDP > which give blank screens after S3 resume. > > It turned out that BLC_PWM_CPU_CTL must be written after > BLC_PWM_CPU_CTL2. Otherwise it doesn't take effect on the

Re: [Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard wrote: > Jesse Barnes writes: > > > High frequency link configurations have the potential to cause trouble > > with long and/or cheap cables, so prefer slow and wide configurations > > instead. This patch has the potential to cause trouble for e

Re: [Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

On Fri, 2012-06-22 at 10:05 +0100, Chris Wilson wrote: > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard wrote: > > Jesse Barnes writes: > > > > > High frequency link configurations have the potential to cause trouble > > > with long and/or cheap cables, so prefer slow and wide configurations

Re: [Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

On Fri, 22 Jun 2012 10:05:19 +0100 Chris Wilson wrote: > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard wrote: > > Jesse Barnes writes: > > > > > High frequency link configurations have the potential to cause trouble > > > with long and/or cheap cables, so prefer slow and wide configuration

Re: [Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

Chris Wilson writes: > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard wrote: > It was structured to minimise lane count because certain chipsets did > not wire up all the lanes, right? Is that still relevant as we are using > the advertised max_lane_count from the DPCD now? We've always use

Re: [Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

Jesse Barnes writes: > In embedded applications, some of the lanes may not exist, but the DPCD > should indicate that (though as Keith says, some lie about it). But if > we set aside eDP it may be safe... Yeah, that's my thinking. We should probably include eDP hooked up to the PCH DP lanes (fo

Re: [Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

On Fri, 22 Jun 2012 10:40:22 -0700, Keith Packard wrote: > Chris Wilson writes: > > > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard wrote: > > > It was structured to minimise lane count because certain chipsets did > > not wire up all the lanes, right? Is that still relevant as we are usin

[Intel-gfx] Ivy Bridge open source programming manuals are now available

Hi folks, Intel Open Source HD Graphics Programmer's Reference Manuals (PRMs) for 2012 Intel Core Processor Family (codenamed Ivy Bridge) are now available at http://intellinuxgraphics.org/documentation.html. Have fun :). -- Eugeni Dodonov __

Re: [Intel-gfx] GMA 950 Intel 945G gallium driver

On Sun, Jun 3, 2012 at 5:44 AM, Emam Hossain wrote: > Hello Everyone, > > Recently I have tested one of my old desktop which got Intel 945G on a > Dual Core CPU. I have installed Ubuntu 11.10 with XServer 1.11, kernel 3.2 > and xf86-video-intel 2.18. > > What I have found that Gallium driver i915

Re: [Intel-gfx] GMA 950 Intel 945G gallium driver

On 2012-06-22 11:18-0700 Stéphane Marchesin wrote: On Sun, Jun 3, 2012 at 5:44 AM, Emam Hossain wrote: Hello Everyone, Recently I have tested one of my old desktop which got Intel 945G on a Dual Core CPU. I have installed Ubuntu 11.10 with XServer 1.11, kernel 3.2 and xf86

Re: [Intel-gfx] GMA 950 Intel 945G gallium driver

On Fri, Jun 22, 2012 at 12:41 PM, Alan W. Irwin wrote: > On 2012-06-22 11:18-0700 Stéphane Marchesin wrote: > > >> >> On Sun, Jun 3, 2012 at 5:44 AM, Emam Hossain >> wrote: >> Hello Everyone, >> >> Recently I have tested one of my old desktop which got Intel 945G on >> a Dual Core CPU.

Re: [Intel-gfx] [PATCH] drm/i915: rip out the PM_IIR WARN

On Thu, Jun 21, 2012 at 02:55:22PM +0200, Daniel Vetter wrote: > After banging my head against this for the past few months, I still > don't see how this could possible race under the premise that once an > irq bit is masked in PM_IMR and reset in PM_IIR it won't show up again > until we unmask it

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix eDP blank screen after S3 resume on HP desktops

On Thu, Jun 21, 2012 at 03:30:41PM +0200, Takashi Iwai wrote: > This patch fixes the problem on some HP desktop machines with eDP > which give blank screens after S3 resume. > > It turned out that BLC_PWM_CPU_CTL must be written after > BLC_PWM_CPU_CTL2. Otherwise it doesn't take effect on these

Re: [Intel-gfx] [PATCH] drm/i915: expose energy counter on SNB and IVB

On Wed, 20 Jun 2012 14:48:58 -0700 Jesse Barnes wrote: > On SNB and IVB, there's an MSR (also exposed through MCHBAR) we can use > to read out the amount of energy used over time. Expose this in sysfs > to make it easy to do power comparisons with different configurations. > > If the platform s