Re: [Intel-gfx] [PATCH 01/10] drm/i915: don't save/restore DSPARB on gen5+

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Because the register does not exist in gen5+. This patch solves unclaimed register messages on Haswell after suspend/resume. Reviewed-by: Jani Nikula jani.nik...@intel.com

Re: [Intel-gfx] [PATCH 02/10] drm/i915: don't read DP_TP_STATUS(PORT_A)

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Our documentation is wrong, this register does not exist on port A, so sleep 800us since it's the timeout mentioned on the mode set sequence document. Would be nice to have some reference,

Re: [Intel-gfx] [PATCH 2/2] drm/i915: fixup per-crtc locking in intel_release_load_detect_pipe

On Wed, Jan 23, 2013 at 05:25:09PM +0100, Daniel Vetter wrote: One of the early return cases missed the mutex unlocking. Hilarity ensued. This regression has been introduced in commit 7b24056be6db7ce907baffdd4cf142ab774ea60c Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Wed Dec 12

Re: [Intel-gfx] [PATCH 03/10] drm/i915: fix intel_init_power_wells

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com The current code was wrong in many different ways, so this is a full rewrite. We don't have different power wells for different parts of the GPU, we have a single power well, but we have

Re: [Intel-gfx] [PATCH 08/10] drm/i915: set TRANSCODER_EDP even earlier

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Instead of setting it at the beginning of haswell_crtc_mode_set, let's set it at the beginning of intel_crtc_mode_set. When intel_crt_mode_set calls drm_vblank_pre_modeset we already need

Re: [Intel-gfx] [PATCH 09/10] drm/i915: print IVB/HSW display error interrupts

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com If we get one of these messages it means we did something wrong, and the first step to fix wrong things is to detect them and recognize they exist. For now, leave these messages as

Re: [Intel-gfx] [PATCH 09/10] drm/i915: print IVB/HSW display error interrupts

On Fri, 18 Jan 2013, Ben Widawsky b...@bwidawsk.net wrote: On Fri, Jan 18, 2013 at 06:29:11PM -0200, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com If we get one of these messages it means we did something wrong, and the first step to fix wrong things is to detect them and

Re: [Intel-gfx] [PATCH 04/10] drm/i915: dynamic Haswell display power well support

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Daniel Vetter daniel.vet...@ffwll.ch We can disable (almost) all the display hw if we only use pipe A, with the integrated edp transcoder on port A. Because we don't set the cpu transcoder that early (yet), we need to help us

Re: [Intel-gfx] [PATCH 07/10] drm/i915: turn on the power well before suspending

On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Our suspend code touches a lot of registers all over the place, so we need to enable the power well before suspending. Reviewed-by: Jani Nikula jani.nik...@intel.com Signed-off-by: Paulo

[Intel-gfx] [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG()

Hi Daniel, Here's the proper kill IS_DISPLAYREG() series, based on the feedback to the RFC. Hopefully I managed to address most of the comments. Changes since the RFC: - split the monster patch into small chunks - s/mmio_offset/display_mmio_offset - use enum port in hdmi/dp code - VLV only

[Intel-gfx] [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port

From: Ville Syrjälä ville.syrj...@linux.intel.com Use intel_dig_port-port rather than intel_hdmi-sdvox_erg. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 27 +++ 1 file changed, 15 insertions(+), 12 deletions(-) diff

[Intel-gfx] [PATCH 02/33] drm/i915: Convert intel_dp to enum port

From: Ville Syrjälä ville.syrj...@linux.intel.com Use intel_dig_port-port rather than intel_dp-output_reg. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info

From: Ville Syrjälä ville.syrj...@linux.intel.com Add an optional offset to intel_device_info, which will added to most display register offsets. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git

[Intel-gfx] [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is for VLV only

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 10/33] drm/i915: Primary plane registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 11/33] drm/i915: Pipe registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 12/33] drm/i915: Cursor registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com CURSIZE is not present on VLV, so it was left out, as were the IVB specific cursor B registers. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 12 ++-- 1 file changed, 6 insertions(+), 6

[Intel-gfx] [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 15/33] drm/i915: DSPARB register needs an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 18/33] drm/i915: Panel fitter registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 19/33] drm/i915: PORT_HOTPLUG registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code

From: Ville Syrjälä ville.syrj...@linux.intel.com ADPA doesn't include the required offset, so don't use it in VLV specific code. VLV_ADPA must be used instead. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_crt.c | 6 +++--- 1 file changed, 3

[Intel-gfx] [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers

From: Ville Syrjälä ville.syrj...@linux.intel.com Don't touch VGA0/VGA1/VGA_PD in suspend/resume paths. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_suspend.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git

[Intel-gfx] [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable

From: Ville Syrjälä ville.syrj...@linux.intel.com Instead of 0x18 use (VLV_DISPLAY_BASE + ). Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers

From: Ville Syrjälä ville.syrj...@linux.intel.com Instead of 0x18 use (VLV_DISPLAY_BASE + ). Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[Intel-gfx] [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH 29/33] drm/i915: VGA registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 38 +++--- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com This will cause display registers to include the correct offset on VLV. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Intel-gfx] [PATCH 30/33] drm/i915: GPIO/GMBUS registers need an offset on VLV

From: Ville Syrjälä ville.syrj...@linux.intel.com GPIO/GMBUS registers must be offset on VLV, so simply adjust gpio_mmio_base to include the correct offset. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_i2c.c | 2 ++ 1 file changed, 2 insertions(+)

[Intel-gfx] [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG()

From: Ville Syrjälä ville.syrj...@linux.intel.com All display registers should now include the proper offset on VLV. That means IS_DISPLAYREG() is now useless, and we can eliminate it. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.c | 104

[Intel-gfx] [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers

From: Ville Syrjälä ville.syrj...@linux.intel.com Apart from VLV_IIR_RW all the VLV interrupt registers are the same as on pre-PCH platforms. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--- drivers/gpu/drm/i915/i915_irq.c | 44

Re: [Intel-gfx] [PATCH 01/10] drm/i915: don't save/restore DSPARB on gen5+

On Thu, Jan 24, 2013 at 11:26:13AM +0200, Jani Nikula wrote: On Fri, 18 Jan 2013, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Because the register does not exist in gen5+. This patch solves unclaimed register messages on Haswell after

[Intel-gfx] [PATCH 0/4] gtt abstractions

Hi all, Whith Ben wrestling the gtt code and trying to finally wear us off the intel-gtt fix I've figured I might as well drop my idea for how we could better organize the pte writing/clearing. With these patches there's no a clean cut between the code which manages the address spaces and the

[Intel-gfx] [PATCH 1/4] drm/i915: vfuncs for gtt_clear_range/insert_entries

We have a few too many differences between platforms here, so finally take the prepared abstraction and run with it. A few smaller changes are required to get things into shape: - Move i915_cache_level up since we need it in the gt funcs. - Split up i915_ggtt_clear_range and move the two

[Intel-gfx] [PATCH 3/4] drm/i915: pte_encode is gen6+

All the other gen6+ hw code has the gen6_ prefix, so be consistent about it. Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_gem_gtt.c | 24 ++-- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git

[Intel-gfx] [PATCH 2/4] drm/i915: vfuncs for ppgtt

Like for the global gtt we want a notch more flexibility here. Only big change (besides a few tiny function parameter adjustments) was to move gen6_ppgtt_insert_entries up (and remove _sg_ from its name, we only have one kind of insert_entries since the last gtt cleanup). A follow-up patch will

[Intel-gfx] [PATCH 4/4] drm/i915: extract hw ppgtt setup/cleanup code

At the moment only cosmetics, but being able to initialize/cleanup arbitrary ppgtt address spaces paves the way to have more than one of them ... Just in case we ever get around to implementing real per-process address spaces. Note that in that case another vfunc for ppgtt initialization would be

Re: [Intel-gfx] [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port

Hi 2013/1/24 ville.syrj...@linux.intel.com: From: Ville Syrjälä ville.syrj...@linux.intel.com Use intel_dig_port-port rather than intel_hdmi-sdvox_erg. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Possible optional suggestions: - Create macros that receive port as argument

Re: [Intel-gfx] [PATCH 02/33] drm/i915: Convert intel_dp to enum port

Hi 2013/1/24 ville.syrj...@linux.intel.com: From: Ville Syrjälä ville.syrj...@linux.intel.com Use intel_dig_port-port rather than intel_dp-output_reg. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 9 + 1 file changed, 5

[Intel-gfx] Monitors on thunderbolt? (Was: Question about driver capatibilities - triple monitor?)

At 2013-01-23 13:02, Daniel Vetter wrote: tbh I have no idea whether you can actually by hw which supports 2x DP out, it's certainly no common. The description was only from the hw pov. It might be that the 2x thunderbolt works, otoh I've never tested thunderbolt so I have no idea how well (or

Re: [Intel-gfx] [PATCH 0/4] gtt abstractions

On Thu, 24 Jan 2013 16:50:11 +0100 Daniel Vetter daniel.vet...@ffwll.ch wrote: Hi all, Whith Ben wrestling the gtt code and trying to finally wear us off the intel-gtt fix I've figured I might as well drop my idea for how we could better organize the pte writing/clearing. With these

Re: [Intel-gfx] circular locking warning during suspend

On Thu, Jan 24, 2013 at 6:34 PM, Johannes Berg johan...@sipsolutions.net wrote: Hi, I didn't find this reported, but maybe it has been, I didn't search for too long. I'm using 3.8.0-rc4 (plus wireless bits), and lockdep is unhappy. Note that I am booting with no_console_suspend. Patches for

Re: [Intel-gfx] external screen goes black

Any further thoughts on this issue? On Sun, Jan 20, 2013 at 1:17 PM, Jonathan Adamczewski jonathan.adamczew...@gmail.com wrote: Yanking and re-plugging the DP cable did work when I tried it. My recollection is that there have been times when it hasn't worked, though it's possible there was

Re: [Intel-gfx] external screen goes black

On Thu, Jan 24, 2013 at 9:16 PM, Jonathan Adamczewski jonathan.adamczew...@gmail.com wrote: Any further thoughts on this issue? Please file a bug report about your issue on bugs.freedesktop.org against DRI - DRM/Intel with a summary of the findings thus far. We know that we don't yet have

Re: [Intel-gfx] [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV

On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com It's true that we safe/restore these suckers across suspend/resume, but I have no idea why or whether we

Re: [Intel-gfx] [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV

On Thu, Jan 24, 2013 at 03:29:34PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com We already have a switch since VGACNTRL moved around on pch-split platforms, too. To avoid confusion with

Re: [Intel-gfx] [PATCH 15/33] drm/i915: DSPARB register needs an offset on VLV

On Thu, Jan 24, 2013 at 03:29:40PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com With Paulo's patch to no longer safe/resume DSPARB on gen4+ gone, there's no user of this left for vlv.

Re: [Intel-gfx] [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV

On Thu, Jan 24, 2013 at 03:29:42PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com When passing the DP/HDMI/SDVO registers to the encoder init functions, include the VLV specific offset in the value. Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code

On Thu, Jan 24, 2013 at 03:29:45PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com ADPA doesn't include the required offset, so don't use it in VLV specific code. VLV_ADPA must be used instead. Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV

On Thu, Jan 24, 2013 at 03:29:47PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com I've noticed that the PALETTE moved around a bit for pch-split platforms already, but otoh the palette

Re: [Intel-gfx] [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers

On Thu, Jan 24, 2013 at 03:29:49PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Don't touch VGA0/VGA1/VGA_PD in suspend/resume paths. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com By sheer coincidence I'm working on a few

Re: [Intel-gfx] [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV

On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 14 +++--- 1 file changed, 7 insertions(+), 7

Re: [Intel-gfx] [PATCH 29/33] drm/i915: VGA registers need an offset on VLV

On Thu, Jan 24, 2013 at 03:29:54PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Admittedly I haven't checked them closely, but with my proposed patch in he modeset_s-r branch, do we

[Intel-gfx] [PATCH 1/6] drm/i915: vfuncs for gtt_clear_range/insert_entries

From: Daniel Vetter daniel.vet...@ffwll.ch We have a few too many differences here, so finally take the prepared abstraction and run with it. A few smaller changes are required to get things into shape: - move i915_cache_level up since we need it in the gt funcs - split up i915_ggtt_clear_range

[Intel-gfx] [PATCH 2/6] drm/i915: vfuncs for ppgtt

From: Daniel Vetter daniel.vet...@ffwll.ch Like for the global gtt we want a notch more flexibility here. Only big change (besides a few tiny function parameter adjustments) was to move gen6_ppgtt_insert_entries up (and remove _sg_ from its name, we only have one kind of insert_entries since the

[Intel-gfx] [PATCH 3/6] drm/i915: pte_encode is gen6+

From: Daniel Vetter daniel.vet...@ffwll.ch All the other gen6+ hw code has the gen6_ prefix, so be consistent about it. Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_gem_gtt.c | 24 ++-- 1 file changed, 14 insertions(+), 10 deletions(-)

[Intel-gfx] [PATCH 4/6] drm/i915: extract hw ppgtt setup/cleanup code

From: Daniel Vetter daniel.vet...@ffwll.ch At the moment only cosmetics, but being able to initialize/cleanup arbitrary ppgtt address spaces paves the way to have more than one of them ... Just in case we ever get around to implementing real per-process address spaces. Note that in that case

[Intel-gfx] [PATCH 5/6] drm/i915: Add probe and remove to the gtt ops

The idea, and much of the code came originally from: commit 0712f0249c3148d8cf42a3703403c278590d4de5 Author: Ben Widawsky b...@bwidawsk.net Date: Fri Jan 18 17:23:16 2013 -0800 drm/i915: Create a vtable for i915 gtt Daniel didn't like the color of that patch series, and so I asked him to

[Intel-gfx] [PATCH 6/6] drm/i915: Resume dissecting intel_gtt

With the probe call in our dispatch table, we can now cut away two of the remaining members in the intel_gtt shared struct. v2: Rebased on top of Daniel's series Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/char/agp/intel-gtt.c | 36 --

Re: [Intel-gfx] [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV

On Thu, Jan 24, 2013 at 03:29:56PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com This will cause display registers to include the correct offset on VLV. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Ok, applied most patches up

Re: [Intel-gfx] [PATCH V3 3/3] i915: introduce modeset_on_resume

On 2013.01.24 19:49:40 +0800, Zhang Rui wrote: I need some graphics experts' comments before sending it out. Please send to intel-gfx@lists.freedesktop.org for i915 specific issue. On Thu, 2013-01-24 at 19:43 +0800, Zhang Rui wrote: i915 driver needs to do modeset when 1. system resumes