Re: [Intel-gfx] [PATCH] intel-decode: Fix gen6 HIER_DEPTH_BUFFER decoding

2013-04-03 Thread Eric Anholt
Daniel Vetter writes: > It accidentally used the cmd id for the gen7 command and had an > outdated lenght field. Spotted while trying to make sense of an ivb > error_state from mesa 7.11 ... Reviewed-by: Eric Anholt pgpFNtB_upuPa.pgp Description: PGP signature

Re: [Intel-gfx] [PATCH 12/13] drm/i915: fix DP get_hw_state return value

2013-04-03 Thread Jesse Barnes
On Thu, 4 Apr 2013 01:15:28 +0200 Daniel Vetter wrote: > On Tue, Apr 02, 2013 at 08:11:05PM +0200, Daniel Vetter wrote: > > On Tue, Apr 02, 2013 at 10:03:56AM -0700, Jesse Barnes wrote: > > > If we couldn't find a pipe we shouldn't return true. This might be even > > > better as a WARN though, s

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Ben Widawsky
On Wed, Apr 03, 2013 at 01:41:05PM -0700, Ben Widawsky wrote: > On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > > So I've checked hsw bspec and the problem is that hw guys again > > > changed the bits around a bit, and I t

Re: [Intel-gfx] [PATCH] drm/i915: re-add eDP bpp clamping notice

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 11:03:02PM +0200, Daniel Vetter wrote: > This has been lost in my recent bpp handling rework in > > commit 4e53c2e010e531b4a014692199e978482d471c7e > Author: Daniel Vetter > Date: Wed Mar 27 00:44:58 2013 +0100 > > drm/i915: precompute pipe bpp before touching the h

Re: [Intel-gfx] [PATCH 12/13] drm/i915: fix DP get_hw_state return value

2013-04-03 Thread Daniel Vetter
On Thu, Apr 04, 2013 at 01:15:28AM +0200, Daniel Vetter wrote: > On Tue, Apr 02, 2013 at 08:11:05PM +0200, Daniel Vetter wrote: > > On Tue, Apr 02, 2013 at 10:03:56AM -0700, Jesse Barnes wrote: > > > If we couldn't find a pipe we shouldn't return true. This might be even > > > better as a WARN tho

Re: [Intel-gfx] [PATCH 12/13] drm/i915: fix DP get_hw_state return value

2013-04-03 Thread Daniel Vetter
On Tue, Apr 02, 2013 at 08:11:05PM +0200, Daniel Vetter wrote: > On Tue, Apr 02, 2013 at 10:03:56AM -0700, Jesse Barnes wrote: > > If we couldn't find a pipe we shouldn't return true. This might be even > > better as a WARN though, since it should be impossible to have the port > > enabled without

[Intel-gfx] 3.8.2, intel 2.21.5: drm:i915_hangcheck_hung with VAAPI

2013-04-03 Thread Jochen Heuer
Hello everyone, I am running VDR (digital videorecoder) with plugin softhddevice (to output video via VAAPI to X11) on a second X server (:1.0) and sometimes the video freezes. Then I see the following messages in dmesg: [202828.719109] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 07:06:01PM +0200, Daniel Vetter wrote: > On Wed, Apr 03, 2013 at 01:08:16PM +0300, Jani Nikula wrote: > > On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > > > Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the > >

[Intel-gfx] [PATCH] drm/i915: re-add eDP bpp clamping notice

2013-04-03 Thread Daniel Vetter
This has been lost in my recent bpp handling rework in commit 4e53c2e010e531b4a014692199e978482d471c7e Author: Daniel Vetter Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw Cc: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/

Re: [Intel-gfx] GPU Hang in Intel Driver

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 04:54:31PM -0400, Dihan Wickremasuriya wrote: > mesa 8.0.4-r1, libdrm 2.4.43 and xf86-video-intel 2.21.5 on top of kernel > 3.8.5 seems to work well. No hangs or crashes so far. Thank you very much > for your help with this! > > Would you also happen to know where I can g

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Ben Widawsky
On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > So I've checked hsw bspec and the problem is that hw guys again > > changed the bits around a bit, and I think on HSW we actually want > > (0x8 << 3) instead of what's currentl

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > So I've checked hsw bspec and the problem is that hw guys again > changed the bits around a bit, and I think on HSW we actually want > (0x8 << 3) instead of what's currently there. Meh, I've screwed up reading the tables, 0x3 << 3 is what we

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 9:17 PM, Kenneth Graunke wrote: > On 04/03/2013 11:06 AM, Ben Widawsky wrote: >> >> Apparently these ECOCHK bits changed on HSW and the behavior is not what >> we want. I've not been able to find VLV definition specifically so I'll >> assume it's the same as IVB. >> >> (Only

Re: [Intel-gfx] [v3.8 Regression] Merge tag 'v3.7-rc2' into drm-intel-next-queued

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 9:08 PM, Joseph Salisbury < joseph.salisb...@canonical.com> wrote: > Hi Daniel, > > A bug was opened against the Ubuntu kernel[0]. After a kernel bisect, it > was found the following was the first bad commit: > > > commit c2fb7916927e989ea424e61ce5fe61**7e54878827 > Merge:

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Kenneth Graunke
On 04/03/2013 11:06 AM, Ben Widawsky wrote: Apparently these ECOCHK bits changed on HSW and the behavior is not what we want. I've not been able to find VLV definition specifically so I'll assume it's the same as IVB. (Only compile tested) Reported-by: Kenneth Graunke Signed-off-by: Ben Widaws

[Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Ben Widawsky
Apparently these ECOCHK bits changed on HSW and the behavior is not what we want. I've not been able to find VLV definition specifically so I'll assume it's the same as IVB. (Only compile tested) Reported-by: Kenneth Graunke Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c |

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Don't use the HDMI port color range bit on Valleyview

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 12:33:31PM +0300, Jani Nikula wrote: > On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > VLV docs still list the the color range selection bit for the HDMI > > ports, but for DP ports it has been repurposed. > > > > I have no idea whe

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 01:08:16PM +0300, Jani Nikula wrote: > On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the > > <=Gen4/VLV code follow the same pattern as the Gen5+ codepaths. > > Revi

Re: [Intel-gfx] [PATCH 1/2] [v3] drm/i915: reference count for i915_hw_contexts

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 12:56:11PM +0100, Chris Wilson wrote: > On Tue, Apr 02, 2013 at 06:27:00PM -0700, Ben Widawsky wrote: > > On Tue, Apr 02, 2013 at 03:45:42PM -0700, Ben Widawsky wrote: > > > From: Mika Kuoppala > > > > > > In preparation to do analysis of which context was > > > guilty of

[Intel-gfx] [PATCH] intel-decode: Fix gen6 HIER_DEPTH_BUFFER decoding

2013-04-03 Thread Daniel Vetter
It accidentally used the cmd id for the gen7 command and had an outdated lenght field. Spotted while trying to make sense of an ivb error_state from mesa 7.11 ... Signed-off-by: Daniel Vetter --- intel/intel_decode.c |2 +- intel/tests/gen6-3d.batch-ref.txt |6 +++--- 2 file

Re: [Intel-gfx] GPU Hang in Intel Driver

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 5:58 PM, Dihan Wickremasuriya < dwickremasur...@rethinkrobotics.com> wrote: > Thanks for the quick response and adding the mailing list. I did in fact > attach the error_state in my original mail. Please let me know if it's not > the one you were looking for (re-attached). >

Re: [Intel-gfx] (no subject)

2013-04-03 Thread Daniel Vetter
Hi all, Two things: - Please _always_ include a public mailing list when reporting bugs, your dear maintainer sometimes slacks off. - We need to see the error_state before we can assess what kind of hang you have (it's like gettting a SIGSEGV for a normal program, no two gpu hangs are the same ...

[Intel-gfx] [PATCH] drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900

2013-04-03 Thread Christian Lamparter
The "Mobile Sandy Bridge CPUs" in the Fujitsu Esprimo Q900 mini desktop PCs are probably misleading the LVDS detection code in intel_lvds_supported. Nothing is connected to the LVDS ports in these systems. Signed-off-by: Christian Lamparter --- drivers/gpu/drm/i915/intel_lvds.c |8

[Intel-gfx] [PATCH] drm/i915: drop the coditional mutex

2013-04-03 Thread Sebastian Andrzej Siewior
mutex_is_locked_by() checks the owner of the lock against current. This is done by accessing a private member of struct mutex which works on mainline but does not on RT. I did not figure out, why this "lock-owner-check" and the "lock stealing flag" is required. If the lock can not be acquire the lo

Re: [Intel-gfx] [PATCH] drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 02:34:11PM +0200, Christian Lamparter wrote: > The "Mobile Sandy Bridge CPUs" in the Fujitsu Esprimo Q900 > mini desktop PCs are probably misleading the LVDS detection > code in intel_lvds_supported. Nothing is connected to the > LVDS ports in these systems. > > Signed-off-

Re: [Intel-gfx] [PATCH 3/4] drm/i915: enable VT switchless resume v3

2013-04-03 Thread Jesse Barnes
On Wed, 3 Apr 2013 11:54:23 +0100 Chris Wilson wrote: > On Wed, Apr 03, 2013 at 11:15:40AM +0200, Daniel Vetter wrote: > > On Tue, Mar 26, 2013 at 09:25:45AM -0700, Jesse Barnes wrote: > > > With the other bits in place, we can do this safely. > > > > > > v2: disable backlight on suspend to prev

Re: [Intel-gfx] [PATCH 1/2] [v3] drm/i915: reference count for i915_hw_contexts

2013-04-03 Thread Chris Wilson
On Tue, Apr 02, 2013 at 06:27:00PM -0700, Ben Widawsky wrote: > On Tue, Apr 02, 2013 at 03:45:42PM -0700, Ben Widawsky wrote: > > From: Mika Kuoppala > > > > In preparation to do analysis of which context was > > guilty of gpu hung, store kreffed context pointer > > into request struct. > > > >

Re: [Intel-gfx] [PATCH 3/4] drm/i915: enable VT switchless resume v3

2013-04-03 Thread Chris Wilson
On Wed, Apr 03, 2013 at 11:15:40AM +0200, Daniel Vetter wrote: > On Tue, Mar 26, 2013 at 09:25:45AM -0700, Jesse Barnes wrote: > > With the other bits in place, we can do this safely. > > > > v2: disable backlight on suspend to prevent premature enablement on resume > > v3: disable CRTCs on suspen

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Don't use the HDMI port color range bit on Valleyview

2013-04-03 Thread Jani Nikula
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > VLV docs still list the the color range selection bit for the HDMI > ports, but for DP ports it has been repurposed. > > I have no idea whether the HDMI color range selection bit still works > on VLV, but since we

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Set PIPECONF color range bit on Valleyview

2013-04-03 Thread Jani Nikula
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > VLV has the color range selection bit in the PIPECONF register. > Configure it appropriately. Reviewed-by: Jani Nikula > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_display.c | 7 +++ >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()

2013-04-03 Thread Jani Nikula
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the > <=Gen4/VLV code follow the same pattern as the Gen5+ codepaths. Reviewed-by: Jani Nikula > Signed-off-by: Ville Syrjälä > --- > drivers/gpu

Re: [Intel-gfx] [PATCH 7/8] drm/i915: create pipe_config->dpll for clock state

2013-04-03 Thread Daniel Vetter
On Tue, Apr 02, 2013 at 02:14:23PM -0700, Jesse Barnes wrote: > This one's hard to review since you mixed in a drm_crtc->intel_crtc > function arg change. > > I'd rather have that split out, but it looks ok. Yeah, I've fumbled this one a bit, but decided to punt on the split-up. Generally I'm al

Re: [Intel-gfx] [PATCH 3/4] drm/i915: enable VT switchless resume v3

2013-04-03 Thread Daniel Vetter
On Tue, Mar 26, 2013 at 09:25:45AM -0700, Jesse Barnes wrote: > With the other bits in place, we can do this safely. > > v2: disable backlight on suspend to prevent premature enablement on resume > v3: disable CRTCs on suspend to allow RTD3 (Kristen) > > Signed-off-by: Jesse Barnes Something se

Re: [Intel-gfx] [PATCH] drm/i915: Fix sdvo connector get_hw_state function

2013-04-03 Thread Daniel Vetter
On Tue, Apr 02, 2013 at 09:30:34PM +0200, Daniel Vetter wrote: > The active output is only the currently selected one, which does not > imply that it's actually enabled. Since we don't use the sdvo encoder > side dpms support, we need to check whether the chip-side sdvo port is > enabled instead. >

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree

2013-04-03 Thread Daniel Vetter
On Wed, Apr 03, 2013 at 01:43:49PM +1100, Stephen Rothwell wrote: > Hi all, > > Today's linux-next merge of the drm-intel tree got a conflict in > drivers/gpu/drm/i915/intel_panel.c between commit b1289371fcd5 ("Revert > "drm/i915: write backlight harder"") from Linus' tree and commit > 31ad8ec6a6

Re: [Intel-gfx] [PATCH] drm/i915: Better overclock support

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 4:45 AM, Ben Widawsky wrote: > Most importantly this will allow users to set overclock frequencies in > sysfs. Previously the max was limited by the RP0 max as opposed to the > overclock max. This is useful if one wants to either limit the max > overclock frequency, or set