On Fri, Mar 01, 2013 at 02:08:33PM -0800, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes
Fixed up conflict and applied to dinq.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx m
According to BSpec the link training sequence on HSW port-A should be as
follows:
1. link training: clock recovery
2. link training: equalization
3. display pipe enable
4. link training: disable (set normal mode)
Contrary to this at the moment we do step 4. already after step 2. Fix
this by addin
On Fri, Apr 26, 2013 at 05:45:15PM +0200, Takashi Iwai wrote:
> At Fri, 26 Apr 2013 17:42:07 +0200,
> Daniel Vetter wrote:
> >
> > On Fri, Apr 26, 2013 at 05:12:34PM +0200, Takashi Iwai wrote:
> > > At Fri, 26 Apr 2013 16:57:08 +0200,
> > > Daniel Vetter wrote:
> > > >
> > > > On Fri, Apr 26, 201
At Fri, 26 Apr 2013 17:42:07 +0200,
Daniel Vetter wrote:
>
> On Fri, Apr 26, 2013 at 05:12:34PM +0200, Takashi Iwai wrote:
> > At Fri, 26 Apr 2013 16:57:08 +0200,
> > Daniel Vetter wrote:
> > >
> > > On Fri, Apr 26, 2013 at 07:53:41AM +, Li, Jocelyn wrote:
> > > > -Original Message-
>
On Fri, Apr 26, 2013 at 04:06:06PM +0100, Chris Wilson wrote:
> On Fri, Apr 26, 2013 at 04:46:12PM +0200, Daniel Vetter wrote:
> > On Fri, Apr 26, 2013 at 02:04:25PM +0100, Chris Wilson wrote:
> > > Instead of repeatedly bombarding the user with a request to reboot and
> > > increase the stolen siz
On Fri, Apr 26, 2013 at 05:12:34PM +0200, Takashi Iwai wrote:
> At Fri, 26 Apr 2013 16:57:08 +0200,
> Daniel Vetter wrote:
> >
> > On Fri, Apr 26, 2013 at 07:53:41AM +, Li, Jocelyn wrote:
> > > -Original Message-
> > > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
> > > Sent: Fr
At Fri, 26 Apr 2013 16:57:08 +0200,
Daniel Vetter wrote:
>
> On Fri, Apr 26, 2013 at 07:53:41AM +, Li, Jocelyn wrote:
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
> > Sent: Friday, April 26, 2013 3:25 PM
> > To: Li, Jocelyn
> > Cc: Wang, Xingchao; Zan
On Fri, Apr 26, 2013 at 04:46:12PM +0200, Daniel Vetter wrote:
> On Fri, Apr 26, 2013 at 02:04:25PM +0100, Chris Wilson wrote:
> > Instead of repeatedly bombarding the user with a request to reboot and
> > increase the stolen size with every fb refresh, just inform them the
> > first time only.
> >
On Fri, Apr 26, 2013 at 07:53:41AM +, Li, Jocelyn wrote:
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
> Sent: Friday, April 26, 2013 3:25 PM
> To: Li, Jocelyn
> Cc: Wang, Xingchao; Zanoni, Paulo R; ville.syrj...@linux.intel.com; Lin,
> Mengdong; Girdwood,
On Fri, Apr 26, 2013 at 02:04:25PM +0100, Chris Wilson wrote:
> Instead of repeatedly bombarding the user with a request to reboot and
> increase the stolen size with every fb refresh, just inform them the
> first time only.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_pm.c
From: Chris Wilson
As we recompute the remaining timeout after waiting, there is a
potential for that timeout to be less than zero and so need sanitizing.
The timeout is always returned to userspace and validated, so we should
always perform the sanitation.
v2 [vsyrjala]: Only normalize the time
From: Chris Wilson
As we recompute the remaining timeout after waiting, there is a
potential for that timeout to be less than zero and so need sanitizing.
The timeout is always returned to userspace and validated, so we should
always perform the sanitation.
v2 [vsyrjala]: Only normalize the time
Instead of repeatedly bombarding the user with a request to reboot and
increase the stolen size with every fb refresh, just inform them the
first time only.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/dr
Apart from the two '&' vs. '|' mixups, the series looks all right to me.
Fix those two small things and you can add
Reviewed-by: Ville Syrjälä
for the entire set.
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
ht
On Thu, Apr 25, 2013 at 02:15:25PM -0300, Rodrigo Vivi wrote:
> Display register 46500h bit 23 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: Ville suggested to enable it back when disabling fbc to avoid wasting
> power.
>
> v3: RMW to preserve other
On Thu, Apr 25, 2013 at 02:15:22PM -0300, Rodrigo Vivi wrote:
> Display register 42020h bit 9 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: RMW to preserve other bits (by Ville)
>
> Cc: Ville Syrjälä
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/
Hi Daniel,
Please see my comments below.
Regards,
Jocelyn
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Friday, April 26, 2013 3:25 PM
To: Li, Jocelyn
Cc: Wang, Xingchao; Zanoni, Paulo R; ville.syrj...@linux.intel.com; Lin,
Mengdong; Girdwood, Liam R; int
Summary
We finished a new round of kernel testing. Generally, in this circle, 5 new
bugs are filed, 24 bugs are still opened,2 Duplicated bugs, 2 bugs are closed.
Test Environment
Kernel: (drm-intel-testing) 80ad9206c0d863832bc5f6008c4d1868d1df8e70
Author: Ville Syrjälä
Date: Fri Apr 19 1
On Fri, Apr 26, 2013 at 8:58 AM, Li, Jocelyn wrote:
> Hi Guys,
>
> I apologize that I may have misunderstood on the agreement we have made on
> power well work. I assumed that audio team is expected to create private gfx
> driver API to control the power well between gfx and audio for internal
19 matches
Mail list logo
