From: Adrian Negreanu adrian.m.negre...@intel.com
version.h is -include-ed assuming that builddir is the same
as srcdir;
In file included from command-line:0:0:
./../../tests/../lib/check-ndebug.h:3:1: fatal error:
../../tests/../version.h: No such file or directory
#endif
^
Signed-off-by:
On non-LLC platforms, when changing the cache level of an object, we may
need to unbind it show that prefetching across page boundaries does not
cross into a different memory domain. This requires us to unbind
conflicting vma, but we did so was iterating over the objects vma in an
unsafe manner
On Fri, Mar 21, 2014 at 07:40:56AM +, Chris Wilson wrote:
On non-LLC platforms, when changing the cache level of an object, we may
need to unbind it show that prefetching across page boundaries does not
s/show/so/
cross into a different memory domain. This requires us to unbind
conflicting
Hi,
Could someone clarify how to check HDMI TMDS clock frequency and DisplayPort
link symbol clock frequency?
- Is there some registers which can dump the clock frequency?
- Is 'clock' field in 'struct drm_display_mode' reflect the this clock?
My platform is Haswell,
From: Ville Syrjälä ville.syrj...@linux.intel.com
On SNB the BIOS provided WM memory latency values seem insufficient to
handle high resolution displays.
In this particular case the display mode was a 2560x1440@60Hz, which
makes the pixel clock 241.5 MHz. It was empirically found that a memory
On Fri, Mar 21, 2014 at 11:00:48AM +0200, Jani Nikula wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
On SNB the BIOS provided WM memory latency values seem insufficient to
handle high resolution displays.
In this particular case the display mode was a 2560x1440@60Hz, which
makes
On Fri, Mar 21, 2014 at 09:06:15AM +0200, Adrian Negreanu wrote:
From: Adrian Negreanu adrian.m.negre...@intel.com
version.h is -include-ed assuming that builddir is the same
as srcdir;
In file included from command-line:0:0:
./../../tests/../lib/check-ndebug.h:3:1: fatal error:
On Fri, Mar 21, 2014 at 07:51:58AM +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 07:40:56AM +, Chris Wilson wrote:
On non-LLC platforms, when changing the cache level of an object, we may
need to unbind it show that prefetching across page boundaries does not
s/show/so/
cross into
On 03/20/2014 09:48 PM, Chris Wilson wrote:
As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
debug registers to track the current HEAD of the individual rings, which
may be anywhere within the
During resume the intel hda audio driver depends on the i915 driver
reinitializing the audio power domain. Since the order of calling the
i915 resume handler wrt. that of the audio driver is not guaranteed,
move the power domain reinitialization step to the resume_early
handler. This is guaranteed
On Fri, Mar 21, 2014 at 10:03:38AM +, Tvrtko Ursulin wrote:
On 03/20/2014 09:48 PM, Chris Wilson wrote:
As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
debug registers to track the current HEAD
On Fri, Mar 21, 2014 at 11:00:48AM +0200, Jani Nikula wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
On SNB the BIOS provided WM memory latency values seem insufficient to
handle high resolution displays.
In this particular case the display mode was a 2560x1440@60Hz, which
makes
On 03/21/2014 10:14 AM, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 10:03:38AM +, Tvrtko Ursulin wrote:
On 03/20/2014 09:48 PM, Chris Wilson wrote:
As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
On Fri, 21 Mar 2014, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Mar 21, 2014 at 07:51:58AM +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 07:40:56AM +, Chris Wilson wrote:
On non-LLC platforms, when changing the cache level of an object, we may
need to unbind it show that
On Fri, 2014-02-07 at 12:22 +, Goel, Akash wrote:
From: Akash Goel akash.g...@intel.com
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2: Modified the WA
On Wed, 2014-01-22 at 11:11 +, Chris Wilson wrote:
On Wed, Jan 22, 2014 at 12:54:51PM +0200, Ville Syrjälä wrote:
On Wed, Jan 22, 2014 at 09:15:06AM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added a new rendering specific Workaround
On Fri, Feb 07, 2014 at 05:52:10PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2:
On Fri, Mar 21, 2014 at 10:50:05AM +, Tvrtko Ursulin wrote:
No, think you misunderstood me. I said slightly more defensive
just in the sense that in case of weird hardware failures you have a
potentially infinite loop now, where you don't really need a loop -
probabilities strongly suggest
Broadwell introduces large address spaces, greater than 32bits in width.
These require that we then store and print 64bit values. If we were to
zero pad them out to 16 hexadecimal places, we have to carefully count
the leading zeroes - which is easy to make a mistake. Conversely, if we
do not zero
On 03/21/2014 12:00 PM, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 10:50:05AM +, Tvrtko Ursulin wrote:
No, think you misunderstood me. I said slightly more defensive
just in the sense that in case of weird hardware failures you have a
potentially infinite loop now, where you don't really
From: Akash Goel akash.g...@intel.com
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2: Modified the WA comment (Ville)
v3: Added the vlv identifier with WA name (Damien)
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits the invalidation
of the TLB only to batch buffer boundaries, to pipe_control
commands which have the TLB invalidation bit set and sync
From: Akash Goel akash.g...@intel.com
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
VLV platform as it is not required.
Signed-off-by: Akash Goel akash.g...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
debug registers to track the current HEAD of the individual rings, which
may be anywhere within the per-process address spaces. In order to find
the full
intel_sdvo_get_trained_inputs() returns a bool, check the status
accordingly.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Spotted while reading code, compile tested only.
---
drivers/gpu/drm/i915/intel_sdvo.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Akash Goel akash.g...@intel.com
In Valleyview, Operational flush cannot be enabled on
BWG A0 [Errata BWT006]
Signed-off-by: Akash Goel akash.g...@intel.com
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6
From: Akash Goel akash.g...@intel.com
For VLV, disabling L3 clock gating- MMIO 940c[25] = 1
Signed-off-by: Akash Goel akash.g...@intel.com
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits the invalidation
of the TLB only to batch buffer boundaries,
On Fri, 2014-03-21 at 12:58 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits
It is important that the user is fully aware that the seemingly atomic
read/write of a 64-bit value from MMIO space, may in fact be 2 separate
reads of 32-bits. This can lead to hilarity, such as
commit d18b9619034230b6f945e215276425636ca401fe
Author: Chris Wilson ch...@chris-wilson.co.uk
Date:
On Fri, Mar 21, 2014 at 01:09:12PM +, Gupta, Sourab wrote:
On Fri, 2014-03-21 at 12:58 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode
From: Akash Goel akash.g...@intel.com
This workaround is needed on VLV for the HW context feature.
It is used after adding the mi_set_context command in ring buffer
for Hw context switch. As per the spec
The software must send a pipe_control with a CS stall and a post sync
operation and then a
On Fri, 2014-03-21 at 13:17 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 01:09:12PM +, Gupta, Sourab wrote:
On Fri, 2014-03-21 at 12:58 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Hi Damien,
On Thu, 2014-03-20 at 14:45 +, Damien Lespiau wrote:
On Thu, Mar 20, 2014 at 02:11:40PM +, Damien Lespiau wrote:
(source is premultiplied)
RGBA = ADD(SRC_COLOR*SRC_ALPHA, DST_COLOR*ONE_MINUS_SRC_ALPHA)
Grr, copy/paste error. If the source is already premultiplied:
On Mon, 2014-03-17 at 15:15 +0530, sourab gupta wrote:
On Mon, 2014-03-10 at 22:07 +, 'Chris Wilson' wrote:
On Mon, Mar 10, 2014 at 04:12:23PM +, Gupta, Sourab wrote:
Hi Chris,
For the issue mentioned by you ( regarding botching up ioctls), we
understand that this is
On Fri, Mar 21, 2014 at 01:31:56PM +, Gupta, Sourab wrote:
On Fri, 2014-03-21 at 13:17 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 01:09:12PM +, Gupta, Sourab wrote:
On Fri, 2014-03-21 at 12:58 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 06:05:04PM +0530,
On Fri, Mar 21, 2014 at 02:56:32PM +0200, Jani Nikula wrote:
intel_sdvo_get_trained_inputs() returns a bool, check the status
accordingly.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Will be interesting to see whether this catches anything ... Queued for
-next, thanks for the
On Fri, Mar 21, 2014 at 01:16:43PM +, Chris Wilson wrote:
It is important that the user is fully aware that the seemingly atomic
read/write of a 64-bit value from MMIO space, may in fact be 2 separate
reads of 32-bits. This can lead to hilarity, such as
s/reads/operations/
commit
For setups where we don't have gtk-doc installed, ie when the
GTK_DOC_CHECK macro doesn't expand, we still need to populate the
enable_gtk_doc variable to provide a value to the configure summary.
Cc: Thomas Wood thomas.w...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
On Fri, Mar 21, 2014 at 10:55:44AM +0100, Daniel Vetter wrote:
tests/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.am b/tests/Makefile.am
index aadcbc8..ddb0fd7 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -24,7 +24,7
On Fri, Mar 21, 2014 at 12:26:51PM +0100, Peter Senna Tschudin wrote:
On Thu, Mar 20, 2014 at 10:17 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Mar 20, 2014 at 05:56:20PM +0100, Peter Senna Tschudin wrote:
When Fedora updated the Kernel package from 3.12 to 3.13 my notebook
stopped
On Fri, Mar 21, 2014 at 01:09:48PM +0200, Jani Nikula wrote:
On Fri, 21 Mar 2014, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Mar 21, 2014 at 07:51:58AM +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 07:40:56AM +, Chris Wilson wrote:
On non-LLC platforms, when changing the cache
On Fri, Mar 21, 2014 at 06:02:36PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2:
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits the invalidation
of the TLB only to batch buffer boundaries, to pipe_control
commands which have the TLB invalidation bit set and sync
Hi all,
New -testing cycle with cool stuff:
- Inherit/reuse firmwar framebuffers (for real this time) from Jesse, less
flicker for fastbooting.
- More flexible cloning for hdmi (Ville).
- Some PPGTT fixes from Ben.
- Ring init fixes from Naresh Kumar.
- set_cache_level regression fixes for the
On Fri, 2014-03-21 at 15:15 +, Daniel Vetter wrote:
On Fri, Mar 21, 2014 at 06:02:36PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB
On Fri, Mar 21, 2014 at 4:23 PM, Jiri Kosina jkos...@suse.cz wrote:
So I am still seeing this with current Linus' tree rather regularly (but
it's not deterministic enough for a reliable bisect).
Unfortunately I haven't received any patches to test; what do you propose?
Would reporting this on
On Fri, Mar 21, 2014 at 02:40:00PM +, Damien Lespiau wrote:
For setups where we don't have gtk-doc installed, ie when the
GTK_DOC_CHECK macro doesn't expand, we still need to populate the
enable_gtk_doc variable to provide a value to the configure summary.
Signed-off-by: Damien Lespiau
On Fri, 2014-03-21 at 14:58 +, Daniel Vetter wrote:
On Fri, Mar 21, 2014 at 11:53:40AM +, Gupta, Sourab wrote:
On Wed, 2014-01-22 at 11:11 +, Chris Wilson wrote:
On Wed, Jan 22, 2014 at 12:54:51PM +0200, Ville Syrjälä wrote:
On Wed, Jan 22, 2014 at 09:15:06AM +0530,
On Fri, Mar 21, 2014 at 08:58:08PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits the invalidation
of the TLB only to batch buffer boundaries,
In commit a51435a3137ad8ae75c288c39bd2d8b2696bae8f
Author: Naresh Kumar Kachhi naresh.kumar.kac...@intel.com
Date: Wed Mar 12 16:39:40 2014 +0530
drm/i915: disable rings before HW status page setup
we reordered stopping the rings to do so before we set the HWS register.
However, there is
On Thu, Mar 20, 2014 at 02:26:34PM +0100, Daniel Vetter wrote:
[...]
The right fix therefore is to split this helper into an internal and
external version and add the required locking to the function exported
to drivers.
This remedies locking inconsistencies exposed by me adding locking
On Thu, Mar 20, 2014 at 02:26:35PM +0100, Daniel Vetter wrote:
[...]
Hence the right fix is to grab the mode_config mutex, but only that
and only right around the probe calls.
It seems to be sufficient to shut up all the locking WARNINGs I see on
i915 and nouveau in
Hi Ville,
Can you provide your feedback on this patch.
Waiting for your response.
Regards,
Sourab
-Original Message-
From: Gupta, Sourab
Sent: Monday, March 17, 2014 10:04 AM
To: Syrjala, Ville
Cc: Daniel Vetter; Chris Wilson; Goel, Akash; intel-gfx@lists.freedesktop.org
Subject: RE:
The documentation calls this GFX_MODE bit Flush TLB invalidate Mode.
However, that is not a good name for an enable bit as it doesn't make it
clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS
as enabling that bit actually prevents the TLB from being invalidated at
every flush.
Please check the DRAM configuration for the systems that fail. The higher
latency is more likely with higher tRFC which is mainly found with 8 Gbit
components.
-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Friday,
Hi,
Daniel Vetter daniel.vet...@ffwll.ch writes:
There's an entire pile of issues in here:
- Use the main RING_HEAD register, not ACTHD. ACTHD points at the gtt
offset of the batch buffer when a batch is executed. Semaphores are
always emitted to the main ring, so we always want to look
Hello,
I am sorry for asking specific question about power consumption
on baytrail-M platform.
We found the power consumption of baytrail-M graphic is bigger
under Linux(kernel 3.13) than under windows for playing video 1080p.
My question: Is
On Thu, Mar 13, 2014 at 02:31:37PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
Using MMIO based flips on VLV for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D
On Tue, Feb 04, 2014 at 12:11:03PM +0100, Daniel Vetter wrote:
On Fri, Jan 31, 2014 at 05:14:02PM +0200, Mika Kuoppala wrote:
Found with smatch.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Both smatch patches merged to dinq, thanks.
-Daniel
CC stable?
--
Ben Widawsky,
From: Mika Kuoppala mika.kuopp...@linux.intel.com
Sometimes generic driver code gets forcewake explicitly by
gen6_gt_force_wake_get(), which check forcewake_count before accessing
hardware. However the register access with gen8_write function access
low level hw accessors directly, ignoring the
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
[BDW 3.14 backport]
Cc: sta...@vger.kernel.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
From: Ben Widawsky benjamin.widaw...@intel.com
I'm not clear if the hardware is still subject to the same prefetching
issues that made us use a scratch page in the first place. In either
case, we're using garbage with the current code (we will end up using
offset 0).
This may be the cause of our
From: Jani Nikula jani.nik...@intel.com
BDW is no longer flagged as preliminary hw, but without
i915.preliminary_hw_support module param set the logs are filled with
WARNs about it.
Just make semaphores off the BDW per-chip default for now.
CC: Ben Widawsky b...@bwidawsk.net
Reported-by:
From: Kenneth Graunke kenn...@whitecape.org
I believe this will be necessary on production hardware.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
[danvet: Fix whitespace fail spotted by
From: Mika Kuoppala mika.kuopp...@intel.com
When we get control from BIOS there might be mt forcewake
bits already set. This causes us to do double mt get
without proper clear/ack sequence.
Fix this by clearing mt forcewake register on init,
like we do with older gens.
Signed-off-by: Mika
From: Ben Widawsky benjamin.widaw...@intel.com
Apparently it is wiped out from under us, and we get some really fun
caching artifacts upon resume (it seems to be WB for all types by
default).
Reported-by: James Ausmus james.aus...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
[BDW 3.14 backport]
Cc: sta...@vger.kernel.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
From: Damien Lespiau damien.lesp...@intel.com
While wandering in the spec, I noticed that BDW removes those 2 bits
from INSTPM. I couldn't find any direct way to invalidate the TLB (ie
without the ring working already). Maybe someone will be more lucky.
At least, we now know we may be a problem.
On Wed, Mar 05, 2014 at 01:05:46PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
gen7_enable_fbc() may write to some registers which we've already
touched, so use RMW so that we don't undo any previous updates.
Also note that we implemnt
Hi Ville,
Please could you review this patch provide a feedback.
This is as per your suggestions our earlier discussions.
Regards,
Sourab
-Original Message-
From: Goel, Akash
Sent: Tuesday, March 11, 2014 6:24 PM
To: intel-gfx@lists.freedesktop.org
Cc: Purushothaman, Vijay A; G,
On Fri, Mar 21, 2014 at 07:06:46PM +0530, Sagar Arun Kamble wrote:
Hi Damien,
On Thu, 2014-03-20 at 14:45 +, Damien Lespiau wrote:
On Thu, Mar 20, 2014 at 02:11:40PM +, Damien Lespiau wrote:
(source is premultiplied)
RGBA = ADD(SRC_COLOR*SRC_ALPHA,
On Fri, Mar 21, 2014 at 11:39:55AM -0700, Ben Widawsky wrote:
On Tue, Feb 04, 2014 at 12:11:03PM +0100, Daniel Vetter wrote:
On Fri, Jan 31, 2014 at 05:14:02PM +0200, Mika Kuoppala wrote:
Found with smatch.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Both smatch patches
On Fri, Mar 21, 2014 at 7:48 PM, Ben Widawsky
benjamin.widaw...@linux.intel.com wrote:
The following patches are the backported simple fixes for 3.14. Some
of these already had Cc: stable on them, but required conflict
resolution which I've provided (presumably they canbe dropped if it's
On Mon, Mar 10, 2014 at 6:14 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 10, 2014 at 10:40:50AM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added 2 new drm crtc properties. One property
provides control to vary the PIPESRC value. With this the
size of
From: Jani Nikula jani.nik...@intel.com
BDW is no longer flagged as preliminary hw, but without
i915.preliminary_hw_support module param set the logs are filled with
WARNs about it.
Just make semaphores off the BDW per-chip default for now.
v2: Spurious merge hunk leftover in v1 removed
CC:
On Fri, Mar 21, 2014 at 08:49:35PM +0100, Daniel Vetter wrote:
On Fri, Mar 21, 2014 at 7:48 PM, Ben Widawsky
benjamin.widaw...@linux.intel.com wrote:
The following patches are the backported simple fixes for 3.14. Some
of these already had Cc: stable on them, but required conflict
With the recent addition of locking checks in
commit 62ff94a5492175759546f8bc61383189d6b49122
Author: Daniel Vetter daniel.vet...@ffwll.ch
AuthorDate: Thu Jan 23 22:18:47 2014 +0100
drm/crtc-helper: remove LOCKING from kerneldoc
drm_add_edid_modes started to WARN about the
With the recent addition of locking checks in
commit 62ff94a5492175759546f8bc61383189d6b49122
Author: Daniel Vetter daniel.vet...@ffwll.ch
AuthorDate: Thu Jan 23 22:18:47 2014 +0100
drm/crtc-helper: remove LOCKING from kerneldoc
drm_add_edid_modes started to WARN about the
On Thu, Mar 20, 2014 at 11:53:07AM -0700, Yu Dai wrote:
All,
Thanks for the review of z-order patch. Based on that, we had some
internal discussion within our Display driver team. Here is the
summary.
1. Re: define plane z-order combinations as an enum property
User mode needs extra
From: Yu(Alex) Dai yu@intel.com
Add zorder property to crtc to control Z-order of sprite and
primary planes. The plane tag is packed into the 64 bits value
in the order of from bottom (lower bits) to top (higher bits).
Four bits are used for each plane tag. It can support up to 16
planes.
On Fri, Mar 21, 2014 at 03:14:48PM -0700, Ben Widawsky wrote:
On Fri, Mar 21, 2014 at 08:49:35PM +0100, Daniel Vetter wrote:
On Fri, Mar 21, 2014 at 7:48 PM, Ben Widawsky
benjamin.widaw...@linux.intel.com wrote:
The following patches are the backported simple fixes for 3.14. Some
of
On 03/21/2014 04:03 PM, Matt Roper wrote:
On Thu, Mar 20, 2014 at 11:53:07AM -0700, Yu Dai wrote:
All,
Thanks for the review of z-order patch. Based on that, we had some
internal discussion within our Display driver team. Here is the
summary.
1. Re: define plane z-order combinations as an
On Fri, Mar 21, 2014 at 04:47:05PM -0700, Greg KH wrote:
On Fri, Mar 21, 2014 at 03:14:48PM -0700, Ben Widawsky wrote:
On Fri, Mar 21, 2014 at 08:49:35PM +0100, Daniel Vetter wrote:
On Fri, Mar 21, 2014 at 7:48 PM, Ben Widawsky
benjamin.widaw...@linux.intel.com wrote:
The following
On Fri, Mar 21, 2014 at 05:06:06PM -0700, Ben Widawsky wrote:
On Fri, Mar 21, 2014 at 04:47:05PM -0700, Greg KH wrote:
On Fri, Mar 21, 2014 at 03:14:48PM -0700, Ben Widawsky wrote:
On Fri, Mar 21, 2014 at 08:49:35PM +0100, Daniel Vetter wrote:
On Fri, Mar 21, 2014 at 7:48 PM, Ben
Let's try this again. I've pushed a branch here:
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=bdw-backports
I need to re-review some of the merge conflicts for 4g GGTT, which I
will try to do before Monday.
Daniel: please make sure this is what you had in mind. I don't know
where you
On Fri, 2014-03-21 at 17:18 +, Chris Wilson wrote:
The documentation calls this GFX_MODE bit Flush TLB invalidate Mode.
However, that is not a good name for an enable bit as it doesn't make it
clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS
as enabling that bit
On Fri, 2014-03-21 at 16:52 +, Chris Wilson wrote:
On Fri, Mar 21, 2014 at 08:58:08PM +0530, sourab.gu...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits
Actually since the Panel fitter is at the Pipe level and also the PIPESRC
register, this has been exposed through crtc property. But with crtc also, it
is kind of associated with primary planes only.
Best Regards
Akash
-Original Message-
From: daniel.vet...@ffwll.ch
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