On Tue, Apr 15, 2014 at 07:43:07PM -0700, Ben Widawsky wrote:
> On Mon, Apr 14, 2014 at 10:55:53PM +0300, Ville Syrjälä wrote:
> > On Mon, Apr 14, 2014 at 10:41:14PM +0530, deepa...@intel.com wrote:
> > > From: Ben Widawsky
> > >
> > > Almost all of it is reusable from the existing code. The prim
On Wed, Apr 16, 2014 at 07:58:48AM +0200, Egbert Eich wrote:
> Daniel Vetter writes:
> > On Mon, Apr 14, 2014 at 07:26:09PM +0200, Egbert Eich wrote:
> > > Depending on the SDVO output_flags SDVO may have multiple connectors.
> > > These are all initialized in intel_sdvo_output_setup(). The conn
On Wed, Apr 16, 2014 at 7:47 AM, Yang, Guang A wrote:
> Ok there are a few cases where we can indeed make tests faster, but it will
> be work for us. And that won't really speed up much since we're adding piles
> more testcases at a pretty quick rate. And many of these new testcases are
> CRC base
On Tue, Apr 15, 2014 at 07:43:07PM -0700, Ben Widawsky wrote:
> On Mon, Apr 14, 2014 at 10:55:53PM +0300, Ville Syrjälä wrote:
> > On Mon, Apr 14, 2014 at 10:41:14PM +0530, deepa...@intel.com wrote:
> > > From: Ben Widawsky
> > >
> > > Almost all of it is reusable from the existing code. The prim
From: Mika Kuoppala
If hw_contexts are disabled, we always return the per file
descriptor default context stats. Make sure that the context
is correctly given and fail accordingly if not.
Testcase: igt/gem_reset_stats/params
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_contex
Depending on the SDVO output_flags SDVO may have multiple connectors
linking to the same encoder (in intel_connector->encoder->base).
Only one of those connectors should be active (ie link to the encoder
thru drm_connector->encoder).
If intel_connector_break_all_links() is called from intel_sanitiz
> I think stopping the tests after 10 minutes is ok, but in general the point of
> stress tests is to beat on the kernel for corner cases. E.g.
> even with todays extensive set of stress tests some spurious OOM bugs can
> only be reproduced in 1 out of 5 runs. Reducing the test time could severely
Bail out if crtc is NULL to keep the driver from crashing.
Signed-off-by: Egbert Eich
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c276733..dfebced 100644
--- a
On Wed, Apr 16, 2014 at 11:46 AM, Egbert Eich wrote:
> Bail out if crtc is NULL to keep the driver from crashing.
>
> Signed-off-by: Egbert Eich
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/dr
On Wed, Apr 16, 2014 at 11:16:45AM +0200, Egbert Eich wrote:
> Depending on the SDVO output_flags SDVO may have multiple connectors
> linking to the same encoder (in intel_connector->encoder->base).
> Only one of those connectors should be active (ie link to the encoder
> thru drm_connector->encode
On Mon, Apr 14, 2014 at 08:24:30PM +0300, Imre Deak wrote:
> Atm we can end up in the GPU reset deferred work in D3 state if the last
> runtime PM reference is dropped between detecting a hang/scheduling the
> work and executing the work. At least one such case I could trigger is
> the simulated re
On Mon, Apr 14, 2014 at 08:24:32PM +0300, Imre Deak wrote:
> While checking the error capture path I noticed that we lacked the
> power domain-on check for PIPESTAT so fix this by moving that to where
> the rest of pipe registers are captured.
>
> The move also revealed that we actually don't incl
On Mon, Apr 14, 2014 at 08:24:31PM +0300, Imre Deak wrote:
> While checking the error capture path I noticed that this register is
> read twice for GEN2, so fix this and also move the read where it's done
> for other platforms.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_gpu_e
On Mon, Apr 14, 2014 at 08:24:35PM +0300, Imre Deak wrote:
> Atm, an invalid enable_rc6 module option will be silently ignored, so
> emit an info message about it. Doing an early sanitization we can also
> reuse intel_enable_rc6() in a follow-up patch to see if RC6 is actually
> enabled. Currently
On Wed, 2014-04-16 at 15:28 +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 08:24:35PM +0300, Imre Deak wrote:
> > Atm, an invalid enable_rc6 module option will be silently ignored, so
> > emit an info message about it. Doing an early sanitization we can also
> > reuse intel_enable_rc6() in a
On Mon, Apr 14, 2014 at 08:24:46PM +0300, Imre Deak wrote:
> Add runtime PM support for VLV, but leave it disabled. The next patch
> enables it.
>
> The suspend/resume sequence used is based on [1] and [2]. In practice we
> depend on the GT RC6 mechanism to save the HW context depending on the
> r
On Wed, 2014-04-16 at 15:22 +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 08:24:31PM +0300, Imre Deak wrote:
> > While checking the error capture path I noticed that this register is
> > read twice for GEN2, so fix this and also move the read where it's done
> > for other platforms.
> >
>
On Wed, Mar 12, 2014 at 09:25:42AM +, Chris Wilson wrote:
> On Wed, Mar 12, 2014 at 11:16:59AM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 12, 2014 at 08:35:39AM +, Chris Wilson wrote:
> > > On Tue, Mar 11, 2014 at 07:37:35PM +0200, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From:
On Mon, Apr 14, 2014 at 10:36:55PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 10:41:15PM +0530, deepa...@intel.com wrote:
> > From: Deepak S
> >
> > In BDW, Apart from unmasking up/down threshold interrupts. we need
> > to umask bit 32 of PM_INTRMASK to route interrupts to target via D
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> Based on the hardware spec, the BDW GT3 has the different configuration
> with the BDW GT1/GT2. So split the BDW device info definition.
> This is to do the preparation for adding the Dual BSD rings on BDW GT3
> machine.
>
> V1->V2: Follow Da
Some drivers need to be able to have a perfect race-free fbcon setup.
Current drivers only enable hotplug processing after the call to
drm_fb_helper_initial_config which leaves a tiny but important race.
This race is especially noticable on embedded platforms where the
driver itself enables the vo
On Mon, Apr 14, 2014 at 08:24:46PM +0300, Imre Deak wrote:
> Add runtime PM support for VLV, but leave it disabled. The next patch
> enables it.
>
> The suspend/resume sequence used is based on [1] and [2]. In practice we
> depend on the GT RC6 mechanism to save the HW context depending on the
> r
The pipe is off at that point in time, so a vblank wait is simply a
50ms wait. Caught by Jesse's verbose "make vblank wait timeouts WARN"
patch. We've probably had a few versions of this float around already.
To document assumptions put a pipe assert into the same place. And
also add a posting rea
On Tue, 15 Apr 2014 19:17:59 +0200
Daniel Vetter wrote:
> Ok there are a few cases where we can indeed make tests faster, but it
> will be work for us. And that won't really speed up much since we're
> adding piles more testcases at a pretty quick rate. And many of these
> new testcases are CRC ba
On Sun, Apr 13, 2014 at 4:39 PM, Daniel Vetter wrote:
> I've forgotten to clean this all up correctly in
>
> commit e3d6ddb35f6221859b6054879d186e13a3af351e
> Author: Daniel Vetter
> Date: Tue Apr 1 22:15:00 2014 +0200
>
> drm/crtc-helper: don't disable disconnected outputs
>
> Reported-by:
On 16/04/2014 17:42, Jesse Barnes wrote:
On Tue, 15 Apr 2014 19:17:59 +0200
Daniel Vetter wrote:
Ok there are a few cases where we can indeed make tests faster, but it
will be work for us. And that won't really speed up much since we're
adding piles more testcases at a pretty quick rate. And ma
On Wed, Apr 16, 2014 at 04:56:09PM +0200, Daniel Vetter wrote:
> The pipe is off at that point in time, so a vblank wait is simply a
> 50ms wait. Caught by Jesse's verbose "make vblank wait timeouts WARN"
> patch. We've probably had a few versions of this float around already.
>
> To document assu
On Wed, Apr 16, 2014 at 08:42:27AM -0700, Jesse Barnes wrote:
> And can you elaborate on the CRC tests? It doesn't seem like those
> should take more than a few frames to verify we're getting what we
> expect...
Indeed, if the CRC tests take a long time, that's a bug (for instance we
may never re
On Wed, 2014-04-16 at 16:53 +0200, Daniel Vetter wrote:
> On Mon, Apr 14, 2014 at 08:24:46PM +0300, Imre Deak wrote:
> > Add runtime PM support for VLV, but leave it disabled. The next patch
> > enables it.
> >
> > The suspend/resume sequence used is based on [1] and [2]. In practice we
> > depend
On Wed, Apr 16, 2014 at 05:50:20PM +0200, Daniel Vetter wrote:
> On 16/04/2014 17:42, Jesse Barnes wrote:
> > On Tue, 15 Apr 2014 19:17:59 +0200
> > Daniel Vetter wrote:
> >> Ok there are a few cases where we can indeed make tests faster, but it
> >> will be work for us. And that won't really spee
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> Based on the hardware spec, the BDW GT3 machine has two independent
> BSD ring that can be used to dispatch the video commands.
> So just initialize it.
>
> Signed-off-by: Zhao Yakui
A couple of nitpicks below, with or without those:
Reviewe
On Tue, Apr 15, 2014 at 09:25:44PM +0200, Daniel Vetter wrote:
> On Fri, Apr 11, 2014 at 10:21:59AM +0300, Jani Nikula wrote:
> > On Fri, 11 Apr 2014, Ben Widawsky wrote:
> > > On Wed, Apr 09, 2014 at 06:44:29PM -0300, Paulo Zanoni wrote:
> > >> From: Paulo Zanoni
> > >>
> > >> Hi
> > >>
> > >>
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> Signed-off-by: Zhao Yakui
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_irq.c |5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> i
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> The Gen7 doesn't have the second BSD ring. But it will complain the switch
> check
> warning message during compilation. So just add it to remove the
> switch check warning.
>
> V1->V2: Follow Daniel's comment to update the comment
>
> Signe
On Wed, Apr 16, 2014 at 07:37:16PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 15, 2014 at 09:25:44PM +0200, Daniel Vetter wrote:
> > On Fri, Apr 11, 2014 at 10:21:59AM +0300, Jani Nikula wrote:
> > > On Fri, 11 Apr 2014, Ben Widawsky wrote:
> > > > On Wed, Apr 09, 2014 at 06:44:29PM -0300, Paulo Za
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> One extra ring is added in the kernel driver but it is transparent to the
> user-space application/middleware. In such case the number of the rings
> in kernel driver is bigger than that exported to the user-space. So
> it needs to filter out t
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> The BDW GT3 has two independent BSD rings, which can be used to process the
> video commands. To be simpler, it is transparent to user-space driver/middle.
> Instead the kernel driver will decide which ring is to dispatch the BSD video
> comman
On Mon, Apr 14, 2014 at 08:24:38PM +0300, Imre Deak wrote:
> This is needed by the next patch moving the call out from platform
> specific RPM callbacks to platform independent code.
>
> No functional change.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 --
> d
On 25/03/2014 13:23, Chris Wilson wrote:
Try to flush out dirty pages into the swapcache (and from there into the
swapfile) when under memory pressure and forced to drop GEM objects from
memory. In effect, this should just allow us to discard unused pages for
memory reclaim and to start writeback
On Mon, Apr 14, 2014 at 08:24:40PM +0300, Imre Deak wrote:
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b87109c..1f88917 100644
> --- a/drive
On Mon, Apr 14, 2014 at 08:24:42PM +0300, Imre Deak wrote:
> This will be needed by the VLV runtime PM helpers too, so factor it out.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.c | 37 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drive
Hi all,
New -testing cycle with cool stuff:
- vlv infoframe fixes from Jesse
- dsi/mipi fixes from Shobhit
- gen8 pageflip fixes for LRI/SRM from Damien
- cmd parser fixes from Brad Volkin
- some prep patches for CHV, DRRS, ...
- and tons of little things all over
A bit earlier than usual since I
Well, first of all I couldn't find the regs definitions. I decided to
do this review during fly but I didn't had this regs definitions on
VLV docs I have here with me. Could you please point me to the correct
docs?
Anyway this patch isn't really modifying any behaviour. So I would
tend to let my R
On Wed, 2014-04-16 at 18:08 -0300, Rodrigo Vivi wrote:
> Well, first of all I couldn't find the regs definitions. I decided to
> do this review during fly but I didn't had this regs definitions on
> VLV docs I have here with me. Could you please point me to the correct
> docs?
These regs are defin
On Tue, 15 Apr 2014, Imre Deak wrote:
> On Tue, 2014-04-15 at 21:43 +0200, Daniel Vetter wrote:
>> On Mon, Apr 14, 2014 at 11:56:03AM -0700, Steven Noonan wrote:
>> > On Mon, Apr 14, 2014 at 11:35:05AM -0700, Keith Packard wrote:
>> > > Steven Noonan writes:
>> > >
>> > > > Was using my machine
On Wed, Apr 16, 2014 at 2:46 PM, Jani Nikula
wrote:
> On Tue, 15 Apr 2014, Imre Deak wrote:
>> On Tue, 2014-04-15 at 21:43 +0200, Daniel Vetter wrote:
>>> On Mon, Apr 14, 2014 at 11:56:03AM -0700, Steven Noonan wrote:
>>> > On Mon, Apr 14, 2014 at 11:35:05AM -0700, Keith Packard wrote:
>>> > > St
On Wed, 2014-04-16 at 10:23 -0600, Deak, Imre wrote:
> On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote:
> > Based on the hardware spec, the BDW GT3 machine has two independent
> > BSD ring that can be used to dispatch the video commands.
> > So just initialize it.
> >
> > Signed-off-by: Zhao Y
Signed-off-by: Zhao Yakui
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h|1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_ge
This is the patch set that tries to add the support of dual BSD rings on BDW
GT3. Based on hardware spec, the BDW GT3 has two independent BSD rings, which
can be used to process the video commands. To be simpler, it is transparent
to user-space driver/middleware. In such case the kernel driver wil
Reviewed-by: Imre Deak
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i915/i915_irq.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7a4d3ae..63bd5de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
++
The BDW GT3 has two independent BSD rings, which can be used to process the
video commands. To be simpler, it is transparent to user-space driver/middle.
Instead the kernel driver will decide which ring is to dispatch the BSD video
command.
As every BSD ring is powerful, it is enough to dispatch t
The Gen7 doesn't have the second BSD ring. But it will complain the switch check
warning message during compilation. So just add it to remove the
switch check warning.
V1->V2: Follow Daniel's comment to update the comment
Reviewed-by: Imre Deak
Signed-off-by: Zhao Yakui
---
drivers/gpu/drm/i91
Based on the hardware spec, the BDW GT3 has the different configuration
with the BDW GT1/GT2. So split the BDW device info definition.
This is to do the preparation for adding the Dual BSD rings on BDW GT3 machine.
V1->V2: Follow Daniel's comment to pay attention to the stolen check for BDW
in ker
Based on the hardware spec, the BDW GT3 machine has two independent
BSD ring that can be used to dispatch the video commands.
So just initialize it.
V3->V4: Follow Imre's comment to do some minor updates. For example:
more comments are added to describe the semaphore between ring.
Reviewed-by: Im
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