From: Sourab Gupta
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to us
Re-define MIPI register definitions in such a way that most of
the existing DSI code can be re-used for future platforms. Register
definitions are re-written using MMIO offset variable, so that without
changing the existing sequence, same code can be generically applied.
V4: Addressing review comm
Conceptually, the MIPI registers are addressed by the MIPI transcoder
index, not the pipe. It doesn't matter right now, because there's a
1:1 relationship between pipes and MIPI transcoders, but that change
allows us to break that link in the future
V1: Created new patch to address Damien's review
Hi Dave,
drm-intel-next-2014-05-23:
- prep refactoring for execlists (Oscar Mateo)
- corner-case fixes for runtime pm (Imre)
- tons of vblank improvements from Ville
- prep work for atomic plane/sprite updates (Ville)
- more chv code, now almost complete (tons of different people)
- refactoring an
On Sun, Jun 01, 2014 at 04:43:13PM +0530, sourab.gu...@intel.com wrote:
> From: Sourab Gupta
>
> This patch enables the framework for using MMIO based flip calls,
> in contrast with the CS based flip calls which are being used currently.
>
> MMIO based flip calls can be enabled on architectures
