On Thu, Jun 12, 2014 at 02:18:37PM -0700, armin.c.re...@intel.com wrote:
> From: Armin Reese
>
> This subtest forces the driver down the code path in
> i915_gem_object_set_cache_level()
> which unbinds VMAs and triggers the kernel panic described in VIZ-3721. This
> test will pass if the bug fi
On Fri, Jun 13, 2014 at 02:52:04PM +0800, Quanxian Wang wrote:
> DP connector will be disconnected after chvt to another console
> for 10 minutes or more on valleyview platform VTC1010.
This needs _much_ more detail, really.
Also it smells like we work around a sink issue, which means the correct
Hi,
On 06/13/2014 03:28 AM, Aaron Lu wrote:
> On 06/12/2014 08:42 PM, Kalle Valo wrote:
>> Hi Aaron,
>>
>> after your commit 0e9f81d3b7c ("ACPI / video: Add systems that should
>> favour native backlight interface") I have had an regression that every
>> time after resume the display brightness ha
On Thu, Jun 12, 2014 at 10:16:46AM -0700, Rodrigo Vivi wrote:
> On the current structure HSW doesn't support PSR with sprites enabled
> but sprites can be enabled after PSR was enabled what would cause
> user to miss screen updates.
>
> v2: move it to update_plane.
>
> Cc: Ville Syrjälä
> Review
From: Ville Syrjälä
obj->framebuffer_references isn't an atomic_t so the decrement needs to
be protected by some lock. struct_mutex seems like the appropriate lock
here, and we may already take it for the obj unref anyway.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c |
On Thu, Jun 12, 2014 at 10:16:43AM -0700, Rodrigo Vivi wrote:
> Reviewed-by: Vijay Purushothaman
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
On Fri, Jun 13, 2014 at 11:10:53AM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> obj->framebuffer_references isn't an atomic_t so the decrement needs to
> be protected by some lock. struct_mutex seems like the appropriate lock
> here, and we may already take it for the obj
Aside: The test has way too many bool return values that are then
always checked with igt_assert. Imo cleaner to switch to a more
declarative approach and shovel the igt_assert/require into those
functions instead.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79962
Signed-off-by: Daniel
From: Tom O'Rourke
Correct a merge mishap in
commit e4443e459ccf43f2c139358400365fd6a839d40d
Author: Ville Syrjälä
Date: Wed Apr 9 13:28:41 2014 +0300
drm/i915/chv: Add a bunch of pre production workarounds
Remove the the chv specific workarounds from bdw code, specifically
gen8_enable_
Signed-off-by: Daniel Vetter
---
tests/prime_self_import.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 67fd5217479c..defe97ef421f 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -302,
Hi,
On 06/07/2014 01:12 PM, Chris Wilson wrote:
> On Sat, Jun 07, 2014 at 12:18:35PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 06/06/2014 04:51 PM, Chris Wilson wrote:
>>> commit c6cd10f536e099277cdc46643725a5a50ea8b525
>>> Author: Chris Wilson
>>> Date: Thu Jun 5 22:43:37 2014 +0100
>>
>> Th
On Fri, 13 Jun 2014, Jani Nikula wrote:
> From: Tom O'Rourke
>
> Correct a merge mishap in
>
> commit e4443e459ccf43f2c139358400365fd6a839d40d
> Author: Ville Syrjälä
> Date: Wed Apr 9 13:28:41 2014 +0300
>
> drm/i915/chv: Add a bunch of pre production workarounds
>
> Remove the the chv sp
On Fri, Jun 13, 2014 at 10:49:12AM +0200, Hans de Goede wrote:
> Hi,
>
> On 06/07/2014 01:12 PM, Chris Wilson wrote:
> > On Sat, Jun 07, 2014 at 12:18:35PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 06/06/2014 04:51 PM, Chris Wilson wrote:
> >>> commit c6cd10f536e099277cdc46643725a5a50ea8b5
On Fri, 13 Jun 2014, Daniel Vetter wrote:
> On Fri, Jun 13, 2014 at 02:52:04PM +0800, Quanxian Wang wrote:
>> DP connector will be disconnected after chvt to another console
>> for 10 minutes or more on valleyview platform VTC1010.
>
> This needs _much_ more detail, really.
>
> Also it smells like
Suggested by Chris Wilson. Not yet rolled out since I'm trying to use
cocci for this.
Signed-off-by: Daniel Vetter
---
lib/igt_core.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index f7f7015a32f5..b54ef61565d0 100644
--- a/lib/igt_core.h
++
Cocci is awesome
Signed-off-by: Daniel Vetter
---
tests/drv_hangman.c | 14 --
tests/kms_psr_sink_crc.c | 4 ++--
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
index d74ed483407c..667491baf7f1 100644
--- a/tests/drv_ha
Small start but useful to collect refactorings/simplifications for
common igt patterns. Please add more if you stumble over some so that
we can occasionally run this to clean up the tests.
I haven't figured out yet how to do the assert_cmpint->assert_eq
transformation.
Run this with
spatch --sp-
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Friday, June 13, 2014 3:16 PM
> To: Wang, Quanxian
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv: DP_SINK_COUNT is not
> reliable for val
On Tue, 10 Jun 2014, Damien Lespiau wrote:
> The "usage" text should explain it all. I found, in my quilt series
> handling endeavours, that I wanted to be able to shift the prefix
> numbers of a patch series.
>
> v2: Use heredoc for usage string, fix second example, use mv -i (Jani)
>
> Signed-of
On Thu, Jun 12, 2014 at 11:16:55PM +0200, Hans de Goede wrote:
> Hi All,
>
> While preparing 1.15.99.903 server + 2.99.912 intel drv packages
> for Fedora 21, I noticed that both gdm and gnome-shell (tested
> with startx) hang, they show the initial background screen and
> then just sit there.
Ca
From: Deepak S
Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
min freq should bring bring the voltage Vnn.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 40 +---
1 file changed, 1 insertion(+), 39 deletions(-)
dif
On Fri, 13 Jun 2014, "Wang, Quanxian" wrote:
>> -Original Message-
>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>> Vetter
>> Sent: Friday, June 13, 2014 3:16 PM
>> To: Wang, Quanxian
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH] dr
From: Ville Syrjälä
I was tring to see if the 200 MHz cdclk option would work on VLV, and also
whether the Vnn voltage drops in response to cdclk. Sadly neither seems be to
true on my VLV. Might be some other unit is keeping Vnn elevated. I need to
trawl the docs more to see if I can find some fu
From: Ville Syrjälä
Avoid using magic values for CCK frequency bits. Also the mask we were
using for the requested frequency was one bit too short. Fix it up.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_display.c | 4 ++--
2 files
From: Ville Syrjälä
Depending on the HPLL frequency one of the supported cdclk frquencies is
either 320MHz or 333MHz. Figure out which one it is to accurately pick
the minimal required cdclk. This would also avoid a warning from the
cdclk code where it compares the actual cdclk read out from the
From: Ville Syrjälä
We have a standard hook for reading out the current cdclk. Move the VLV
code from valleyview_cur_cdclk() to .get_display_clock_speed().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 33 +
drivers/gpu/drm/i915/intel_d
From: Ville Syrjälä
Now that the CMNRESET deassert is part of the cmnlane power well,
intel_reset_dpio() is called too late to make any difference. We've
deasserted CMNRESET by that time, and so the off+on toggle w/a will
never kick in.
Move the workaround to intel_power_domains_init_hw() where
From: Ville Syrjälä
If someone is interested in the current cdclk frquency it should
be stable and not in process of changing frquency. Warn if the current
and requested cdclk don't match in .get_display_clock_spee() on vlv.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c
From: Ville Syrjälä
Drop the cdclk frequency to 200MHz on vlv when all pipes are off. In
theory we should be able to use 200MHz also when the pixel clock is at
most 90% of 200MHz. However in practice all we seem to get is a solid
color picture or an otherwise corrupted display.
Signed-off-by: Vi
From: Ville Syrjälä
Remove the clutter in __vlv_set_power_well() by moving the cmnlane
handling into custom enable/disable hooks for the cmnlane.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 92 -
1 file changed, 55 insertions(+), 3
From: Ville Syrjälä
We have a slightly different way of readoing out the cdclk in
gmbus_set_freq(). Kill that and just call .get_display_clock_speed().
Also need to remove the GMBUSFREQ update from intel_i2c_reset() since
that gets called way too early. Let's do it in intel_modeset_init_hw()
ins
From: Ville Syrjälä
Use kHz units in vlv cdclk code since that's more customary.
Also replace the precomputed 90% values with *9/10 computation
for extra clarity.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 27 ++-
drivers/gpu/drm/i915/intel
From: Ville Syrjälä
Set some bits in CCK/CCU to turn off display clocks when disp2d is power
gated. Not sure this really helps with anything. Docs aren't all that clear.
XXX: Doesn't actually work. CCK_DISPLAY_REF_CLOCK_CONTROL and CCU_ICLK_5
writes don't have any effect on the registers for som
From: Ville Syrjälä
VLV Punit doesn't support the 400MHz cdclk option, so we bypass the
Punit and poke at CCK directly. However we forgot to wait for the
frequeency change to complete. Poll the CCK clock status to make sure
the clock has changed before we fire up any pipes.
Signed-off-by: Ville
On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
> min freq should bring bring the voltage Vnn.
>
> Signed-off-by: Deepak S
> ---
> drivers/gpu/drm/i915/intel_pm.c | 40 +---
Atm it's possible that we enable the memory self-refresh mode before the
watermark levels used by this mode are programmed with valid values. So
move the enabling after we programmed the WM levels.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 21 ++---
1 file ch
This functionality will be also needed by an upcoming patch, so factor
it out. As a bonus this also makes things a bit more uniform across
platforms. Note that this also changes the register read-modify-write
to a simple write during disabling. This is what we do during enabling
anyway and accordin
Blanking/unblanking the console in a loop on an Asus T100 sometimes
leaves the console blank. After some digging I found that applying
commit 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595
Author: Egbert Eich
Date: Mon Mar 4 09:24:38 2013 -0500
DRM/i915: On G45 enable cursor plane briefly after
On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
> > min freq should bring bring the voltage Vnn.
> >
>
On Fri, 13 Jun 2014, Daniel Vetter wrote:
> On Thu, Jun 12, 2014 at 10:16:46AM -0700, Rodrigo Vivi wrote:
>> On the current structure HSW doesn't support PSR with sprites enabled
>> but sprites can be enabled after PSR was enabled what would cause
>> user to miss screen updates.
>>
>> v2: move it
Hi,
When trying to run the latest xorg + intel drv, with dri3, with Xorg not
running as root, the followin assert in src/intel_device.c: authorise() :
assert(is_i915_gem(fd));
Triggers, this is caused by the DRM_IOCTL_I915_GETPARAM ioctl in
is_i915_gem() failing with -EACCESS in this case.
I th
On Fri, 06 Jun 2014, Daniel Vetter wrote:
> On Fri, Jun 06, 2014 at 06:18:01PM +0100, Damien Lespiau wrote:
>> On Fri, Jun 06, 2014 at 08:22:08AM +0200, Daniel Vetter wrote:
>> > + mutex_lock(&crtc->base.mutex);
>> > + if (crtc->active)
>> > + intel_wait_for_vbla
On Friday 13 June 2014 05:27 PM, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
min freq sh
On Fri, Jun 13, 2014 at 02:08:06PM +0200, Hans de Goede wrote:
> Hi,
>
> When trying to run the latest xorg + intel drv, with dri3, with Xorg not
> running as root, the followin assert in src/intel_device.c: authorise() :
>
> assert(is_i915_gem(fd));
>
> Triggers, this is caused by the DRM_IOCTL
From: Ville Syrjälä
Knowing the device stepping may be crucial in analyzing problems. Since
we always ask bug reporters for dmegs with drm.debug=0xe (or something)
it would be nice if the PCI revision is already included in the dump.
Avoids having to ask for lspci output as well.
Signed-off-by:
Hi,
On 06/13/2014 02:36 PM, Chris Wilson wrote:
> On Fri, Jun 13, 2014 at 02:08:06PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> When trying to run the latest xorg + intel drv, with dri3, with Xorg not
>> running as root, the followin assert in src/intel_device.c: authorise() :
>>
>> assert(is_i915_g
On Fri, Jun 13, 2014 at 02:44:44PM +0200, Hans de Goede wrote:
> Hi,
>
> On 06/13/2014 02:36 PM, Chris Wilson wrote:
> > On Fri, Jun 13, 2014 at 02:08:06PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> When trying to run the latest xorg + intel drv, with dri3, with Xorg not
> >> running as root,
Hi, currently the gem_seqno_wrap test in igt is not built for android due to it
Using the wordexp function which is missing from bionic.
The test author (Mika Kuoppala) is of the opinion that this option is redundant
And can be removed. Does anyone use this option? Otherwise I'll remove it.
Tim
igt_fixture and igt_subtests use longjmp/setjmp internally, which
means local variables at the same stack frame are at risk. Best
practice is to move them out right in front of the igt_main block.
It would be awesome if someone could come up with a cocci patch to
auto-fix this, but unfortunately m
Hi,
On 06/13/2014 02:53 PM, Chris Wilson wrote:
> On Fri, Jun 13, 2014 at 02:44:44PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 06/13/2014 02:36 PM, Chris Wilson wrote:
>>> On Fri, Jun 13, 2014 at 02:08:06PM +0200, Hans de Goede wrote:
Hi,
When trying to run the latest xorg + intel
From: Ville Syrjälä
CHECK linux/drivers/gpu/drm/i915/i915_gem_execbuffer.c
linux/drivers/gpu/drm/i915/i915_gem_execbuffer.c:1529:47: warning: incorrect
type in initializer (different address spaces)
linux/drivers/gpu/drm/i915/i915_gem_execbuffer.c:1529:47:expected struct
drm_i915_gem_exec
Also update old hunks to match on igt logging instead of fprintf.
Signed-off-by: Daniel Vetter
---
lib/igt.cocci | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/lib/igt.cocci b/lib/igt.cocci
index a5f7c2dbfbce..9c6d0d045fac 100644
--- a/lib/igt.cocci
abort should only be used for internal library checks - using
abort() we get a "crash" result, using igt_fail we get "fail"
in piglit.
Signed-off-by: Daniel Vetter
---
lib/igt.cocci | 7 +++
1 file changed, 7 insertions(+)
diff --git a/lib/igt.cocci b/lib/igt.cocci
index 9c6d0d045fac..a0573
Signed-off-by: Daniel Vetter
---
lib/igt.cocci | 8
1 file changed, 8 insertions(+)
diff --git a/lib/igt.cocci b/lib/igt.cocci
index a0573f5d4e4f..ff0de31c9c48 100644
--- a/lib/igt.cocci
+++ b/lib/igt.cocci
@@ -22,6 +22,14 @@ expression list[n] Ep;
- igt_skip(Ep);
- }
+ igt_skip_on_f
Needs to be run a few times to reach a stable state ...
Signed-off-by: Daniel Vetter
---
tests/ddi_compute_wrpll.c | 12 +
tests/gem_bad_reloc.c | 4 +-
tests/gem_fence_upload.c| 12 ++---
tests/gem_render_linear_blits.c | 2 +-
tests/gem_render_tiled_blits.c |
These should go to stdout instead. The next patch will clean this up
with cocci, so no change from fprintf(stdout, to printf( here.
Signed-off-by: Daniel Vetter
---
lib/igt.cocci | 1 +
tests/gem_stress.c | 2 +-
tests/testdisplay.c | 34 +-
3 files chang
On Fri, Jun 13, 2014 at 03:02:21PM +0300, Jani Nikula wrote:
> On Fri, 13 Jun 2014, Daniel Vetter wrote:
> > On Thu, Jun 12, 2014 at 10:16:46AM -0700, Rodrigo Vivi wrote:
> >> On the current structure HSW doesn't support PSR with sprites enabled
> >> but sprites can be enabled after PSR was enable
On Fri, Jun 13, 2014 at 05:56:41PM +0530, Deepak S wrote:
>
> On Friday 13 June 2014 05:27 PM, Ville Syrjälä wrote:
> >On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
> >>On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
> >>>From: Deepak S
> >>>
> >>>Workar
On Fri, Jun 13, 2014 at 03:39:56PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Knowing the device stepping may be crucial in analyzing problems. Since
> we always ask bug reporters for dmegs with drm.debug=0xe (or something)
> it would be nice if the PCI revision is alre
On Fri, Jun 13, 2014 at 01:15:32PM +, Gore, Tim wrote:
> Hi, currently the gem_seqno_wrap test in igt is not built for android due to
> it
> Using the wordexp function which is missing from bionic.
> The test author (Mika Kuoppala) is of the opinion that this option is
> redundant
> And can
On Fri, Jun 13, 2014 at 04:42:51PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> CHECK linux/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> linux/drivers/gpu/drm/i915/i915_gem_execbuffer.c:1529:47: warning: incorrect
> type in initializer (different address spaces)
> linu
On Thu, 22 May 2014, Vandana Kannan wrote:
> Adding relevant read out comparison code, in check_crtc_state, for the new
> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
> values for a DP downclock mode (if available). Suggested by Daniel.
>
> v2: Changed patch title.
> Dan
On Thu, Jun 12, 2014 at 06:36:04PM +0100, Chris Wilson wrote:
> On Thu, Jun 12, 2014 at 10:10:58AM -0700, Volkin, Bradley D wrote:
> > On Thu, Jun 12, 2014 at 03:13:14PM +0100, Chris Wilson wrote:
> > > + /* Check if a second thread completed the prefaulting for us */
> > > + if (obj->fault_mappabl
To disable a plane, userspace passes in an framebuffer id of 0. This
causes us to pass CRTC == NULL to setplane_internal, who promptly
deferences it to grab the struct drm_device. Oops.
[ 1296.467327] BUG: unable to handle kernel NULL pointer dereference at (null)
[ 1296.467332] IP: [] setplane_
And also pimp the spatch file itself with usage hints.
Signed-off-by: Daniel Vetter
---
NEWS | 3 +++
lib/igt.cocci | 8
2 files changed, 11 insertions(+)
diff --git a/NEWS b/NEWS
index ee920744f4c4..33354f9d5360 100644
--- a/NEWS
+++ b/NEWS
@@ -1,6 +1,9 @@
Release 1.8 (-
On Fri, Jun 13, 2014 at 03:47:31PM +0200, Daniel Vetter wrote:
> These should go to stdout instead. The next patch will clean this up
> with cocci, so no change from fprintf(stdout, to printf( here.
>
> Signed-off-by: Daniel Vetter
> ---
> lib/igt.cocci | 1 +
> tests/gem_stress.c | 2 +
On Fri, Jun 13, 2014 at 04:42:26PM +0200, Daniel Vetter wrote:
> On Fri, Jun 13, 2014 at 03:22:28PM +0100, Chris Wilson wrote:
> > To disable a plane, userspace passes in an framebuffer id of 0. This
> > causes us to pass CRTC == NULL to setplane_internal, who promptly
> > deferences it to grab the
On Fri, Jun 13, 2014 at 07:17:06AM -0700, Volkin, Bradley D wrote:
> On Thu, Jun 12, 2014 at 06:36:04PM +0100, Chris Wilson wrote:
> > On Thu, Jun 12, 2014 at 10:10:58AM -0700, Volkin, Bradley D wrote:
> > > On Thu, Jun 12, 2014 at 03:13:14PM +0100, Chris Wilson wrote:
> > > > + /* Check if a
On Fri, Jun 13, 2014 at 04:42:26PM +0200, Daniel Vetter wrote:
> On Fri, Jun 13, 2014 at 03:22:28PM +0100, Chris Wilson wrote:
> > Fixes regression from
> > commit b02fd7fd8a541c3d590bfdda23365a927b507ceb
> > Author: Matt Roper
> > Date: Tue Jun 10 08:28:10 2014 -0700
> >
> > drm: Support l
On Fri, Jun 13, 2014 at 03:22:28PM +0100, Chris Wilson wrote:
> To disable a plane, userspace passes in an framebuffer id of 0. This
> causes us to pass CRTC == NULL to setplane_internal, who promptly
> deferences it to grab the struct drm_device. Oops.
>
> [ 1296.467327] BUG: unable to handle ker
Adding Egbert since he's done the original hack here. Imre please keep
him on cc.
-Daniel
On Fri, Jun 13, 2014 at 1:54 PM, Imre Deak wrote:
> Blanking/unblanking the console in a loop on an Asus T100 sometimes
> leaves the console blank. After some digging I found that applying
>
> commit 61bc95c
On Fri, Jun 13, 2014 at 07:44:33AM -0700, Matt Roper wrote:
> On Fri, Jun 13, 2014 at 04:42:26PM +0200, Daniel Vetter wrote:
> > On Fri, Jun 13, 2014 at 03:22:28PM +0100, Chris Wilson wrote:
> > > To disable a plane, userspace passes in an framebuffer id of 0. This
> > > causes us to pass CRTC == N
Early revs didn't have PPGTT support, so disable there.
References: https://bugs.freedesktop.org/show_bug.cgi?id=79669
References: https://bugs.freedesktop.org/show_bug.cgi?id=79670
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_gem_gtt.c |4
1 file changed, 4 insertions(+)
From: Oscar Mateo
For the most part, logical ring context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to poke certain offsets of the object for
initialization, updating the tail pointer or updating the PDPs.
F
From: Oscar Mateo
These two functions make no sense in an Logical Ring Context & Execlists
world.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_gem_context.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/
From: Oscar Mateo
There are a few big differences between context init and fini with the
previous implementation of hardware contexts. One of them is
demonstrated in this patch: we must allocate a ctx backing object for
each engine.
Regarding the context size, reading the register to calculate t
From: Oscar Mateo
For a description of this patchset, please check the previous cover letters:
[1] and [2].
The main difference with v2 is in how we get to the point of context
submission: this time
around, instead of massaging the legacy ringbuffer submission functions (mostly
located in int
From: Oscar Mateo
We are going to use it later to allocate our own context objects.
No functional changes.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_context.c | 54 +
2 files changed, 37 insert
From: Oscar Mateo
This is mostly for correctness so that we know we are running the LR
context correctly (this is, the PDPs are contained inside the context
object).
v2: Move the check to inside the enable PPGTT function. The switch
happens in two places: the legacy context switch (that we won't
From: Oscar Mateo
... and namespace appropriately.
It looks to me like it belongs logically there.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_drv.h| 3 +++
drivers/gpu/drm/i915/i915_gem_context.c| 23 +++
drivers/gpu/drm/i915/i915_gem_execbuf
From: Oscar Mateo
We are going to start creating a lot of extra ringbuffers soon, so
these functions are handy.
No functional changes.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 26 --
drivers/gpu/drm/i915/intel_ringbuffer.h | 4
2 f
From: Oscar Mateo
GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
These expanded contexts enable a number of new abilities, especially
"Execlists".
The macro is defined to off until we have things in place to hope to
work. In dev_priv, lrc_enabled will reflect the state of
From: Oscar Mateo
Some legacy HW context code assumptions don't make sense for this new
submission method, so we will place this stuff in a separate file.
Note for reviewers: I've carefully considered the best name for this file
and this was my best option (other possibilities were intel_lr_cont
From: Oscar Mateo
Without this, i915_gem_context_free looks obfuscated. But, also, it
gives me the possibility to know which kind of context I am dealing
with at freeing time (at this point we only have fake and legacy hw
contexts, but soon we will have logical ring contexts as well).
Signed-off
From: Oscar Mateo
Early in the series we had our own gen8_gem_context_init/fini
functions, but the truth is they now look almost the same as the
legacy hw context init/fini functions. We can always split them
later if this ceases to be the case.
Also, we do not fall back to legacy ringbuffers wh
From: Oscar Mateo
The reason for doing this will be better explained in the following
patch. For now, suffice it to say that this backing object is only
used with the render ring, so we're making this fact more explicit.
Done with the following Coccinelle patch (plus manual renaming of the
struc
From: Oscar Mateo
The backing objects for contexts created via open fd are actually
empty until the user starts sending execbuffers to them. We do this
because, at create time, we really don't know which engine is going
to be used with the context later on.
v2: As context created via ioctl can o
From: Oscar Mateo
As we have said a couple of times by now, logical ring contexts have
their own ringbuffers: not only the backing pages, but the whole
management struct.
In a previous version of the series, this was achieved with two separate
patches:
drm/i915/bdw: Allocate ringbuffer backing o
From: Oscar Mateo
A context backing object only makes sense for a given engine (because
it holds state data specific to that engine).
In legacy ringbuffer sumission mode, the only MI_SET_CONTEXT we really
perform is for the render engine, so one backing object is all we needed.
With Execlists,
From: Oscar Mateo
The time has come, the Walrus said, to talk of many things.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89b6d5c..b62b
From: Oscar Mateo
This is a hard one, since there is no direct hardware ring to
control when in Execlists.
We reuse intel_ring_idle here, but it should be fine as long
as i915_add_request does the ring thing.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 27 +++
From: Oscar Mateo
The batchbuffer that sets the render context state is submitted
in a different way, and from different places.
We needed to make both the render state preparation and free functions
outside accesible, and namespace accordingly. This mess is so that all
LR, LRC and Execlists fun
From: Ben Widawsky
This has turned out to be really handy in debug so far.
Update:
Since writing this patch, I've gotten similar code upstream for error
state. I've used it quite a bit in debugfs however, and I'd like to keep
it here at least until preemption is working.
Signed-off-by: Ben Wida
From: Oscar Mateo
Allocate and populate the default LRC for every ring, call
gen-specific init/cleanup, init/fini the command parser and
set the status page (now inside the LRC object).
Stopping the ring before cleanup and initializing the seqnos
is left as a TODO task (we need more infrastructu
From: Oscar Mateo
We need to attend context switch interrupts from all rings. Also, fixed writing
IMR/IER and added HWSTAM at ring init time.
Notice that, if added to irq_enable_mask, the context switch interrupts would
be incorrectly masked out when the user interrupts are due to no users waiti
From: Oscar Mateo
If we reset a ring after a hang, we have to make sure that we clear
out all queued Execlists requests.
v2: The ring is, at this point, already being correctly re-programmed
for Execlists, and the hangcheck counters cleared.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915
From: Oscar Mateo
Execlists are indeed a brave new world with respect to workload
submission to the GPU.
In previous version of these series, I have tried to impact the
legacy ringbuffer submission path as little as possible (mostly,
passing the context around and using the correct ringbuffer wh
From: Sourab Gupta
If we want flips to work, either we create an Execlists-aware version
of intel_gen7_queue_flip, or we don't place commands directly in the
ringbuffer.
When upstreamed, this patch should implement the second option:
drm/i915: Replaced Blitter ring based flips with MMIO fli
From: Oscar Mateo
No mistery here: the seqno is still retrieved from the engine's
HW status page (the one in the default context. For the moment,
I see no reason to worry about other context's HWS page).
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 20
From: Oscar Mateo
I plan to reuse these for the new logical ring path.
No functional changes.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 31 ++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +++
2 files changed, 21 insertions(+), 13 de
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