On Wed, 20 Aug 2014, Larry Finger wrote:
> My Toshiba A50 with graphics adapter described by
>
> 00:02.0 VGA compatible controller [0300]: Intel Corporation 4th Gen Core
> Processor Integrated Graphics Controller [8086:0416] (rev 06) gets the
> following
> warning on 3.17-rc1:
https://bugs.freed
From: Deepak S
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
Author: Ben Widawsky
Date: Sat Nov 2 21:07:09 2013 -0700
drm/i915/bdw: Implement interrupt changes
Signed-
On Wed, 20 Aug 2014, "Wilde, Martin" wrote:
> Greetings - after reviewing Chris¹s feedback below and some thought, I
> most likely do not need to add another trace message and the existing
> ³i915_flip_complete² trace message can be used.
>
> Thus the only change requested is to have the T1_T3 val
kmstest_edid_add_3d adds an EDID extension block with 3D support to a
copy of the specified EDID.
Signed-off-by: Thomas Wood
---
lib/igt_kms.c | 80 +++
lib/igt_kms.h | 1 +
2 files changed, 81 insertions(+)
diff --git a/lib/igt_kms.c b/l
Move create_stereo_fb from testdisplay to igt_create_stereo_fb in igt_fb
so that it can be used in other tests.
Signed-off-by: Thomas Wood
---
lib/Makefile.am | 4 +-
lib/igt_fb.c| 131
lib/igt_fb.h| 2 +
lib/igt_kms.h
Add a test to verify creation and use of 3D stereo modes.
Signed-off-by: Thomas Wood
---
lib/igt_fb.c | 4 +-
tests/.gitignore | 1 +
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_3d.c | 118 +
On Thu, Aug 21, 2014 at 01:37:09PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Programing GT IER interrupts was fumbled while enabling Interrupts for
> gen8
True, but...
>
> This is a regression from
> commit abd58f0175915bed644aa67c8f69dc571b8280e0
> Author: Ben Widaws
On Mon, Aug 18, 2014 at 01:48:35PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Backlight on delay uses PWM enable time to seperate PWM to
> backlight enable assert. Previous time difference used timing
> from VDD enable which occur several seconds before resulting
> in PWM s
Be sure to always flush a stuck pageflip even if we couldn't possibly
expect one to be there.
References: https://bugs.freedesktop.org/show_bug.cgi?id=82612
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
di
On Wed, Aug 20, 2014 at 01:13:34PM +0100, Chris Wilson wrote:
> Be sure to always flush a stuck pageflip even if we couldn't possibly
> expect one to be there.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=82612
> Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
> ---
> d
Make sure plane rotation is reset correctly when restoring the fbdev
configuration by using drm_mode_plane_set_obj_prop which calls the
driver's set_property callback.
The rotation reset feature was introduced in commit 9783de2 (drm:
Resetting rotation property) and the callback issue was original
On 18 August 2014 13:51, Damien Lespiau wrote:
> Pimp up the debug message that tells us we've been waiting for a vblank
> that never arrived. Printing the pipe could lead a "doh!" moment where
> we've been waiting for a vblank on a pipe that was off for instance.
>
> Signed-off-by: Damien Lespiau
In this patch workarounds for BDW are applied using golden render state.
Only those registers that are part of register state are added to this batch.
Remaining workarounds are still in its current place init_clock_gating() which
are not affected by a gpu reset. I can send another patch where they
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the WA registers are part of register
state context and they are restored with every context switch so initializing
them in golden render state ensures that they are applied even when w
Workarounds are applied using golden render state and they are placed
at the beginning of this batch buffer. They are essentially register updates
and we use this fact to extract them and generate a list of WAs applied.
This list is also exported via debugfs file and it is used to validate their
st
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
> Workarounds for bdw are currently applied in init_clock_gating() but they
> are lost following a gpu reset. Some of the WA registers are part of register
> state context and they are restored with every context switch so initializing
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of alistair.mcau...@intel.com
> Sent: Friday, August 15, 2014 6:52 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3] drm/i915: Rework GPU reset sequence to
> match
Currently in BDW, workarounds are initialized in init_clock_gating() but
some of them are lost followed by a gpu reset. The solution is to apply
them in golden render state which keeps them valid when starting with an
uninitialized state after reset.
Arun Siluvery (2):
tools/null_state_render: A
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workarounds.
Signed-off-by: Arun Siluvery
---
tests/Makefile.sources | 1 +
tests/gem_worka
On Wed, Aug 20, 2014 at 03:19:17PM +0100, Arun Siluvery wrote:
> Workarounds for bdw are currently applied in init_clock_gating() but they
> are lost following a gpu reset. Some of the WA registers are part of register
> state context and they are restored with every context switch so initializing
Some workaround registers are part of register state context and they are
restored with every context switch so initializing them in golden render state
ensures that they are applied even when we start with an uninitialized context
or during hw initialization followed by a reset.
Signed-off-by: Ar
On Wed, Aug 20, 2014 at 02:46:37PM +, Daniel, Thomas wrote:
>
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of alistair.mcau...@intel.com
> > Sent: Friday, August 15, 2014 6:52 PM
> > To: intel-gfx@lists.freedesktop.org
> >
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Wednesday, August 20, 2014 3:58 PM
> To: Daniel, Thomas
> Cc: Mcaulay, Alistair; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: Rework GPU reset sequence to
> match driver
A pending commit removes synchronous mode from switch_mm. This breaks
execlists because switch_mm will always try to write to the legacy ring
buffer.
Return immediately from i915_ppgtt_init_gw in execlists mode.
No longer check for execlists mode in gen8_ppgtt_enable() because this
will no longer
These two functions make no sense in an Logical Ring Context & Execlists
world.
v2: We got rid of lrc_enabled and centralized everything in the sanitized
i915.enable_execlists instead.
Signed-off-by: Oscar Mateo
v3: Rebased. Corrected a typo in comment for i915_switch_context and
added a comme
On Wed, Aug 20, 2014 at 02:45:00PM +0100, Thomas Wood wrote:
> Make sure plane rotation is reset correctly when restoring the fbdev
> configuration by using drm_mode_plane_set_obj_prop which calls the
> driver's set_property callback.
>
> The rotation reset feature was introduced in commit 9783de2
On Wed, Aug 20, 2014 at 04:29:24PM +0100, Thomas Daniel wrote:
> These two functions make no sense in an Logical Ring Context & Execlists
> world.
>
> v2: We got rid of lrc_enabled and centralized everything in the sanitized
> i915.enable_execlists instead.
>
> Signed-off-by: Oscar Mateo
>
> v3
On 20 August 2014 15:52, Arun Siluvery wrote:
> Some of the workarounds are lost followed by a gpu reset, suspend/resume;
> this patch adds a test which compares register state before and after
> the test scenario.
>
> This test currently verifies only bdw workarounds.
Just a few points from an i
> -Original Message-
> From: Daniel, Thomas
> Sent: Friday, August 15, 2014 9:44 AM
> To: 'Daniel Vetter'
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 27/43] drm/i915/bdw: Render state init for
> Execlists
>
>
>
> > -Original Message-
> > From: Daniel
On Wed, Aug 20, 2014 at 03:21:55PM +, Mcaulay, Alistair wrote:
> It is not the same. This is a special case when re-initialising the hw. This
> flag is to allow gem_init_hw() to complete successfully during reset.
> At any other point during reset, -EAGAIN should be returned.
Indeed. You've
On 20/08/2014 16:37, Thomas Wood wrote:
On 20 August 2014 15:52, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workaro
Hi Jani - the DRM_DEBUG_KMS is part of the DRM_DEBUG_CODE preprocessor
macro and thus not available unavailable in a non-debug build kernel from
my understanding.
The issue we have seen many times is that the BIOS (firmware) team does
not set the T3 value correctly in the VBT table of the BIOS (or
On Wed, Aug 20, 2014 at 06:03:52PM +, Wilde, Martin wrote:
> Hi Jani - the DRM_DEBUG_KMS is part of the DRM_DEBUG_CODE preprocessor
> macro and thus not available unavailable in a non-debug build kernel from
> my understanding.
>
> The issue we have seen many times is that the BIOS (firmware)
From: Vedang Patel
The patch introduces fixes for the debugfs attributes emitted by
the i915 driver for GEN8. Currently, it is not emitting the correct
attributes which include the status of RC6 states.
Change-Id: Ib2068a0cac9a5wq3f228e547fa1a097ad369d242df
Signed-off-by: Vedang Patel
---
dri
Daniel Vetter writes:
> On Wed, Aug 13, 2014 at 10:25 PM, Rusty Russell wrote:
>> Jani Nikula writes:
>>> This is a generic version of Daniel's patch [1] letting us have unsafe
>>> module parameters (experimental, debugging, testing, etc.) that taint
>>> the kernel when set. Quoting Daniel,
>>
>
On Wednesday 20 August 2014 04:26 PM, Ville Syrjälä wrote:
On Thu, Aug 21, 2014 at 01:37:09PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
True, but...
This is a regression from
commit abd58f0175915be
From: Deepak S
Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8
This is a regression from
commit abd58f0175915bed644aa67c8f69dc571b8280e0
Author: Ben Widawsky
Date: Sat Nov 2 21:07:09 2013 -0700
drm/i915/bdw: Implement interrupt changes
v2: Kil
From: Sonika Jindal
v2: Moving setting of plane members in the end to take care of failure cases and
not-visible cases (Matt).
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_display.c | 38 +++---
1 file changed, 31 insertions(+), 7 deletions(-)
diff
From: Sonika Jindal
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issuein
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