On Thu, 04 Sep 2014, Daniel Vetter wrote:
> More important is to Cc: all the people (in the commit message to make
> sure it doesn't get lost, git send-email then takes care of
> everything) who commented on that patch so that they'll see your
> updated version.
git send-email taking care of ever
On Thu, Sep 04, 2014 at 08:15:32PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 02, 2014 at 02:57:37PM +0100, Chris Wilson wrote:
> > If we successfully confuse the hardware, and cause it to drop a queued
> > pageflip, we wait for 60s and issue a warning before continuing on with
> > the modeset. Howe
On Fri, Sep 05, 2014 at 07:13:23AM +0100, Chris Wilson wrote:
> Hi Daniel,
>
> these are the first two patches in the flip boosting series pushed ahead
> of the request rework. These are the interesting ones as they help paper
> over oddities in our hardware and prevent the driver from wedging its
On Fri, Sep 05, 2014 at 09:27:16AM +0200, Daniel Vetter wrote:
> On Thu, Sep 04, 2014 at 08:15:32PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 02, 2014 at 02:57:37PM +0100, Chris Wilson wrote:
> > > If we successfully confuse the hardware, and cause it to drop a queued
> > > pageflip, we wait for
On Thu, Sep 04, 2014 at 06:22:47PM -0400, Rodrigo Vivi wrote:
> Lets just do this small sleep to allow human eyes to see what is happening,
> but let's avoid any kind of interference on the actual test.
>
> Signed-off-by: Rodrigo Vivi
> ---
> tests/kms_psr_sink_crc.c | 6 +-
> 1 file changed
On Thu, Sep 04, 2014 at 06:22:49PM -0400, Rodrigo Vivi wrote:
> This helps to debug and check if the CRC you are reading correspond
> what you are seeing on the screen
>
>
> Signed-off-by: Rodrigo Vivi
> ---
> tests/kms_psr_sink_crc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/
On Thu, Sep 04, 2014 at 08:31:07PM +0200, Daniel Vetter wrote:
> Readding intel-gfx since this is interesting for everyone.
>
> On Thu, Sep 4, 2014 at 8:09 PM, Clint Taylor
> wrote:
> > I will attempt to improve my patch submissions process. I also need to start
> > annotating version in the sub
- Use keys in just one env variable to enable/disable it.
- Add an informational message so that the users knows when to press
the key (more useful over ssh than when run on the terminal ofc).
- Improve the documentation so that it's clearer how to use this
when running tests.
Cc: Rodrigo Vivi
On Thu, Sep 04, 2014 at 06:22:51PM -0400, Rodrigo Vivi wrote:
> This allows to run tests with psr disabled and know what to expect when
> PSR is actually enabled.
>
> Signed-off-by: Rodrigo Vivi
I don't really follow what this is useful for ... Can you please elaborate
how this is used and how i
On Thu, Sep 04, 2014 at 10:47:41AM -0700, Clint Taylor wrote:
> On 08/26/2014 07:06 AM, Ville Syrjälä wrote:
> > On Tue, Aug 26, 2014 at 03:36:07PM +0200, Daniel Vetter wrote:
> >> On Tue, Aug 26, 2014 at 04:21:00PM +0300, Jani Nikula wrote:
> >>> On Tue, 26 Aug 2014, Ville Syrjälä wrote:
> O
On Fri, Sep 05, 2014 at 08:52:31AM +0200, Daniel Vetter wrote:
> - Use keys in just one env variable to enable/disable it.
> - Add an informational message so that the users knows when to press
> the key (more useful over ssh than when run on the terminal ofc).
> - Improve the documentation so th
On Thu, Sep 04, 2014 at 12:27:09PM +0100, Damien Lespiau wrote:
> From: Pradeep Bhat
>
> This patch reads the memory latency values for all the 8 levels for
> SKL. These values are needed for the Watermark computation.
>
> v2: Incorporated the review comments from Damien on register
> indent
On Fri, Sep 05, 2014 at 11:25:30AM +0300, Ville Syrjälä wrote:
> > +/* SKL GT Driver Mailbox registers for reading memory latencies */
> > +#define GEN9_MAILBOX_DATA1 0x13812C
> > +#define GEN9_MAILBOX_READ_MEM_LAT(0x6)
> > +#define GEN9_MAILBOX_READ_TIMEOUT150
>
> Time
On Thu, Sep 04, 2014 at 05:55:24PM -0700, Rodrigo Vivi wrote:
> adding suspend_autoresume on primary tests like this:
> @ -470,6 +472,8 @@ igt_main
> data.test_plane = PRIMARY;
> data.op = op;
> run_test(&data);
> +
On Thu, Sep 04, 2014 at 05:40:05PM -0700, Rodrigo Vivi wrote:
> Here goes results on BDW with pure today's nightly (with idle_frame=1)
>
> # First run
>
> IGT-Version: 1.7-gd4b43f0 (x86_64) (Linux: 3.17.0-rc2+ x86_64)
> Subtest primary_page_flip: SUCCESS
> Subtest primary_mmap_gtt: SUCCESS
> Tes
On Thu, Sep 04, 2014 at 09:43:45PM +0100, Chris Wilson wrote:
> Oops, apparently intel_hdmi/intel_dp is the encoder - an object with a
> distinct lifetime to the connector, and so we cannot simply reuse the
> common function to unset and free the edid.
>
> Signed-off-by: Chris Wilson
Queued for
On Fri, Sep 05, 2014 at 09:29:33AM +0100, Damien Lespiau wrote:
> On Fri, Sep 05, 2014 at 11:25:30AM +0300, Ville Syrjälä wrote:
> > > +/* SKL GT Driver Mailbox registers for reading memory latencies */
> > > +#define GEN9_MAILBOX_DATA1 0x13812C
> > > +#define GEN9_MAILBOX_READ_MEM_
On Thu, Sep 04, 2014 at 06:07:02PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> If we don't cancel them, we may end up running them while the device
> is runtime suspended, which will trigger lots and lots of WARNs on
> dmesg.
>
> Regression introduced by:
> commit c76bb61a71083b2d90504cc
On Fri, Sep 05, 2014 at 08:31:20AM +0100, Chris Wilson wrote:
> On Fri, Sep 05, 2014 at 09:27:16AM +0200, Daniel Vetter wrote:
> > On Thu, Sep 04, 2014 at 08:15:32PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 02, 2014 at 02:57:37PM +0100, Chris Wilson wrote:
> > > > If we successfully confuse th
On Thu, Sep 04, 2014 at 12:53:39PM -0700, Rodrigo Vivi wrote:
> On Thu, Sep 4, 2014 at 1:06 AM, Ville Syrjälä > wrote:
>
> > On Wed, Sep 03, 2014 at 10:49:57PM -0400, Rodrigo Vivi wrote:
> > > Now that we are tracking psr states on Software side we don't need HW
> > help anymore.
> > > So we can
Signed-off-by: Thomas Wood
---
tests/kms_3d.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/kms_3d.c b/tests/kms_3d.c
index ddf4dc6..c11873b 100644
--- a/tests/kms_3d.c
+++ b/tests/kms_3d.c
@@ -60,7 +60,8 @@ igt_simple_main
&length);
This updated and rebased series fixes various issues with the previous one and
also skips testing on gen 7 and 8 where it is not currently possible to force
the HDMI and DP connector states. There is also a small documentation fix for
igt_create_fb.
Thomas Wood (6):
lib: add kmstest_edid_add_3d
Forcing HDMI or DP connectors on gen 7 and 8 doesn't currently work, so
fail early to allow the test to skip if required.
Signed-off-by: Thomas Wood
---
lib/igt_kms.c | 12
1 file changed, 12 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 0dc46f9..e9455aa 100644
---
kmstest_edid_add_3d adds an EDID extension block with 3D support to a
copy of the specified EDID.
v2: Avoid using an invalid CEC SPA (Clint Taylor)
Signed-off-by: Thomas Wood
---
lib/igt_kms.c | 80 +++
lib/igt_kms.h | 1 +
2 files change
Make sure the parameters in the prototype and implementation of
igt_create_fb match and are complete so that the documentation is
correct.
Signed-off-by: Thomas Wood
---
lib/igt_fb.c | 2 +-
lib/igt_fb.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/igt_fb.c b/lib/ig
Add a test to verify creation and use of 3D stereo modes.
v2: update for API changes
Signed-off-by: Thomas Wood
---
tests/.gitignore | 1 +
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_3d.c | 120 +
4 f
Move create_stereo_fb from testdisplay to igt_create_stereo_fb in igt_fb
so that it can be used in other tests.
v2: update for new igt_create_fb API
add parameters for format and tiling
remove some old debug code
Signed-off-by: Thomas Wood
---
lib/Makefile.am | 4 +-
lib/igt_fb.c
Avoid calling functions in igt_reset_connectors that are not safe to use
in signal handlers by keeping a list of connectors that have been
modified, instead of enumerating all connectors.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83498
Cc: Paulo Zanoni
Signed-off-by: Thomas Wood
---
On Fri, Sep 05, 2014 at 11:55:19AM +0100, Thomas Wood wrote:
> Avoid calling functions in igt_reset_connectors that are not safe to use
> in signal handlers by keeping a list of connectors that have been
> modified, instead of enumerating all connectors.
>
> Bugzilla: https://bugs.freedesktop.org/
On Fri, Sep 05, 2014 at 10:52:08AM +0100, Thomas Wood wrote:
> Forcing HDMI or DP connectors on gen 7 and 8 doesn't currently work, so
> fail early to allow the test to skip if required.
>
> Signed-off-by: Thomas Wood
> ---
> lib/igt_kms.c | 12
> 1 file changed, 12 insertions(+)
>
Ville found out that the DATA1 register exists since SNB with some
scarce apparitions in the specs throughout the times. In his own words:
Also according to Bspec the mailbox data1 register already existed
since snb. The hsw cdclk change sequence also mentions that it should
be set to 0, bu
Ville had 2 comments on the SKL memory latency patch that are better addressed
as separate patches on top.
Patch 1: SKL unifies the plane hw and their latencies to fech data from memory
is identical. So SKL only needs a single array. We save some room by using
anymous union/structs. However, last
Suggested-by: Ville Syrjälä
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0baf7f3..8471d12 1006
On Fri, Sep 05, 2014 at 11:42:32AM +0300, Ville Syrjälä wrote:
> On Fri, Sep 05, 2014 at 09:29:33AM +0100, Damien Lespiau wrote:
> > On Fri, Sep 05, 2014 at 11:25:30AM +0300, Ville Syrjälä wrote:
> > > > +/* SKL GT Driver Mailbox registers for reading memory latencies */
> > > > +#define GEN9_MAILB
(adding Daisy Sun to the conversation)
2014-09-04 18:07 GMT-03:00 Paulo Zanoni :
> From: Paulo Zanoni
>
> If we don't cancel them, we may end up running them while the device
> is runtime suspended, which will trigger lots and lots of WARNs on
> dmesg.
>
> Regression introduced by:
> commit c76bb
Use full PPGTT as the default option in gen7.
Note that aliasing PPGTT is the default option for gen8 (see HAS_PPGTT).
This may well come back to bite me later.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
Hi all,
New -testing cycle with cool stuff:
- final bits (again) for the rotation support (Sonika Jindal)
- support bl_power in the intel backlight (Jani)
- vdd handling improvements from Ville
- i830M fixes from Ville
- piles of prep work all over to make skl enabling just plug in (Damien, Sonika
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f79473b3348b..ba96179eea0e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/
I really didn't like this implementation because I'm using the global
variable in the test case.
So I think also providing a define igt_skip_function_on_dryrun() if
(igt_dry_run) return 0 is more igt like.
For psr I need a way to run the testcases even when PSR is disabled to know
what to expect
On Wed, 27 Aug 2014 19:43:57 +0100
Chris Wilson wrote:
> On Wed, Aug 27, 2014 at 10:11:34AM +0200, Daniel Vetter wrote:
> > A bunch of warnings fire on some ->irq_postinstall hooks since those
> > can enable interrupts (e.g. rps interrupts). And then our ordering
> > self-checks fire and complain
With the new vma/ppgtt lifetime rules, the ppgtt (vm) could be removed
after i915_vma_unbind.
Use list_for_each_entry_safe() to prevent this use-after-free.
Found with gem_persistent_relocs and gem_evict_everything igt tests.
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
---
drivers/gpu/drm
On Fri, Aug 08, 2014 at 03:54:04PM +0200, Thomas Jarosch wrote:
> New Intel G3258 CPU, new MSI board, same problem:
> The GPU interrupt fired like crazy on monitor unplug.
>
> lspci output:
> 00:02.0 VGA compatible controller: Intel Corporation Device 0402 (rev 06)
> Subsystem: Micro-Star
2014-08-04 7:51 GMT-03:00 Rodrigo Vivi :
> According to spec FBC on BDW and HSW are identical without any gaps.
> So let's copy the nuke and let FBC really start compressing stuff.
>
> Without this patch we can verify with false color that nothing is being
> compressed. With the nuke in place and f
From: Ville Syrjälä
The spec says:
"For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata,
GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31
(DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in
both the DPLL A Control Register (06014h-06017h) and DPLL B Co
From: Ville Syrjälä
830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO). Limit the watermark value to at least 8 cache lines.
That also matches the burst size we use on most platforms. BSpec seems
On 05.09.2014 20:54, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO). Limit the watermark value to at least 8 cache lines.
That also m
On Fri, Sep 5, 2014 at 11:28 AM, Paulo Zanoni wrote:
> 2014-08-04 7:51 GMT-03:00 Rodrigo Vivi :
> > According to spec FBC on BDW and HSW are identical without any gaps.
> > So let's copy the nuke and let FBC really start compressing stuff.
> >
> > Without this patch we can verify with false color
From: Gustavo Padovan
This new struct will be the storage of src and dst coordinates
between the check and commit stages of a plane update.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/i915/intel_drv.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Gustavo Padovan
Due to the upcoming atomic modesetting feature we need to separate
some update functions into a check step that can fail and a commit
step that should, ideally, never fail.
This commit splits intel_update_plane() and its commit part can still
fail due to the fb pinning proc
From: Gustavo Padovan
This is the beginning of the work to prepare i915 for the upcoming
atomic modesetting API. Here we split the plane update fucntions in
the check and commit states.
v2: use struct intel_plane_state to keep states between check and
commit stages.
v3: take Ville's comments:
From: Gustavo Padovan
Due to the upcoming atomic modesetting feature we need to separate
some update functions into a check step that can fail and a commit
step that should, ideally, never fail.
The commit part can still fail, but that should be solved in another
upcoming patch.
Signed-off-by:
From: Gustavo Padovan
As a preparation for atomic updates we need to split the code to check
everything we are going to commit first. This patch starts the work to
split intel_primary_plane_setplane() into check() and commit() parts.
More work is expected on this to get a better split of the two
From: Gustavo Padovan
Due to the upcoming atomic modesetting feature we need to separate
some update functions into a check step that can fail and a commit
step that should, ideally, never fail.
The commit part can still fail, but that should be solved in another
upcoming patch.
Signed-off-by:
Avoid touching fbc register when fbc is disabled.
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45f71e6..c3d3439 100644
--- a/drivers
The sw cache clean on gen8 is a tempoorary workaround because we cannot
set cache clean on blt ring with risk of hungs. So we are doing the cache clean
on sw.
However we are doing much more than needed. Not only when using blt ring.
So, with this extra w/a we minimize the ammount of cache cleans a
As Paulo told the part 2 of his proposal is still missing and we will get
the WARN of reading fbc register at fbc_enabled when on runtime_suspend...
But I couldn't find the propper place to check for intel_crtc->active. This
was another issue reported by power team that on screen off there was to
Hey Daniel,
funny story: Remember that with idle_frames=1 on BDW it was working but it
was faililng on HSW?
So, with these 2 patches applied now BDW PSR fails like HSW!!!
Ville, any thoughts on this?
On Fri, Sep 5, 2014 at 1:57 PM, Rodrigo Vivi wrote:
> The sw cache clean on gen8 is a tempoor
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