On Mon, Nov 24, 2014 at 02:16:25PM +, Thomas Wood wrote:
Use igt_debugfs_open to open the connector file, since the
forced_connectors array now only stores the connector path relative to
the debugfs path. Also add some extra error checking to ensure a test
failure if the reset fails.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 367/367
On Mon, Nov 24, 2014 at 05:02:45PM +0100, Daniel Vetter wrote:
Apparently PCH fifo underruns are tricky, we have plenty reports that
we see the occasional underrun (especially at boot-up).
So for a change let's see what happens when we don't re-enable pch
fifo underrun reporting when the
On Mon, Nov 24, 2014 at 08:46:22PM +0100, Daniel Vetter wrote:
On Mon, Nov 24, 2014 at 5:56 PM, Egbert Eich e...@suse.de wrote:
Before testing if the panel VDD is enabled on eDP cancel any pending
disable worker. This makes sure the worker doesn't fire when we expect
VDD to be enabled.
On Tue, Nov 25, 2014 at 9:43 AM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Mon, Nov 24, 2014 at 08:46:22PM +0100, Daniel Vetter wrote:
On Mon, Nov 24, 2014 at 5:56 PM, Egbert Eich e...@suse.de wrote:
Before testing if the panel VDD is enabled on eDP cancel any pending
disable
From: Akash Goel akash.g...@intel.com
A new subtest added to validate the new version of gem_mmap ioctl,
for creating the wc mappings, on yet to be supported flags.
Older kernel is also checked against the flags field, which should
be treated as a don't care by it.
Signed-off-by: Akash Goel
On Mon, 24 Nov 2014, Egbert Eich e...@suse.de wrote:
For eDP in the Intel driver pps_lock()/unlock() need to be called before
initiating an I2C/AUX channel transfer. These operations can be quite
expensive - especially on values for HZ lower than 1000.
It
Dynamic context pinning for LRCs introduced a leak in legacy mode.
Reinstate context unreference in i915_gem_free_request for legacy contexts.
Leak reported by i-g-t/drv_module_reload fixed by this patch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86507
Signed-off-by: Thomas Daniel
Looks good to me.
Reviewed-by: John Harrisonjohn.c.harri...@intel.com
On 25/11/2014 10:39, Thomas Daniel wrote:
Dynamic context pinning for LRCs introduced a leak in legacy mode.
Reinstate context unreference in i915_gem_free_request for legacy contexts.
Leak reported by
Daniel Vetter writes:
On Mon, Nov 24, 2014 at 5:56 PM, Egbert Eich e...@suse.de wrote:
Before testing if the panel VDD is enabled on eDP cancel any pending
disable worker. This makes sure the worker doesn't fire when we expect
VDD to be enabled.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 367/367
On Tue, Nov 25, 2014 at 02:28:52PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
A new subtest added to validate the new version of gem_mmap ioctl,
for creating the wc mappings, on yet to be supported flags.
Older kernel is also checked against the flags field,
On Mon, Nov 24, 2014 at 02:32:25PM +, Dave Gordon wrote:
On 24/11/14 10:04, Daniel Vetter wrote:
On Tue, Nov 18, 2014 at 08:07:22PM +, Dave Gordon wrote:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ae09258..a08ae65 100644
This reverts commit c211a47c2c28562f8a3fff9e027be1a3ed9e154a.
This causes an unwarranteed API break for existing and active userspace.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 90 +
1 file changed, 90
On Tue, Nov 25, 2014 at 12:41:16PM +0100, Daniel Vetter wrote:
On Mon, Nov 24, 2014 at 02:32:25PM +, Dave Gordon wrote:
On 24/11/14 10:04, Daniel Vetter wrote:
On Tue, Nov 18, 2014 at 08:07:22PM +, Dave Gordon wrote:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
Before testing if the panel VDD is enabled on eDP cancel any pending
disable worker. This makes sure the worker will be triggered with a
delay from the last time edp_panel_vdd_schedule_off() is called, not
the first time. This avoids unnecessary overhead.
Before suspending, we wait upon the outstanding GPU requests and flush
our pending idle handlers. This should downclock the GPU to its lowest
power state. Add a WARN to check that the delayed tasks were run and did
their job properly.
Suggested-by: Akash Goel akash.g...@intel.com
Signed-off-by:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of john.c.harri...@intel.com
Sent: Monday, November 24, 2014 6:49 PM
To: Intel-GFX@Lists.FreeDesktop.Org
Subject: [Intel-gfx] [PATCH v3 00/28] Replace seqno values with request
structures
On Tue, Nov 25, 2014 at 11:42:56AM +, Chris Wilson wrote:
This reverts commit c211a47c2c28562f8a3fff9e027be1a3ed9e154a.
This causes an unwarranteed API break for existing and active userspace.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Hm, SNA still seems to be able to cope
On Tue, Nov 25, 2014 at 01:01:39PM +0100, Daniel Vetter wrote:
On Tue, Nov 25, 2014 at 11:42:56AM +, Chris Wilson wrote:
This reverts commit c211a47c2c28562f8a3fff9e027be1a3ed9e154a.
This causes an unwarranteed API break for existing and active userspace.
Signed-off-by: Chris
On Mon, Nov 24, 2014 at 09:43:12PM +0100, Daniel Vetter wrote:
Note that we need the rpm_get/put to make power_is_enabled work
properly.
I still don't get that. intel_display_power_is_enabled() only checks for
states kept in dev_priv. In particular, it doesn't touch the hardware
and it looks at
On Tue, Nov 25, 2014 at 12:29:00PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Updates in forcewake range for Render/Media/Common
power wells for Gen9.
Signed-off-by: Akash Goel akash.g...@intel.com
Signed-off-by: Zhe Wang zhe1.w...@intel.com
Reviewed-by:
On Mon, Nov 24, 2014 at 06:28:49PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Clear the video overlay state on GPU reset. Any pending overlay request
in the ring has been nuked, and the display itself gets reset. So we
pretty much lose all
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 367/367
On Fri, Nov 21, 2014 at 09:54:27PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
915/945 have the same reset registers as 965, so share the code.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
I didn't find the gmch docs anywhere
On Mon, Nov 24, 2014 at 08:29:40AM -0800, Rodrigo Vivi wrote:
From: Zhipeng Gong zhipeng.g...@intel.com
On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and
On Mon, Nov 24, 2014 at 08:29:46AM -0800, Rodrigo Vivi wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Previously, this was restricted to only operate on bound objects - to
make pointer access through the GTT to the object coherent with writes
to and from the GPU. A second usecase is
On Tue, Nov 25, 2014 at 12:54:57PM +0100, Egbert Eich wrote:
Before testing if the panel VDD is enabled on eDP cancel any pending
disable worker. This makes sure the worker will be triggered with a
delay from the last time edp_panel_vdd_schedule_off() is called, not
the first time. This avoids
The crc code doesn't handle anything really that could drop the
register state (by design so that we have less complexity). Which
means userspace may only start crc capture once the pipe is fully set
up.
With an i-g-t patch this will be the case, but there's still the
problem that this results in
On Mon, Nov 24, 2014 at 06:16:22PM +0100, Egbert Eich wrote:
For eDP in the Intel driver pps_lock()/unlock() need to be called before
initiating an I2C/AUX channel transfer. These operations can be quite
expensive - especially on values for HZ lower than 1000.
On Tue, Nov 25, 2014 at 12:26:55PM +, Damien Lespiau wrote:
On Tue, Nov 25, 2014 at 12:29:00PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Updates in forcewake range for Render/Media/Common
power wells for Gen9.
Signed-off-by: Akash Goel
On Tue, Nov 25, 2014 at 12:06:33PM +, Chris Wilson wrote:
On Tue, Nov 25, 2014 at 01:01:39PM +0100, Daniel Vetter wrote:
On Tue, Nov 25, 2014 at 11:42:56AM +, Chris Wilson wrote:
This reverts commit c211a47c2c28562f8a3fff9e027be1a3ed9e154a.
This causes an unwarranteed API
On Tue, Nov 25, 2014 at 02:08:10PM +0100, Daniel Vetter wrote:
The crc code doesn't handle anything really that could drop the
register state (by design so that we have less complexity). Which
means userspace may only start crc capture once the pipe is fully set
up.
With an i-g-t patch this
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we just make sure vdd is off before suspending, but we don't
cancel the vdd off work. The work wil not touch vdd if
want_panel_vdd==false so in theory this is fine.
In the past that was perfectly fine since the vdd off work didn't do
That's the version actually taking the dev_priv-power_domains lock.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
On Tue, Nov 25, 2014 at 11:56:33AM +, Chris Wilson wrote:
Before suspending, we wait upon the outstanding GPU requests and flush
our pending idle handlers. This should downclock the GPU to its lowest
power state. Add a WARN to check that the delayed tasks were run and did
their job
-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Thursday, November 20, 2014 12:51 PM
To: Chris Wilson; Daniel, Thomas; intel-gfx@lists.freedesktop.org; akash goel
(akash.go...@gmail.com)
Subject: Re: [Intel-gfx]
On Tue, 2014-11-25 at 15:43 +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we just make sure vdd is off before suspending, but we don't
cancel the vdd off work. The work wil not touch vdd if
want_panel_vdd==false so in theory this is
On Tue, Nov 25, 2014 at 02:30:55PM +, Daniel, Thomas wrote:
-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Thursday, November 20, 2014 12:51 PM
To: Chris Wilson; Daniel, Thomas; intel-gfx@lists.freedesktop.org;
On Tue, Nov 25, 2014 at 02:44:33PM +, Chris Wilson wrote:
On Tue, Nov 25, 2014 at 02:30:55PM +, Daniel, Thomas wrote:
-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Thursday, November 20, 2014 12:51 PM
On Tue, Nov 25, 2014 at 01:45:41PM +, Damien Lespiau wrote:
That's the version actually taking the dev_priv-power_domains lock.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/drmtest.c | 2 +-
lib/igt_core.h | 2 +-
lib/intel_batchbuffer.c | 4 ++--
lib/ioctl_wrappers.c| 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index
Simple tests do not support subtests, so fail if igt_subtest is used in
one.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_core.c | 1 +
lib/tests/.gitignore | 1 +
lib/tests/Makefile.sources | 2 ++
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
tests/gem_tiled_swapping.c | 64 --
1 file changed, 34 insertions(+), 30 deletions(-)
diff --git a/tests/gem_tiled_swapping.c b/tests/gem_tiled_swapping.c
index 69d1cfa..11bb245 100644
---
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, November 25, 2014 4:00 PM
To: Chris Wilson; Daniel, Thomas; Daniel Vetter; intel-
g...@lists.freedesktop.org; akash goel (akash.go...@gmail.com)
Subject: Re: [Intel-gfx]
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 367/367
Daniel Vetter writes:
Imo this approach with overwrite all the entry points won't scale since
besides i2c and dpcd there will be more sooner or later (oui, dp mst, some
debugfs userspace dp aux tools, ...).
I think what we need is the same as in the i2c layer has with the
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 367/367
On Tue, Nov 25, 2014 at 02:34:02PM +0100, Daniel Vetter wrote:
On Tue, Nov 25, 2014 at 12:06:33PM +, Chris Wilson wrote:
On Tue, Nov 25, 2014 at 01:01:39PM +0100, Daniel Vetter wrote:
On Tue, Nov 25, 2014 at 11:42:56AM +, Chris Wilson wrote:
This reverts commit
On Tue, Nov 25, 2014 at 04:42:22PM +, Daniel, Thomas wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, November 25, 2014 4:00 PM
To: Chris Wilson; Daniel, Thomas; Daniel Vetter; intel-
So the problem with async commit (especially async modeset commit) is
that the legacy pointers only get updated after the point of no
return, in the async part of the modeset sequence. At least as
implemented by the current helper functions. This is done in the
set_routing_links function in
From: Dave Airlie airl...@redhat.com
At least on two MST devices I've tested with, when
they are link training downstream, they are totally
unable to handle aux ch msgs, so they defer like nuts.
I tried 16, it wasn't enough, 32 seems better.
This fixes one Dell 4k monitor and one of the
MST
From: Dave Airlie airl...@redhat.com
On MST systems the monitors don't appear when we set the fb up,
but plymouth opens the drm device and holds it open while they
come up, when plymouth finishes and lastclose gets called we
don't do the delayed fb probe, so the monitor never appears on the
On 26 November 2014 at 13:20, Tom Stellard t...@stellard.net wrote:
On Wed, Nov 26, 2014 at 01:17:22PM +1000, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
At least on two MST devices I've tested with, when
they are link training downstream, they are totally
unable to handle aux ch
From: Dave Airlie airl...@redhat.com
At least on two MST devices I've tested with, when
they are link training downstream, they are totally
unable to handle aux ch msgs, so they defer like nuts.
I tried 16, it wasn't enough, 32 seems better.
This fixes one Dell 4k monitor and one of the
MST
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 366/366
On Wed, Nov 26, 2014 at 01:17:23PM +1000, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
On MST systems the monitors don't appear when we set the fb up,
but plymouth opens the drm device and holds it open while they
come up, when plymouth finishes and lastclose gets called we
don't
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