If the firmware has declared more than 8 video output devices, and the
one that control the internal panel's backlight is listed after the
first 8 output devices, the _DOD will not include it due to the current
i915 operation region implementation. As a result, we will not create a
backlight
On Thu, Dec 11, 2014 at 05:33:00PM +, Tvrtko Ursulin wrote:
+struct vgt_if {
+uint64_t magic; /* VGT_MAGIC */
+uint16_t version_major;
+uint16_t version_minor;
+uint32_t vgt_id;/* ID of vGT instance */
+uint32_t rsv1[12]; /* pad to offset 0x40 */
On Thu, Nov 13, 2014 at 08:02:46PM +0800, Yu Zhang wrote:
Display switch logic is added to notify the host side that
current vGPU have a valid surface to show. It does so by
writing the display_ready field in PV INFO page, and then
will be handled in the host side. This is useful to avoid
On Thu, Dec 11, 2014 at 05:03:46PM +, Tvrtko Ursulin wrote:
Hi,
I'll try to do the detailed review of your series in the following few days.
I might ask some questions on the design also to help me understand the
bigger picture.
First thing, I see that patches are checkpatch.pl
On Mon, Dec 15, 2014 at 08:55:32AM +0100, Daniel Vetter wrote:
On Sun, Dec 14, 2014 at 03:37:36PM -0800, Ben Widawsky wrote:
On Sun, Dec 14, 2014 at 03:12:21PM +0200, Ville Syrjälä wrote:
On Sat, Dec 13, 2014 at 07:08:24PM -0800, Ben Widawsky wrote:
If we're moving a bunch of buffers
On Fri, Dec 12, 2014 at 07:16:34PM -0800, Rodrigo Vivi wrote:
On Mon, Dec 8, 2014 at 1:35 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Dec 05, 2014 at 08:40:42PM -0500, Rodrigo Vivi wrote:
Since active function on VLV immediately activate PSR let's give more
time for idleness.
v2:
On Thu, Dec 11, 2014 at 10:19:39AM +, Michel Thierry wrote:
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A short section describing background, implementation and intended usage.
v2:
* Align section name between template and DOC
On Fri, Dec 12, 2014 at 04:53:45PM -0800, Rodrigo Vivi wrote:
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
.. because it would be a waste of time, so move the place where the
check is done. Also, with this we won't risk
On Fri, Dec 12, 2014 at 04:55:52PM -0800, Rodrigo Vivi wrote:
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
This may save a few picoseconds on !HAS_FBC platforms. And it also
satisfies my OCD.
Signed-off-by: Paulo
On Fri, Dec 12, 2014 at 05:10:42PM -0800, Rodrigo Vivi wrote:
wondering if this fixes: https://bugs.freedesktop.org/show_bug.cgi?id=87143
Next time you digg out a bugzilla please ping it for testing. I've done
thatt now.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79
On Fri, Dec 12, 2014 at 05:23:24PM -0800, Rodrigo Vivi wrote:
I always ask myself if we should just clean the code and remove all
platforms before HSW that always had many fbc issues. So we could make
it simple and just do for pipe A for all platforms.
With frontbuffer tracking we should be
On Fri, Dec 12, 2014 at 05:05:41PM -0800, Rodrigo Vivi wrote:
On Mon, Dec 8, 2014 at 8:53 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Dec 08, 2014 at 02:09:15PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We want to port FBC to the frontbuffer tracking
On Thu, Dec 11, 2014 at 10:15:58AM +, Chris Wilson wrote:
On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote:
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Calling intel_runtime_pm_put() is illegal from a soft-irq
On Wed, Dec 10, 2014 at 04:56:39PM +, Daniel, Thomas wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Wednesday, December 10, 2014 4:44 PM
To: Intel Graphics Development
Cc: Daniel Vetter; Daniel, Thomas; Vetter, Daniel
Subject: [PATCH]
On Fri, Dec 12, 2014 at 02:34:37PM +, Tvrtko Ursulin wrote:
On 12/09/2014 05:29 AM, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
The pipe wm parameters is not correctly updated with sprite parameters
because it copies them for each plane from plane_list to
On Wed, Dec 10, 2014 at 05:11:09PM +, Dave Gordon wrote:
On 10/12/14 10:42, Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 12:59:08PM +, john.c.harri...@intel.com wrote:
From: Dave Gordon david.s.gor...@intel.com
There is a workaround for a hardware bug when reading the seqno from
On Mon, 15 Dec 2014, Aaron Lu aaron...@intel.com wrote:
If the firmware has declared more than 8 video output devices, and the
one that control the internal panel's backlight is listed after the
first 8 output devices, the _DOD will not include it due to the current
i915 operation region
On Wed, Dec 10, 2014 at 10:35:37PM +0200, Ville Syrjälä wrote:
On Wed, Dec 10, 2014 at 12:16:05PM -0800, Jesse Barnes wrote:
Should probably just init this in the GMbus code all the time, based on
the cdclk and HPLL like we do on newer platforms. Ville has code for
that in a rework branch,
On Fri, Dec 12, 2014 at 11:17:19AM +0200, Ville Syrjälä wrote:
On Wed, Dec 10, 2014 at 02:00:02PM -0800, Jesse Barnes wrote:
Should address a warning reported in #79824.
References: https://bugs.freedesktop.org/show_bug.cgi?id=79824
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
On Mon, 15 Dec 2014, Daniel Vetter dan...@ffwll.ch wrote:
Well I mostly run --strict since that checks for the alignment of
continuation lines for function parameters. Imo not following the i915
coding style for that looks a bit too jarring ;-)
Still checkpatch is just a tool and occasionally
On 12/15/2014 08:45 AM, Daniel Vetter wrote:
Nah, this is just a kernel cmdlineoption. So please boot with
i915.mmio_debug=1 added to the kernel cmdline, reproduce and then grab the
entire dmesg.
Thanks, Daniel
errm, I did it, rebooted, suspended and then the WARNING appeared:
Dec 12
On Fri, Dec 12, 2014 at 09:20:49AM +, Chris Wilson wrote:
On Fri, Dec 12, 2014 at 11:09:15AM +0200, Ville Syrjälä wrote:
On Thu, Dec 11, 2014 at 08:17:00AM +, Chris Wilson wrote:
In order to act as a full command barrier by itself, we need to tell the
pipecontrol to actually stall
On Thu, Dec 11, 2014 at 08:16:59AM +, Chris Wilson wrote:
In the gen7 pipe control there is an extra bit to flush the media
caches, so let's set it during cache invalidation flushes.
Cc: Simon Farnsworth si...@farnz.org.uk
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc:
On Thu, Dec 11, 2014 at 08:17:01AM +, Chris Wilson wrote:
There exists a current workaround to prevent a hang on context switch
should the ring go to sleep in the middle of the restore,
WaProgramMiArbOnOffAroundMiSetContext (applicable to all gen7+). In
spite of disabling arbitration
On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote:
Adding i915 module parameter for setting drrs_interval. If this param is
set to 0, then drrs is disabled. If changed in runtime, then the new interval
value will be considered for scheduling the next drrs work.
drrs_interval is
On Thu, Dec 11, 2014 at 02:22:53AM +0530, Vandana Kannan wrote:
Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
called as part of frontbuffer tracking.
Apart from calls as a result of GEM tracking to fb invalidate/flush, a
call has been added to invalidate fb obj
On Thu, Dec 11, 2014 at 02:22:49AM +0530, Vandana Kannan wrote:
This patch series inserts DRRS into frontbuffer tracking mechanism.
1. Previous submission for this feature was designed considering only eDP
DRRS. In this series, apart from following fb tracking, changes have been made
to make
On 12/15/2014 8:30 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 10:19:39AM +, Michel Thierry wrote:
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A short section describing background, implementation and intended usage.
v2:
* Align
On Thu, Dec 11, 2014 at 02:02:48PM +0200, Jani Nikula wrote:
On Thu, 11 Dec 2014, Thomas Daniel thomas.dan...@intel.com wrote:
Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915
On 12/11/2014 5:58 PM, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
On Thu, Dec 11, 2014 at 12:48:35PM +, Thomas Daniel wrote:
Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the
On Thu, Dec 11, 2014 at 12:48:35PM +, Thomas Daniel wrote:
Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When execlists submission is enabled, try full ppgtt by default.
Note, this patch considers that execlist support has been enabled by
default on Gen8.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
From: Deepak M m.dee...@intel.com
LFP brighness control from the VBT block 43 indicates which
controller is used for brightness.
LFP1 brightness control method:
Bit 7-4 = This field controller number of the brightnes controller.
0 = Controller 0
1 = Controller 1
2 = Controller 2
3 = Controller 3
On Thu, Dec 11, 2014 at 03:20:39PM +, Tvrtko Ursulin wrote:
On 12/11/2014 12:28 PM, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.
On Mon, Dec 15, 2014 at 10:24:53AM +0100, Toralf Förster wrote:
On 12/15/2014 08:45 AM, Daniel Vetter wrote:
Nah, this is just a kernel cmdlineoption. So please boot with
i915.mmio_debug=1 added to the kernel cmdline, reproduce and then grab the
entire dmesg.
Thanks, Daniel
errm, I
On Mon, Dec 15, 2014 at 03:58:21PM +0530, Vandana Kannan wrote:
From: Deepak M m.dee...@intel.com
LFP brighness control from the VBT block 43 indicates which
controller is used for brightness.
LFP1 brightness control method:
Bit 7-4 = This field controller number of the brightnes
On Wed, Dec 10, 2014 at 05:27:58PM +, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index de241eb..c6610bc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2098,8 +2098,7 @@ i915_gem_shrink(struct
On 15-Dec-14 3:17 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote:
Adding i915 module parameter for setting drrs_interval. If this param is
set to 0, then drrs is disabled. If changed in runtime, then the new interval
value will be considered for
On 12/15/2014 10:24 AM, Daniel Vetter wrote:
On Wed, Dec 10, 2014 at 05:27:58PM +, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index de241eb..c6610bc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
On Mon, Dec 15, 2014 at 8:31 AM, Daniel Vetter dan...@ffwll.ch wrote:
[---snip---]
Sorry for the delay. Absolutely no difference in the relevant parts of the
log. There could be the chance that something is hidden somewhere, so can
please grab a new set of logs but this time with
On Friday 12 December 2014 10:04 PM, Ville Syrjälä wrote:
On Sat, Dec 13, 2014 at 11:43:27AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
v2:
On Monday 15 December 2014 12:21 PM, Jani Nikula wrote:
On Fri, 12 Dec 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Fri, Dec 12, 2014 at 02:18:15PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Use new Sideband offset to read max/min/gaur freq
On 12/15/2014 10:11 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When execlists submission is enabled, try full ppgtt by default.
Note, this patch considers that execlist support has been enabled by
default on Gen8.
Signed-off-by: Michel Thierry
On 15.12.2014, Daniel Vetter wrote:
Can you please boot with drm.debug=0xf on both good and bad kernels and
then grab dmesg from each?
The output is attached. The dmesg log stops after runlevel 3 for the
3.18 kernel, because I'm not able to do anything in runlevel 5 with a
black screen.
To
On Thu, Dec 11, 2014 at 03:41:34PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Eliminate six needless spin lock/unlock pairs when writing ELSP.
RFC for now with some #define copy and paste.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Dave
On Thu, 11 Dec 2014, Todd Previte tprev...@gmail.com wrote:
This patch was part of [PATCH 05/10] drm/i915: Add debugfs interface for
Displayport debug and compliance testing. That patch has been split into
smaller patches for ease of review and integration.
This patch contains the
On Mon, Dec 15, 2014 at 12:46:09PM +0100, Emmanuel Benisty wrote:
On Mon, Dec 15, 2014 at 8:31 AM, Daniel Vetter dan...@ffwll.ch wrote:
[---snip---]
Sorry for the delay. Absolutely no difference in the relevant parts of the
log. There could be the chance that something is hidden
From: Paulo Zanoni paulo.r.zan...@intel.com
We want to port FBC to the frontbuffer tracking infrastructure, but
for that we need to know what caused the object invalidation/flush so
we can react accordingly: CPU mmaps need manual, GTT mmaps and
flips don't need handling and ring rendering needs
From: Paulo Zanoni paulo.r.zan...@intel.com
Kill the blt/render tracking we currently have and use the frontbuffer
tracking infrastructure.
Don't enable things by default yet.
v2: (Rodrigo) Fix small conflict on rebase and typo at subject.
v3: (Paulo) Rebase on RENDER_CS change.
Reviewed-by:
On 15-Dec-14 3:30 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:49AM +0530, Vandana Kannan wrote:
This patch series inserts DRRS into frontbuffer tracking mechanism.
1. Previous submission for this feature was designed considering only eDP
DRRS. In this series, apart from following
On 15-Dec-14 3:27 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:53AM +0530, Vandana Kannan wrote:
Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
called as part of frontbuffer tracking.
Apart from calls as a result of GEM tracking to fb invalidate/flush, a
On Mon, Dec 15, 2014 at 04:25:32PM +0530, Kannan, Vandana wrote:
On 15-Dec-14 3:17 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote:
Adding i915 module parameter for setting drrs_interval. If this param is
set to 0, then drrs is disabled. If changed
On Mon, Dec 15, 2014 at 12:47:14PM +, Michel Thierry wrote:
On 12/15/2014 10:11 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When execlists submission is enabled, try full ppgtt by default.
Note, this patch considers that execlist support has
On Mon, Dec 15, 2014 at 07:45:13PM +0530, Kannan, Vandana wrote:
On 15-Dec-14 3:27 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:53AM +0530, Vandana Kannan wrote:
Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
called as part of frontbuffer tracking.
On 15-Dec-14 7:46 PM, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 04:25:32PM +0530, Kannan, Vandana wrote:
On 15-Dec-14 3:17 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote:
Adding i915 module parameter for setting drrs_interval. If this param is
On Mon, Dec 15, 2014 at 03:22:08PM +0100, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 12:47:14PM +, Michel Thierry wrote:
On 12/15/2014 10:11 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When execlists submission is enabled, try full ppgtt by
When adding instructions to a legacy or LRC ringbuffer, the sequence of
emit() calls must be preceded by a call to intel(_logical)_ring_begin()
to reserve the required amount of space, and followed by a matching call
to intel(_logical)_ring_advance() (note that this used to trigger
immediate
On Mon, Dec 15, 2014 at 07:56:08PM +0530, Kannan, Vandana wrote:
On 15-Dec-14 7:46 PM, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 04:25:32PM +0530, Kannan, Vandana wrote:
On 15-Dec-14 3:17 PM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 02:22:57AM +0530, Vandana Kannan wrote:
On Fri, Dec 12, 2014 at 11:43:55AM +, Thomas Wood wrote:
On 12 December 2014 at 10:18, tim.g...@intel.com wrote:
From: Tim Gore tim.g...@intel.com
intel_sprite_on wont build on Android, due to use
of a particular API that has changed in Gmin
Signed-off-by: Tim Gore
On Fri, Dec 12, 2014 at 02:26:58PM +, Damien Lespiau wrote:
I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
chance to be working as well as prevous platforms.
Signed-off-by: Damien Lespiau
On Fri, Dec 12, 2014 at 07:06:24PM +0200, Ville Syrjälä wrote:
On Fri, Dec 12, 2014 at 05:57:38PM +0200, Imre Deak wrote:
After
commit a18c0af171bfb875012da26f23df051004726973
uthor: Thierry Reding tred...@nvidia.com
Date: Wed Dec 10 11:38:49 2014 +0100
drm: Zero out DRM
On 12/15/2014 2:28 PM, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 03:22:08PM +0100, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 12:47:14PM +, Michel Thierry wrote:
On 12/15/2014 10:11 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, December 15, 2014 2:41 PM
To: Wood, Thomas
Cc: Gore, Tim; Intel Graphics Development
Subject: Re: [Intel-gfx] [PATCH i-g-t] Demos/Android.mk: dont build
intel_sprite_on
On Fri, Dec 12, 2014 at 09:26:23AM +, Bloomfield, Jon wrote:
-Original Message-
From: Nguyen, Michael H
Sent: Thursday, December 11, 2014 8:13 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v7 5/5] drm/i915: Tidy up execbuffer
In Gen8+, full ppgtt needs execlist, otherwise the ctx switch can hang.
Also remove the current restriction, a user should be able to explicitly set
ppgtt=2.
Note, this patch considers that execlist support has been enabled by
default on Gen8.
v2: Remove non-default restriction and clarify
On Thu, Dec 11, 2014 at 03:48:20PM -0800, Ben Widawsky wrote:
On Thu, Dec 11, 2014 at 01:28:09PM -0800, Jordan Justen wrote:
This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.
Just so we have all the formally required pieces: Can you
On Fri, 12 Dec 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Wed, Dec 10, 2014 at 02:00:02PM -0800, Jesse Barnes wrote:
Should address a warning reported in #79824.
References: https://bugs.freedesktop.org/show_bug.cgi?id=79824
Signed-off-by: Jesse Barnes
On Mon, Dec 15, 2014 at 02:58:00PM +, Michel Thierry wrote:
In Gen8+, full ppgtt needs execlist, otherwise the ctx switch can hang.
Also remove the current restriction, a user should be able to explicitly set
ppgtt=2.
Note, this patch considers that execlist support has been enabled by
On Tue, Dec 16, 2014 at 05:39:19PM +0530, Deepak S wrote:
On Friday 12 December 2014 10:04 PM, Ville Syrjälä wrote:
On Sat, Dec 13, 2014 at 11:43:27AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead
On Thu, 04 Dec 2014, Imre Deak imre.d...@intel.com wrote:
On Thu, 2014-12-04 at 14:58 +0100, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 02:59:32PM +0200, Imre Deak wrote:
Atm, we don't disable RPS interrupts and related work items before
resetting the GPU. This may interfere with the
On Thu, Dec 11, 2014 at 02:02:52PM +0200, Ville Syrjälä wrote:
On Fri, Dec 12, 2014 at 02:18:16PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
With cherryview onwards, Gunit hardware itself save and restore all the
Gunit registers. Skipping the
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Mon, Dec 15, 2014 at 04:59:42PM +0200, Jani Nikula wrote:
On Fri, 12 Dec 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Wed, Dec 10, 2014 at 02:00:02PM -0800, Jesse Barnes wrote:
Should address a warning reported in #79824.
References:
On Mon, Dec 15, 2014 at 04:08:37PM +0100, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 02:58:00PM +, Michel Thierry wrote:
In Gen8+, full ppgtt needs execlist, otherwise the ctx switch can hang.
Also remove the current restriction, a user should be able to explicitly set
ppgtt=2.
Backtraces make me jump and this one is very noisy, please merge. :)
Reviewed-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
On 11/26/2014 02:21 PM, Michel Thierry wrote:
Otherwise, new platforms without workarounds will hit this warning for
every new context created.
Cc: Tvrtko Ursulin
On Mon, Dec 15, 2014 at 03:40:11PM +, Tvrtko Ursulin wrote:
Backtraces make me jump and this one is very noisy, please merge. :)
It's kinda the point ;-)
Reviewed-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Queued for -next, thanks for the patch.
-Daniel
On 11/26/2014 02:21 PM,
On Mon, Dec 15, 2014 at 02:51:03PM +, Gore, Tim wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, December 15, 2014 2:41 PM
To: Wood, Thomas
Cc: Gore, Tim; Intel Graphics Development
Subject: Re:
On 12/15/2014 11:16 AM, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 10:24:53AM +0100, Toralf Förster wrote:
On 12/15/2014 08:45 AM, Daniel Vetter wrote:
Nah, this is just a kernel cmdlineoption. So please boot with
i915.mmio_debug=1 added to the kernel cmdline, reproduce and then grab the
On Mon, Dec 15, 2014 at 10:41:52AM +0100, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 08:17:01AM +, Chris Wilson wrote:
There exists a current workaround to prevent a hang on context switch
should the ring go to sleep in the middle of the restore,
WaProgramMiArbOnOffAroundMiSetContext
2014-12-10 21:53 GMT-02:00 Todd Previte tprev...@gmail.com:
Move the DPCD read to the top and check for an interrupt from the sink to
catch
Displayport automated testing requests necessary to support Displayport
compliance
testing. The checks for active connectors and link status are moved
On Mon, 2014-12-15 at 16:56 +0100, Toralf Förster wrote:
On 12/15/2014 11:16 AM, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 10:24:53AM +0100, Toralf Förster wrote:
On 12/15/2014 08:45 AM, Daniel Vetter wrote:
Nah, this is just a kernel cmdlineoption. So please boot with
Atm, we don't disable RPS interrupts and related work items before
resetting the GPU. This may interfere with the following GPU
initialization and cause RPS interrupts to show up in PM_IIR too early
before calling gen6_enable_rps_interrupts() (triggering a WARN there).
Solve this by disabling RPS
Paulo noticed that we don't enable RPS interrupts via PM_IER in
gen6_enable_rps_interrupts(). This wasn't a problem so far, since the
only place we disabled RPS interrupts was during system/runtime suspend
and after that we reenable all interrupts in the IRQ pre/postinstall
hooks.
In the next
On Mon, Dec 15, 2014 at 04:24:48PM +, Chris Wilson wrote:
On Mon, Dec 15, 2014 at 10:41:52AM +0100, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 08:17:01AM +, Chris Wilson wrote:
There exists a current workaround to prevent a hang on context switch
should the ring go to sleep in
On Mon, 15 Dec 2014, Imre Deak imre.d...@intel.com wrote:
Atm, we don't disable RPS interrupts and related work items before
resetting the GPU. This may interfere with the following GPU
initialization and cause RPS interrupts to show up in PM_IIR too early
before calling
2014-12-10 21:53 GMT-02:00 Todd Previte tprev...@gmail.com:
The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
specifies that repeated AUX transactions after a failure (no response /
invalid response) must have a minimum delay of 400us before the resend can
occur. Tests
During plane operations, we read/write some registers that only operate
properly if we're not runtime suspended. At the moment we're not
holding the runtime PM reference across the whole plane operation, so
there's a potential for problems.
This issue was already partially addressed by commit
2014-12-15 16:11 GMT-02:00 Matt Roper matthew.d.ro...@intel.com:
During plane operations, we read/write some registers that only operate
properly if we're not runtime suspended. At the moment we're not
holding the runtime PM reference across the whole plane operation, so
there's a potential
On Thu, Dec 11, 2014 at 02:38:07PM +0200, Ander Conselvan de Oliveira wrote:
In function that define a local pipe_config variable to point to
crtc-config, replace remaining references to crtc-config with
the local variable. This makes the code more consistent and easier
to change in an
On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
So that we can get rid of the new_config pointer later.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30
On Mon, Dec 15, 2014 at 10:37:57AM -0800, Matt Roper wrote:
On Thu, Dec 11, 2014 at 02:38:07PM +0200, Ander Conselvan de Oliveira wrote:
In function that define a local pipe_config variable to point to
crtc-config, replace remaining references to crtc-config with
the local variable. This
On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
So that we can get rid of the new_config pointer later.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30
2014-12-10 21:53 GMT-02:00 Todd Previte tprev...@gmail.com:
This patch was previously part of [PATCH 05/10] drm/i915: Add debugfs
interface
for Displayport debug and compliance testing. Adds two support functions for
handling Displayport configuration parameters that are used for compliance
On Thu, Dec 11, 2014 at 02:38:10PM +0200, Ander Conselvan de Oliveira wrote:
To match the semantics of drm_crtc-state, which this will eventually
become.
@@ struct intel_crtc *crtc; @@
-crtc-config
+crtc-config
@@ struct intel_crtc *crtc; identifier member; @@
-crtc-config.member
On Mon, Dec 15, 2014 at 11:17:45AM -0800, Matt Roper wrote:
On Thu, Dec 11, 2014 at 02:38:08PM +0200, Ander Conselvan de Oliveira wrote:
So that we can get rid of the new_config pointer later.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
On 2014-12-15 06:59:16, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 03:48:20PM -0800, Ben Widawsky wrote:
On Thu, Dec 11, 2014 at 01:28:09PM -0800, Jordan Justen wrote:
This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.
Just so we
On Sun, Dec 14, 2014 at 08:06:20PM -0800, Jesse Barnes wrote:
On 12/14/2014 4:59 AM, Chris Wilson wrote:
One of the things wbinvd is considered evil for is that it blocks the
CPU for an indeterminate amount of time - upsetting latency critcial
aspects of the OS. For example, the x86/mm has
On Mon, Dec 15, 2014 at 08:20:50AM +, Chris Wilson wrote:
On Mon, Dec 15, 2014 at 08:55:32AM +0100, Daniel Vetter wrote:
On Sun, Dec 14, 2014 at 03:37:36PM -0800, Ben Widawsky wrote:
On Sun, Dec 14, 2014 at 03:12:21PM +0200, Ville Syrjälä wrote:
On Sat, Dec 13, 2014 at 07:08:24PM
From: Ben Widawsky b...@bwidawsk.net
When the original drm code was written there were no centralized functions for
doing a coordinated wbinvd across all CPUs. Now (since 2010) there are, so use
them instead of rolling a new one.
v2: On x86 UP systems the wbinvd_on_all_cpus() is defined as a
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