Mainly taking care of some register offsets, otherwise things are similar to
hsw. Also, programming ddi aux to use hardcoded values for psr data select.
v2: introduce EDP_PSR_AUX_BASE macro (Chris)
v3: Moving to HW tracking for SKL+ platforms, so activating source psr during
psr_enabling and
On 01/15/2015 08:50 PM, Matt Roper wrote:
On Thu, Jan 15, 2015 at 02:55:26PM +0200, Ander Conselvan de Oliveira wrote:
The previous patch changed the config field in intel_crtc to a pointer,
but to keep the mechanical changes (done with spatch) separate from the
new code, the pointer was made
From: Tim Gore tim.g...@intel.com
getsubopt is not available in android. The get option
doesn't really need sub-options, just display all the
current frequency settings (as per discussion with
Ben Widawsky)
Signed-off-by: Tim Gore tim.g...@intel.com
---
man/intel_gpu_frequency.man | 6 +++---
From: Chris Wilson ch...@chris-wilson.co.uk
Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
revert the crude hack
commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
Author: Paulo Zanoni paulo.r.zan...@intel.com
Date: Tue Apr 1 14:55:07 2014 -0300
drm/i915: don't
From: Mika Kuoppala mika.kuopp...@linux.intel.com
As we now have forcewake domains, take advantage of it
by putting the differences in gen fw handling in data rather
than in code.
In past we have opencoded this quite extensively as the fw handling
is in the fast path. There has also been a lot
From: Mika Kuoppala mika.kuopp...@linux.intel.com
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
v2: s/fw_domain/forcewake_domain (Jani)
v3: rebase
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala
From: Mika Kuoppala mika.kuopp...@linux.intel.com
There are multiple forcewake domains in newer architectures.
Rename 'i915_gen6_forcewake_count_info' debugfs entry to
'i915_forcewake_domains' to reflect this.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
From: Chris Wilson ch...@chris-wilson.co.uk
With gen 6 we don't need to take uncore lock as we
don't have anything to protect from concurrent access.
v2: rebase and account for gen9 changes
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk (v1)
Signed-off-by: Mika Kuoppala
From: Mika Kuoppala mika.kuopp...@linux.intel.com
We have multiple forcewake domains now on recent gens. Change the
function naming to reflect this.
v2: More verbose names (Chris)
v3: Rebase
v4: Rebase
v5: Add documentation for forcewake_get/put
Signed-off-by: Mika Kuoppala
From: Chris Wilson ch...@chris-wilson.co.uk
On user forcewake access, assert that runtime pm reference is held.
Fix and cleanup the callsites accordingly.
v2: Remove intel_runtime_pm_get() rebasehap (Deepak)
v3: use drivers own runtime state tracking as pm_runtime_active()
will return wrong
From: Mika Kuoppala mika.kuopp...@linux.intel.com
These two were using a fw dance logic where posting read was done
after both domain bit were set. When in other gens, the posting
read is done immediately after setting the forcewake bit for each
domain.
Now bring these in line with other gens.
From: Chris Wilson ch...@chris-wilson.co.uk
Introduce a structure to track the individual forcewake domains and use
that to eliminate duplicate logic.
v2: - Rebase on latest dinq (Mika)
- for_each_fw_domain macro (Mika)
- Handle reset atomically, keeping the timer running (Mika)
-
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Nick Hoath
Sent: Thursday, January 15, 2015 1:11 PM
To: intel-gfx@lists.freedesktop.org
Cc: daniel.vet...@ffwll.ch
Subject: [Intel-gfx] [PATCH 0/4] drm/i915: Untangle execlist tracking
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5588
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Tue, Jan 13, 2015 at 12:48:47AM +0100, Daniel Vetter wrote:
On Fri, Jan 09, 2015 at 02:21:15PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
915 doens't support hotplug at all, so we shouldn't try to pretend
otherwise in the SDVO code.
On Tue, Jan 13, 2015 at 12:46:53PM -0800, Kenneth Graunke wrote:
This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer. Certain workloads would run very slowly with
HiZ enabled, but run much faster with the hiz=false driconf option.
With this patch,
On Tue, Jan 13, 2015 at 12:08:11AM +0100, Daniel Vetter wrote:
On Fri, Jan 9, 2015 at 1:50 PM, Jani Nikula jani.nik...@intel.com wrote:
I have a slightly uneasy feeling about handing out drm_panel pointers
(both from here and of_drm_find_panel) without refcounting. If the panel
driver gets
wait_for_dsi_fifo_empty can be static in intel_dsi.c. No functional
changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 16
drivers/gpu/drm/i915/intel_dsi_cmd.c | 16
drivers/gpu/drm/i915/intel_dsi_cmd.h | 1 -
3
Add port parameter to wait_for_dsi_fifo_empty, and call it for each dsi
port.
We can now remove the transitional intel_dsi_pipe_to_port() function.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 17 ++---
drivers/gpu/drm/i915/intel_dsi.h | 12
Instead of having the for each dsi port loop within dpi_send_cmd(), add
a port parameter to the function and call it for each port instead.
This is a rewrite of
commit 4510cd779e5897eeb8691aecbd639bb62ec27d55
Author: Gaurav K Singh gaurav.k.si...@intel.com
Date: Thu Dec 4 10:58:51 2014 +0530
This series ports our DSI code over to the drm_panel and
mipi_dsi_host/mipi_dsi_device. There are some rough edges towards the
end of the series, see commit message for patch 8 for details.
Patches 1-6 are prep work, fairly independent
Patch 7 ports the driver over to drm_panel
Patches 8-10
This seems like the right thing to do. This also gets rid of a call to
intel_dsi_pipe_to_port() which we want to remove eventually.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Const is good for you. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
Add basic support for using the drm mipi dsi framework for DSI. We don't
use device tree which is pretty much required by mipi_dsi_host_register
and friends, and we don't have the kind of device model the functions
expect either. So we cheat and use it as a library to abstract what we
need: a
Replace intel_dsi_device and intel_dsi_dev_ops with drm_panel and
drm_panel_funcs. They are adequate for what we have now, and if we end
up needing more than this we should improve drm_panel. This will keep us
better aligned with the drm core infrastructure.
The panel driver initialization
All of these are replaced by the drm core mipi dsi functions.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 259 ---
drivers/gpu/drm/i915/intel_dsi_cmd.h | 72 --
2 files changed, 331 deletions(-)
diff --git
Use the drm core interfaces in preparation of removing our homebrew.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 52 +++---
1 file changed, 34 insertions(+), 18 deletions(-)
diff --git
No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 39 ++--
drivers/gpu/drm/i915/intel_dsi_cmd.c | 34 ---
drivers/gpu/drm/i915/intel_dsi_cmd.h | 5 -
3 files changed,
The removed functions can be resurrected in intel_dsi.c as need arises.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/intel_dsi.c | 1 -
drivers/gpu/drm/i915/intel_dsi_cmd.c | 117
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5591
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 353/353
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0
Based
From: Deepak S deepa...@linux.intel.com
CHV/BSW production system has new turbo offset to read different freq.
This series adds the support.
Deepak S (3):
drm/i915/chv: Populate total EU count on Cherryview
drm/i915: Increase the range of sideband address.
drm/i915: New offset for reading
From: Deepak S deepa...@linux.intel.com
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.
v2: reuse mask definitions INTEL_INFO() to get device info
From: Deepak S deepa...@linux.intel.com
Looks like latest BSW/CHV production system has sideband address 128.
Use u32 data types to cover new offset/address range :)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
When we transitioned to the atomic plane helpers in commit:
commit ea2c67bb4affa84080c616920f3899f123786e56
Author: Matt Roper matthew.d.ro...@intel.com
Date: Tue Dec 23 10:41:52 2014 -0800
drm/i915: Move to atomic plane helpers (v9)
one of the changes was
On Fri, Jan 16, 2015 at 08:42:16PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this
From: Satheeshakrishna M satheeshakrishn...@intel.com
This patch implements core logic of SKL display power well.
v2: Addressed Imre's comments
- Added respective DDIs under power well #1 and #2
- Simplified repetitive code in power well programming
v3: Implemented Imre's
From: Satheeshakrishna M satheeshakrishn...@intel.com
Adding new power doamins for AUX controllers
v2: Added new power domains in power_domain_str per Imre's comment
v3: Added AUX power domains to older platforms
v4: Rebase on top of POWER_DOMAIN_PLLS.
v5: Modified to address review comments
Those two patches implement power support for SKL. Patch 1 is already reviewed.
For the moment we don't do anything fancy with the AUX power domain, so the
series has no real impact on current hardware to ease its inclusion in 3.20.
--
Damien
Satheeshakrishna M (2):
drm/i915/skl: Adding
On Fri, 16 Jan 2015, Matt Roper matthew.d.ro...@intel.com wrote:
When we transitioned to the atomic plane helpers in commit:
commit ea2c67bb4affa84080c616920f3899f123786e56
Author: Matt Roper matthew.d.ro...@intel.com
Date: Tue Dec 23 10:41:52 2014 -0800
On Fri, Jan 16, 2015 at 08:42:18PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which
On Fri, Jan 16, 2015 at 08:42:17PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Looks like latest BSW/CHV production system has sideband address 128.
Use u32 data types to cover new offset/address range :)
Signed-off-by: Deepak S deepa...@linux.intel.com
On Fri, Jan 16, 2015 at 08:42:16PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this
From: Jesse Barnes jbar...@virtuousgeek.org
Per latest PM programming guide.
v2: the wrong flavour of the function updating the ring frequency was
called, leading to dead locks (Tvrtko)
v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien)
Signed-off-by: Jesse Barnes
From: Zhe Wang zhe1.w...@intel.com
Enable coarse power gating for Gen9. This feature allows render and
media engine to enter RC6 independently. Policies are configured
together with RC6. This feature will only be enabled when RC6 is
enabled.
Signed-off-by: Zhe Wang zhe1.w...@intel.com
v2: Use the new function, gen6_init_rps_frequencies() (Damien)
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com (v1)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Akash Goel akash.g...@intel.com
Updated the i915_drpc_info i915_gen6_forcewake_count debugfs interface
v2: Change all IS_GEN9() by gen = 9 (Damien)
Change-Id: Ibed2fb71b233a369e69278bc96298df82d032a47
Signed-off-by: Akash Goel akash.g...@intel.com
Signed-off-by: Damien Lespiau
On Thu, Jan 15, 2015 at 02:55:26PM +0200, Ander Conselvan de Oliveira wrote:
The previous patch changed the config field in intel_crtc to a pointer,
but to keep the mechanical changes (done with spatch) separate from the
new code, the pointer was made to point to a new _config field with type
The I915_EXEC_NO_RELOC flag lets us tell the kernel that the offset we
provide in the validate list entry is what we've used in all relocations
to the bo in question. If the bo hasn't moved, the kernel can skip
relocations completely.
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
---
In userspace we can track which buffer a relocation refers to in
constant time. However, the kernel has to look up the per-fd gem
handle for each relocation. Using the I915_EXEC_HANDLE_LUT flag lets
us use the the bos validation list index instead of the gem handle in
the relocation entries.
On Thu, Jan 15, 2015 at 09:13:02AM +0200, Jani Nikula wrote:
On Wed, 14 Jan 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
The core fix was applied in
commit a63b03e2d2477586440741677ecac45bcf28d7b1
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Tue Jan 6 10:29:35 2015 +
On Thu, Jan 15, 2015 at 08:44:00PM +, Chris Wilson wrote:
On Thu, Jan 15, 2015 at 08:36:15PM +0100, Daniel Vetter wrote:
On Wed, Jan 14, 2015 at 9:34 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This (partially) reverts
commit 5537252b6b6d71fb1a8ed7395a8e5babf91953fd
On Thu, Jan 15, 2015 at 01:25:02PM +0200, Jani Nikula wrote:
On Wed, 14 Jan 2015, Singh, Gaurav K gaurav.k.si...@intel.com wrote:
On 12/12/2014 1:03 PM, Singh, Gaurav K wrote:
On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
For CHT changes are required for calculating the correct m,n p with
On Fri, Jan 16, 2015 at 02:07:26PM +0530, Sonika Jindal wrote:
Mainly taking care of some register offsets, otherwise things are similar to
hsw. Also, programming ddi aux to use hardcoded values for psr data select.
v2: introduce EDP_PSR_AUX_BASE macro (Chris)
v3: Moving to HW tracking for
On Fri, Jan 16, 2015 at 05:46:00PM -0800, Kristian Høgsberg wrote:
The I915_EXEC_NO_RELOC flag lets us tell the kernel that the offset we
provide in the validate list entry is what we've used in all relocations
to the bo in question. If the bo hasn't moved, the kernel can skip
relocations
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5594
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 353/353
On Friday 16 January 2015 10:39 PM, Ville Syrjälä wrote:
On Fri, Jan 16, 2015 at 08:42:18PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read
From: Deepak S deepa...@linux.intel.com
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.
v2: reuse mask definitions INTEL_INFO() to get device info
58 matches
Mail list logo
