2015-02-11 6:30 GMT-02:00 Daniel Vetter dan...@ffwll.ch:
On Mon, Feb 09, 2015 at 07:41:17PM +0100, Daniel Vetter wrote:
On Mon, Feb 09, 2015 at 02:46:31PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We need this for FBC, and possibly for PSR too.
Reviewed-by:
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV have similar DSPARB registers as older platforms, just more of
them due to more planes. Add a bit of code to read out the current FIFO
split from the registers. Will be useful later when we improve the WM
calculations.
v2: Add
On Wed, Feb 11, 2015 at 04:59:48PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
For some reason link training fails when port B is being driven by pipe
A, and was previously driven by port B or the common lane was previously
powered off.
From: Rafael Barbalho rafael.barba...@intel.com
With full PPGTT enabled an object's VMA entry into a PPGTT VM needs to be
cleaned up so that the PPGTT PDE PTE allocations can be freed.
This problem only shows up with full PPGTT because an object's VMA is
only cleaned-up when the object is
From: Rafael Barbalho rafael.barba...@intel.com
This particular memory leak, if I can call it that, shows itself when i915
is in true PPGTT mode and you share a buffer object to another hardware
context using flink.
In the failure case harware context A creates an object does some rendering
to
From: Rafael Barbalho rafael.barba...@intel.com
It's possible to gather up basic information on all active VMs.
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Cc: Daniel Vetter dan...@ffwll.ch
Cc: Jon Bloomfield jon.bloomfi...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 41
On Thu, Feb 12, 2015 at 10:26:02AM +0200, Mika Kuoppala wrote:
We use the pid of the process which opened our device when
we track which was the culprit of the gpu hang. But as that
file descriptor might get inherited, we might blame the
wrong process when we record the error state.
Track
On Thu, Feb 12, 2015 at 10:43:44AM +0100, Daniel Vetter wrote:
On Thu, Feb 12, 2015 at 07:53:18AM +, Chris Wilson wrote:
When we walk the list of vma, or even for protecting against concurrent
framebuffer creation, we must hold the struct_mutex or else a second
thread can corrupt the
We use the pid of the process which opened our device when
we track which was the culprit of the gpu hang. But as that
file descriptor might get inherited, we might blame the
wrong process when we record the error state.
Track process identifiers in requests to always find
the correct offender.
On Thu, Feb 12, 2015 at 07:53:18AM +, Chris Wilson wrote:
When we walk the list of vma, or even for protecting against concurrent
framebuffer creation, we must hold the struct_mutex or else a second
thread can corrupt the list as we walk it.
Fixes regression from
commit
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
UMS is no more!
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 36 +++-
1 file changed, 11 insertions(+), 25
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
At driver load we need to tell the vblank code about the state of the
pipes, so that the logic around reject vblank_get when the pipe is off
works correctly.
Thus far i915 used drm_vblank_off, but one of the side-effects of it
is that
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
Where possible right now. Just a small step towards nirvana ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 9 +
On Thu, Feb 12, 2015 at 08:05:02PM +, rafael.barba...@intel.com wrote:
From: Rafael Barbalho rafael.barba...@intel.com
With full PPGTT enabled an object's VMA entry into a PPGTT VM needs to be
cleaned up so that the PPGTT PDE PTE allocations can be freed.
This problem only shows up
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
With Ville's rework to use drm_crtc_vblank_on/off the core will take
care of rejecting drm_vblank_get calls when the pipe is off. Also the
core won't call the get_vblank_counter hooks in that case either. And
since we've dropped ums
Human readable name for each output type to correspond with names
used in the ACPI property tables.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 57
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed,
This adds an init-time configuration framework that parses configuration
data from an ACPI property table. The table is assumed to have well
defined sub-device property tables that correspond to the various
driver components. Initially the following sub-device tables are
defined:
CRTC (CRTC)
Add VBT device sections with sample data to test the VBT parsing.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/i915-properties.asl | 140 +++
drivers/gpu/drm/i915/i915-properties.hex | 622 +++
2 files changed, 533 insertions(+), 229
Set the initial value of the force audio and broadcast rgb properties
using property values found in the init-time configuration.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/intel_modes.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
Modify the table loading function to accept an included property table
as a last resort. This can be used to create test cases. It may
also be used to provide a static, compiled in configuration.
A sample test table (source and compiled HEX version) are included in
this commit.
Signed-off-by:
If there are ACPI table based workarounds for a platform, use those
instead of the built-in driver list when doing the workaround init.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 19 +++
1 file changed, 11 insertions(+), 8
Use the init-time configuration setting for scaling_mode to set the
initial value of the scaling_mode connector property.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
Add the various workarounds as properties in the ACPI table. How these
get processed and used is still TBD.
Added broadwell and cherrytrail workarounds as examples.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/i915-properties.asl | 50 +
Add ability to parse a list of workarounds from the ACPI table.
Initially, this expects all workarounds listed to be valid and
they replace the hard coded list initialized in init_workarounds_ring().
The main benefit of this is the ability to add/remove workarounds
at runtime. It may also be
We'll reduce some duplicate code if we move the list node allocation
to its own function when we start processing future config items like
workaround or vbt information.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/intel_config.c | 49
Allow the init-time configuration to specify the bits per color value
that gets used if bits per color is not present in EDID data (or if EDID
is not present).
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 14 ++
1 file changed, 14
Background:
This capability is targeted at deeply embedded appliance like devices
that make use of Intel integrated graphics. There are a few use cases
that are not currently supported by the i915 driver. For example,
they may not be running userspace code that is capable of querying and
Add a new section with subsections to the ACPI configuration table
that mimics much of the information typically stored in the VBT/option
ROM. This allows for a way to override incorrect VBT data or to provide
the configuration if VBT is not present. Lack of VBT is common in
embedded systems.
No, we had solved old frontbuffer false positives... some missing
flush somewhere at that time...
So, I added a bunch of printk and I insist that it is conceptually
wrong to set intel_crtc_atomic_commit on check times when you do
memset(intel_crtc-atomic, 0, sizeof(intel_crtc-atomic));
on every
On Thu, Feb 12, 2015 at 08:51:20AM +, Chris Wilson wrote:
On Thu, Feb 12, 2015 at 10:26:02AM +0200, Mika Kuoppala wrote:
We use the pid of the process which opened our device when
we track which was the culprit of the gpu hang. But as that
file descriptor might get inherited, we might
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5762
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 282/282
On Fri, Feb 13, 2015 at 12:57:12AM +0200, Imre Deak wrote:
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
Where possible right now. Just a small step towards nirvana ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
On Fri, Feb 13, 2015 at 12:37:27AM +0200, Imre Deak wrote:
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
With Ville's rework to use drm_crtc_vblank_on/off the core will take
care of rejecting drm_vblank_get calls when the pipe is off. Also the
core won't call the
On Thu, Feb 12, 2015 at 11:56:50PM +0200, Imre Deak wrote:
On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
At driver load we need to tell the vblank code about the state of the
pipes, so that the logic around reject vblank_get when the pipe is off
works correctly.
Thus far i915
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5763
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 1/30/2015 4:39 PM, Ville Syrjälä wrote:
On Fri, Jan 30, 2015 at 12:01:53AM +0530, Vijay Purushothaman wrote:
This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both
On 11/02/2015 18:21, Lespiau, Damien wrote:
I have no idea how that crept in, but we need to do the write from the
ring and this is a masked register. Two fixes in 1!
Cc: Nick Hoath nicholas.ho...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Reviewed-by: Nick Hoath
On Wed, 11 Feb 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Feb 09, 2015 at 07:41:17PM +0100, Daniel Vetter wrote:
On Mon, Feb 09, 2015 at 02:46:31PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We need this for FBC, and possibly for PSR too.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88652
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
On 2/10/2015 6:13 PM, Jani Nikula wrote:
On Thu, 29 Jan 2015, Vijay Purushothaman
vijay.a.purushotha...@linux.intel.com wrote:
This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity
On 11/02/2015 18:21, Lespiau, Damien wrote:
It's always a good idea to keep static analysis happy (also because it
prompts doing the check like I proposed :), this time smatch complains:
drivers/gpu/drm/i915/intel_ringbuffer.c:891 gen9_init_workarounds() warn:
always true condition
On 09/02/2015 19:33, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Reviewed-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_ringbuffer.c | 8
2 files changed, 12 insertions(+)
On 09/02/2015 19:33, Damien Lespiau wrote:
This W/A is put in a gen9 specific function because it may well be
needed on other gen9 platforms.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Reviewed-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5761
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
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