From: Akash Goel
For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
platforms and the time values are expressed in units of 1.33 us,
compared to 1.28 us for ea
From: Akash Goel
On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual
On Thu, 26 Feb 2015, sonika wrote:
> On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
>> Signed-off-by: Jani Nikula
>> ---
>> include/drm/drm_dp_helper.h | 37 +
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/i
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5821
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3 281/281
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 37 +
1 file changed, 37 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index cc96024e8776..07d94
On Thu, Feb 26, 2015 at 10:05:14AM +, Chris Wilson wrote:
> I woke up one morning and found 50k objects sitting in the batch pool
> and every search seemed to iterate the entire list... Painting the
> screen in oils would provide a more fluid display.
Fwiw, I've figured out the culprit here. m
From: Tvrtko Ursulin
So no need to have code which never gets called in the driver.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 24
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
From: Tvrtko Ursulin
Commit 1da30627fc511a57c9bd23a02c97f0576379f761 "drm: Add rotation value to
plane state" moved the rotation property to DRM core but only did the set
property part. This does the get property part as well.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
---
drivers/gpu/drm/d
The patch "drm/i915: Plumb drm_device through page tables operations"
added an extra parameter, but it didn't update the function description.
Also remove unnecessary blank line added by the same patch.
Found by kbuild test robot.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_
On Thu, Feb 26, 2015 at 11:26:10AM +0200, Mika Kahola wrote:
> In a case when DP link has been once trained we can reuse
> the existing link training parameters i.e. voltage swing
> and pre-emphasis levels from cache when there is a need to
> restart link training. In a case of eDP we initially try
On Thu, Feb 26, 2015 at 04:09:47PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> are stored, initially by the Driver, inside the dev_priv->rps structure.
> Since these values are expected to remain same throughout
From: Akash Goel
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain de
Combining list_del() with the list_for_each() is actually safe.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 41 +-
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
b/drivers/gp
Now with the trimmed memcpy before the command parser, we try to
allocate many different sizes of batches, predominantly one or two
pages. We can therefore speed up searching for a good sized batch by
keeping the objects of buckets of roughly the same size.
Signed-off-by: Chris Wilson
---
driver
In the next patch, I want to use the structure elsewhere and so require
it defined earlier. Rather than move the definition to an earlier location
where it feels very odd, place it in its own header file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h| 13 +
I woke up one morning and found 50k objects sitting in the batch pool
and every search seemed to iterate the entire list... Painting the
screen in oils would provide a more fluid display.
One issue with the current design is that we only check for retirements
on the current ring when preparing to
Since we use obj->active as a hint in many places throughout the code,
knowing its state in debugfs is extremely useful.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
At runtime, this helps ensure that the batch pools are kept trim and
fast. Then at suspend, this releases memory that we do not need to
restore. It also ties into the oom-notifier to ensure that we recover as
much kernel memory as possible during OOM.
Signed-off-by: Chris Wilson
---
drivers/gpu/
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 95 ++---
1 file changed, 90 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
i
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Keep the DPCD macros ordered by address, and make indentation conform to
the rest of the file.
commit e045d20bef41707dbba676e58624b54f9f39e172
Author: Sonika Jindal
Date: Thu Feb 19 13:16:44 2015 +0530
drm: Adding edp1.4 specif
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Mostly display control related DPCD addresses.
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 32
1 file changed, 32 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/dr
Imre Deak writes:
>> That patch fixes the problem, with only pci_set_power_state commented
>> out. Do you still want me to try with pci_disable_device() commented
>> out as well?
>
> No, but it would help if you could still try the two attached patch
> separately, without any of the previous wor
In a case when DP link has been once trained we can reuse
the existing link training parameters i.e. voltage swing
and pre-emphasis levels from cache when there is a need to
restart link training. In a case of eDP we initially try
to train the link by using the parameter set that we can find
from V
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5820
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
On Wed, Feb 25, 2015 at 12:46:31PM -0800, Jesse Barnes wrote:
> On 01/28/2015 02:07 AM, Chris Wilson wrote:
> > On Wed, Jan 28, 2015 at 10:50:18AM +0100, Daniel Vetter wrote:
> >> On Wed, Jan 28, 2015 at 09:23:46AM +, Chris Wilson wrote:
> >>> On Wed, Jan 28, 2015 at 10:22:15AM +0100, Daniel Ve
Hi Dave -
First batch of fixes for v4.0-rc, plenty of cc: stable material.
BR,
Jani.
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel tags
On Thu, 26 Feb 2015, Michael Leuchtenburg wrote:
> Okay, here's the results:
> : 12 0a 02 41 00 00 00 00 00 00 00 00 00 0b 00
> 0070: 01 00
> 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0100: 0a 02 00 09 09 00 00 00 01 00 00
> 0200: 01 00 77 00 01 01 55 00
> 0600: 01
> 0700: 02
> 0
On Thu, 2015-02-26 at 08:04 +, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 01:29:09PM +0530, akash.g...@intel.com wrote:
> > From: Akash Goel
> >
> > The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> > are stored, initially by the Driver, inside the dev_priv->rps struc
On Thu, Feb 26, 2015 at 01:29:09PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> are stored, initially by the Driver, inside the dev_priv->rps structure.
> Since these values are expected to remain same throughout
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