[Intel-gfx] [PATCH] checkpatch: spell check reudce

References: http://mid.gmane.org/1424977312-24902-1-git-send-email-ville.syrj...@linux.intel.com Signed-off-by: Jani Nikula --- scripts/spelling.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/spelling.txt b/scripts/spelling.txt index fc7fd52b5e03..bb8e4d0a1911 100644 --- a/scrip

Re: [Intel-gfx] [Beignet] Preventing zero GPU virtual address allocation

On Fri, Mar 06, 2015 at 02:11:18AM +, Zou, Nanhai wrote: > I don't understand why we need a complex solution when there is already a > simple solution with patch. > What is the drawback of reserving page 0? > Before we going to that complex solution, could we just reserve page zero? > It is si

Re: [Intel-gfx] [PATCH] drm/i915: Make WAIT_IOCTL negative timeouts be indefinite again

On Thu, Mar 05, 2015 at 01:27:43PM +0100, Daniel Vetter wrote: > On Wed, Mar 04, 2015 at 06:09:26PM +, Chris Wilson wrote: > > This fixes a regression from > > > > commit 5ed0bdf21a85d78e04f89f15ccf227562177cbd9 > > Author: Thomas Gleixner > > Date: Wed Jul 16 21:05:06 2014 + > > > >

[Intel-gfx] [PATCH] core: Make the start of the debug output more clear

I missing the quiet "Log start" between the test failure and the debug output (and so was very confused by the repetition). You have to shout at me! Signed-off-by: Chris Wilson Cc: Thomas Wood --- lib/igt_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/igt_core.c

[Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer

Userspace can pass in an offset that it presumes the object is located at. The kernel will then do its utmost to fit the object into that location. The assumption is that userspace is handling its own object locations (for example along with full-ppgtt) and that the kernel will rarely have to make

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't assume primary & cursor are always on for wm calculation (v2)

On 03/06/2015 01:31 AM, Matt Roper wrote: Current ILK-style watermark code assumes the primary plane and cursor plane are always enabled. This assumption, along with the combination of two independent commits that got merged at the same time, results in a NULL dereference. The offending commit

Re: [Intel-gfx] [PATCH 05/51] drm/i915: Add return code check to i915_gem_execbuffer_retire_commands()

On 05/03/2015 16:14, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 03:06:42PM +, John Harrison wrote: On 05/03/2015 14:44, Daniel Vetter wrote: Imo reserving a bit of ring space for each add_request should be solid. Userspace uses the exact same reservation logic for adding end-of-batch work

Re: [Intel-gfx] [PATCH] checkpatch: spell check reudce

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5903 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -2 275/275

Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement

On Thu, Mar 05, 2015 at 12:05:38PM -0500, Brian J. Murrell wrote: > On Thu, 2015-03-05 at 14:06 +, Chris Wilson wrote: > > > > Probably unrelated. Look in dmesg > > dmesg is pretty muddy right now as I still have drm.debug=6 set. > > > and /sys/class/drm/card0/error > > http://brian.interli

Re: [Intel-gfx] [PATCH 03/53] drm/i915: Cache ringbuf pointer in request structure

On 05/03/2015 13:56, Tomas Elf wrote: On 19/02/2015 17:17, john.c.harri...@intel.com wrote: From: John Harrison In execlist mode, the ringbuf is a function of the ring and context whereas in legacy mode, it is derived from the ring alone. Thus the calculation required to determine the ringbu

Re: [Intel-gfx] [PATCH 01/53] drm/i915: Rename 'flags' to 'dispatch_flags' for better code reading

On 05/03/2015 13:21, Tomas Elf wrote: On 19/02/2015 17:17, john.c.harri...@intel.com wrote: From: John Harrison There is a flags word that is passed through the execbuffer code path all the way from initial decoding of the user parameters down to the very final dispatch buffer call. It is si

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't assume primary & cursor are always on for wm calculation (v2)

On Thu, Mar 05, 2015 at 05:31:18PM -0800, Matt Roper wrote: > Current ILK-style watermark code assumes the primary plane and cursor > plane are always enabled. This assumption, along with the combination > of two independent commits that got merged at the same time, results in > a NULL dereference

Re: [Intel-gfx] [PATCH v3] drm/i915: Disable the mmio.debug WARN after it fires

On Fri, Dec 26, 2014 at 05:02:30PM -0200, Paulo Zanoni wrote: > 2014-12-18 10:47 GMT-02:00 Chris Wilson : > > On Thu, Dec 18, 2014 at 02:36:54PM +0200, Jani Nikula wrote: > >> On Thu, 18 Dec 2014, Chris Wilson wrote: > >> > If we have a single unclaimed register, we will have lots. A WARN for > >>

Re: [Intel-gfx] [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h

On 05/03/15 16:20, Damien Lespiau wrote: > A couple of things I wanted to do for the longest time: > > - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the > file when updating > - Start a new object, struct drm_intel_device where we could put common code > ac

Re: [Intel-gfx] [PATCH 7/7] drm/i915/skl: Take 90/270 rotation into account in watermark calculations

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5896 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 275/275

[Intel-gfx] [QA 2015/03/06 ww10] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: Skylake, Braswell, Broadwell, Haswell, Baytrail, Sandybridge. In this circle, 10 new bugs have been found (89055, 89073 , 89074

Re: [Intel-gfx] [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h

On Fri, Mar 06, 2015 at 02:10:44PM +, Emil Velikov wrote: > On 05/03/15 16:20, Damien Lespiau wrote: > > A couple of things I wanted to do for the longest time: > > > > - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy > > the > > file when updating > > - Star

[Intel-gfx] [PATCH 1/7] drm/i915: Relax RPS contraints to allows setting minfreq on idle

When we idle, we set the GPU frequency to the hardware minimum (not user minimum). We introduce a new variable to distinguish between the different roles, and to allow easy tuning of the idle frequency without impacting over aspects of RPS. Setting the minimum frequency should be a safety blanket a

[Intel-gfx] [PATCH 4/7] drm/i915: Use down ei for manual Baytrail RPS calculations

Use both up/down manual ei calcuations for symmetry and greater flexibility for reclocking, instead of faking the down interrupt based on a fixed integer number of up interrupts. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/i915_irq.c | 15 ++-

[Intel-gfx] [PATCH 3/7] drm/i915: Improved w/a for rps on Baytrail

Rewrite commit 31685c258e0b0ad6aa486c5ec001382cf8a64212 Author: Deepak S Date: Thu Jul 3 17:33:01 2014 -0400 drm/i915/vlv: WA for Turbo and RC6 to work together. Other than code clarity, the major improvement is to disable the extra interrupts generated when idle. However, the reclocking

[Intel-gfx] [PATCH 5/7] drm/i915: Agressive downclocking on Baytrail

Reuse the same reclocking strategy for Baytail as on its bigger brethren, Sandybridge and Ivybridge. In particular, this makes the device quicker to reclock (both up and down) though the tendency now is to downclock more aggressively to compensate for the RPS boosts. Signed-off-by: Chris Wilson C

[Intel-gfx] [PATCH 6/7] drm/i915: Boost GPU frequency if we detect outstanding pageflips

If we hit a vblank and see that have a pageflip queue but not yet processed, ensure that the GPU is running at maximum in order to clear the backlog. Pageflips are only queued for the following vblank, if we miss it, there will be a visible stutter. Boosting the GPU frequency doesn't prevent us fro

[Intel-gfx] [PATCH 7/7] drm/i915: Deminish contribution of wait-boosting from clients

With boosting for missed pageflips, we have a much stronger indication of when we need to (temporarily) boost GPU frequency to ensure smooth delivery of frames. So now only allow each client to perform one RPS boost in each period of GPU activity due to stalling on results. Signed-off-by: Chris Wi

[Intel-gfx] [PATCH 2/7] drm/i915: Fix computation of last_adjustment for RPS autotuning

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_irq.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9baecb79de8c..1296ce37e435 100644 --- a/drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH] drm/i915: use in_interrupt() not in_irq() to check context

The kernel in_irq() function tests for hard-IRQ context only, so if a system is run with the kernel 'threadirqs' option selected, the test in intel_check_page_flip() generates lots of warnings, because then it gets called in soft-IRQ context. We can instead use in_interrupt() which allows for eith

Re: [Intel-gfx] [PATCH 05/51] drm/i915: Add return code check to i915_gem_execbuffer_retire_commands()

On Fri, Mar 06, 2015 at 11:38:44AM +, John Harrison wrote: > On 05/03/2015 16:14, Daniel Vetter wrote: > >On Thu, Mar 05, 2015 at 03:06:42PM +, John Harrison wrote: > >>On 05/03/2015 14:44, Daniel Vetter wrote: > >>>Imo reserving a bit of ring space for each add_request should be solid. > >

Re: [Intel-gfx] [PATCH 05/53] drm/i915: Add return code check to i915_gem_execbuffer_retire_commands()

On Thu, Mar 05, 2015 at 02:45:11PM +, Tomas Elf wrote: > On 19/02/2015 17:17, john.c.harri...@intel.com wrote: > >From: John Harrison > > > >For some reason, the i915_add_request() call in > >i915_gem_execbuffer_retire_commands() was explicitly having its return code > >ignored. The _retire_co

Re: [Intel-gfx] [PATCH 08/53] drm/i915: Update alloc_request to return the allocated request

On Thu, Mar 05, 2015 at 08:13:07PM +, Tomas Elf wrote: > On 05/03/2015 15:46, John Harrison wrote: > >On 05/03/2015 15:27, Tomas Elf wrote: > >>On 19/02/2015 17:17, john.c.harri...@intel.com wrote: > >>>From: John Harrison > >>> > >>>The alloc_request() function does not actually return the ne

Re: [Intel-gfx] [PATCH 1/2] gpio/crystalcove: Export Panel and backlight en/disable signals as GPIO

On Fri, 2015-03-06 at 12:04 +0100, Linus Walleij wrote: > On Wed, Feb 18, 2015 at 1:18 PM, Shobhit Kumar > wrote: > > > Export Panel BACKLIGHT_EN(offset 0x51) and PANEL_EN(offset 0x52) as two > > additional GPIOs. Needed by display driver to enable the DSI panel on > > BYT platform where the Pan

Re: [Intel-gfx] [PATCH 28/53] drm/i915: Update queue_flip() to do explicit request management

On Thu, Mar 05, 2015 at 07:29:27PM +, Tomas Elf wrote: > On 19/02/2015 17:17, john.c.harri...@intel.com wrote: > >From: John Harrison > > > >Updated the display page flip code to do explicit request creation and > >submission rather than relying on the OLR and just hoping that the request > >a

Re: [Intel-gfx] [PATCH 01/53] drm/i915: Remove ironlake rc6 support

On Thu, Mar 05, 2015 at 03:36:03PM +, John Harrison wrote: > On 05/03/2015 15:22, Daniel Vetter wrote: > >On Thu, Mar 05, 2015 at 02:03:03PM +, john.c.harri...@intel.com wrote: > >>From: John Harrison > >> > >>Apparently, this has never worked reliably and is currently disabled. Also, > >

Re: [Intel-gfx] [PATCH] drm/i915: Update intel_dp_hpd_pulse() to check link status for non-MST operation

On Thu, Mar 05, 2015 at 11:22:19AM -0700, Todd Previte wrote: > Update the hot plug function to handle the SST case. Instead of placing > the SST case within the long/short pulse block, it is now handled after > determining that MST mode is not in use. This way, the topology management > layer can

Re: [Intel-gfx] [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads.

On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote: > From: Deepak S > > In normal cases, RC6 promotion timer is 1700us/500us. This will > result in more time spent in C1 state. For more residency in > C6 in case of media workloads, this is changed to 250us. > Not doing this

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't require primary->fb in intel_crtc_active()

On Thu, Mar 05, 2015 at 03:07:52PM +, Tvrtko Ursulin wrote: > > On 03/04/2015 05:42 PM, Matt Roper wrote: > >On Wed, Mar 04, 2015 at 05:26:36PM +, Tvrtko Ursulin wrote: > >> > >>On 03/04/2015 02:15 AM, Matt Roper wrote: > >>>Universal planes allow us to have an active CRTC without a primar

Re: [Intel-gfx] [PATCH] drm/i915: use in_interrupt() not in_irq() to check context

On Fri, Mar 06, 2015 at 03:34:26PM +, Dave Gordon wrote: > The kernel in_irq() function tests for hard-IRQ context only, so if a > system is run with the kernel 'threadirqs' option selected, the test in > intel_check_page_flip() generates lots of warnings, because then it gets > called in soft-

Re: [Intel-gfx] [PATCH] drm/i915: Make WAIT_IOCTL negative timeouts be indefinite again

On Fri, Mar 06, 2015 at 08:54:35AM +, Chris Wilson wrote: > On Thu, Mar 05, 2015 at 01:27:43PM +0100, Daniel Vetter wrote: > > On Wed, Mar 04, 2015 at 06:09:26PM +, Chris Wilson wrote: > > > This fixes a regression from > > > > > > commit 5ed0bdf21a85d78e04f89f15ccf227562177cbd9 > > > Auth

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane: Ensure planes recover from DPMS

On Thu, Mar 05, 2015 at 07:01:09AM -0800, Matt Roper wrote: > On Thu, Mar 05, 2015 at 01:32:19PM +0100, Daniel Vetter wrote: > > On Wed, Mar 04, 2015 at 10:50:53AM -0800, Matt Roper wrote: > > > i915 was using the main atomic 'disable plane' to turn off sprite planes > > > during a CRTC disable. T

Re: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Support for 90/270 rotation

On Thu, Mar 05, 2015 at 05:56:23PM +0200, Ville Syrjälä wrote: > On Thu, Mar 05, 2015 at 04:29:30PM +0100, Daniel Vetter wrote: > > On Thu, Mar 05, 2015 at 03:08:17PM +0200, Ville Syrjälä wrote: > > > On Thu, Mar 05, 2015 at 01:56:53PM +0100, Daniel Vetter wrote: > > > > On Thu, Mar 05, 2015 at 02:

Re: [Intel-gfx] [PATCH i-g-t] igt.cocci: Replace igt_assert() with igt_assert_CMP() where possible

On Thu, Mar 05, 2015 at 03:01:00PM -0800, Matt Roper wrote: > The integer comparison macros give us better error output by including > the actual values that failed the comparison. > > Signed-off-by: Matt Roper Oh nice, the power of cocci. Applied, thanks -Daniel > --- > lib/igt.cocci

Re: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Support for 90/270 rotation

On Fri, Mar 06, 2015 at 06:03:31PM +0100, Daniel Vetter wrote: > On Thu, Mar 05, 2015 at 05:56:23PM +0200, Ville Syrjälä wrote: > > On Thu, Mar 05, 2015 at 04:29:30PM +0100, Daniel Vetter wrote: > > > On Thu, Mar 05, 2015 at 03:08:17PM +0200, Ville Syrjälä wrote: > > > > On Thu, Mar 05, 2015 at 01:

Re: [Intel-gfx] [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled on VLV/CHV

On Thu, Mar 05, 2015 at 09:19:48PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Poke at the CBR1_VLV register during init_clock_gating to make sure the > PND deadline scheme is used. > > The hardware has two modes of operation wrt. watermarks: > > 1) PND deadline mode:

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Fix computation of last_adjustment for RPS autotuning

On Fri, Mar 06, 2015 at 03:06:26PM +, Chris Wilson wrote: > Signed-off-by: Chris Wilson I might have impending w/e syndrome, but I can't see what you're fixing any more. Can you please augment the commit message a bit? Thanks, Daniel > --- > drivers/gpu/drm/i915/i915_irq.c | 27 +++

Re: [Intel-gfx] [PATCH 12/12] drm/i915: Disable DDR DVFS on CHV

On 03/05/2015 11:19 AM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > DDR DVFS introduces massive memory latencies which can't be handled by > the PND deadline stuff. Instead the watermarks will need to be > programmed to compensate for the latency and the deadlines will need to

Re: [Intel-gfx] [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code

On 03/05/2015 11:19 AM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Assuming the PND deadline mechanism works reasonably we should do > memory requests as early as possible so that PND has schedule the > requests more intelligently. Currently we're still calculating > the water

Re: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Support for 90/270 rotation

On Fri, Mar 06, 2015 at 07:22:46PM +0200, Ville Syrjälä wrote: > On Fri, Mar 06, 2015 at 06:03:31PM +0100, Daniel Vetter wrote: > > On Thu, Mar 05, 2015 at 05:56:23PM +0200, Ville Syrjälä wrote: > > > On Thu, Mar 05, 2015 at 04:29:30PM +0100, Daniel Vetter wrote: > > > > On Thu, Mar 05, 2015 at 03:

Re: [Intel-gfx] [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code

On Fri, Mar 06, 2015 at 09:31:20AM -0800, Jesse Barnes wrote: > I wonder if we should be warning if the wm values we end up with exceed > the mask size (the fact that you write them with a shift and mask made > me think of it), but that could be a follow on, or even put into the > calc code instead

Re: [Intel-gfx] [PATCH 08/53] drm/i915: Update alloc_request to return the allocated request

On 06/03/2015 16:18, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 08:13:07PM +, Tomas Elf wrote: On 05/03/2015 15:46, John Harrison wrote: On 05/03/2015 15:27, Tomas Elf wrote: On 19/02/2015 17:17, john.c.harri...@intel.com wrote: From: John Harrison The alloc_request() function does no

[Intel-gfx] [PULL] drm-intel-next

Hi Dave, drm-intel-next-2015-02-27: - Y tiling support for scanout from Tvrtko&Damien - Remove more UMS support - some small prep patches for OLR removal from John Harrison - first few patches for dynamic pagetable allocation from Ben Widawsky, rebased by tons of other people - DRRS support patc

Re: [Intel-gfx] [PATCH 05/51] drm/i915: Add return code check to i915_gem_execbuffer_retire_commands()

On 06/03/15 15:57, Daniel Vetter wrote: > On Fri, Mar 06, 2015 at 11:38:44AM +, John Harrison wrote: >> On 05/03/2015 16:14, Daniel Vetter wrote: >>> On Thu, Mar 05, 2015 at 03:06:42PM +, John Harrison wrote: On 05/03/2015 14:44, Daniel Vetter wrote: > Imo reserving a bit of ring s

[Intel-gfx] [PATCH] Revert "intel: Fix documentation for drm_intel_gem_bo_wait()"

This reverts commit 080b4929b7452dc1fea32ac1d32e7e571e7fb38b. Chris noticed that "negative values wait forever" is indeed intended behaviour and the issue is just that we didn't have a testcase (fixed now) and that a regression slipped through (fixed and on track for all stable kernels). So lets

[Intel-gfx] [PATCH] Revert "intel: Fix documentation for drm_intel_gem_bo_wait()"

This reverts commit 080b4929b7452dc1fea32ac1d32e7e571e7fb38b. Chris noticed that "negative values wait forever" is indeed intended behaviour and the issue is just that we didn't have a testcase (fixed now) and that a regression slipped through (fixed and on track for all stable kernels). So lets

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Deminish contribution of wait-boosting from clients

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5906 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -6 275/275

Re: [Intel-gfx] [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code

On Fri, Mar 06, 2015 at 09:31:20AM -0800, Jesse Barnes wrote: > On 03/05/2015 11:19 AM, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Assuming the PND deadline mechanism works reasonably we should do > > memory requests as early as possible so that PND has schedule the > >

Re: [Intel-gfx] [PATCH] Revert "intel: Fix documentation for drm_intel_gem_bo_wait()"

On 06/03/15 17:58, Daniel Vetter wrote: > This reverts commit 080b4929b7452dc1fea32ac1d32e7e571e7fb38b. > > Chris noticed that "negative values wait forever" is indeed intended > behaviour and the issue is just that we didn't have a testcase (fixed > now) and that a regression slipped through (fix

Re: [Intel-gfx] [Beignet] [PATCH] drm/i915: Export total subslice and EU counts

On Thu, Mar 05, 2015 at 12:35:55PM +0800, Zhigang Gong wrote: > There is one minor conflict when apply the KMD patch to latest > drm-intel-nightly branch. It should be easy to fix. > > Another issue is that IMO, we should bump libdrm's version number > when increase these new APIs. Then in Beignet

[Intel-gfx] [PATCH 0/6] SKL post-enable power well hook (v2)

Here's a new spin of the series, restoring interrupt registers and DDI translation tables when re-enabling power-wells. v2: - Don't run the post-enable hook when the power well is already enabled - Put the DDI patch with the rest of the serise -- Damien Damien Lespiau (6): drm/i915/skl:

[Intel-gfx] [PATCH 4/6] drm/i915/skl: Restore pipe interrupt registers after power well enabling

The pipe interrupt registers are in the actual pipe power well, so we need to restore them when re-enable the corresponding power well. I've also copied what we do on HSW/BDW for VGA, even if the we haven't enabled unclaimed registers just yet. v2: Don't run skl_power_well_post_enable() if the po

[Intel-gfx] [PATCH 2/6] drm/i915/skl: Introduce enable_requested and is_enabled in the power well code

Just like what we do for HSW/BDW, having those variables makes it a bit easier to parse the code. Suggested-by: Paulo Zanoni Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 3/6] drm/i915/skl: Mirror what we do on HSW for the power well enable log message

Just to be more consistent with what we do on HSW. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8f34d38..46ffb

[Intel-gfx] [PATCH 5/6] drm/i915: Remove unused condition in hsw_power_well_post_enable()

We don't use this function on gen9, no need for that test here. Reviewed-by: Paulo Zanoni Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1

I was dumping the DDI translation tables to make sure my patch updating the HDMI entry was doing the right thing when I noticed that the table was showing reset values after DPMS. And indeed, the DDI translation registers are in power well 1 on SKL, and so we're losing their values when shutting d

[Intel-gfx] [PATCH 1/6] drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

While we only need to restore pipe B/C interrupt registers on BDW when enabling the power well, skylake a bit more flexible and we'll also need to restore the pipe A registers as it has its own power well that can be toggled. Reviewed-by: Paulo Zanoni Signed-off-by: Damien Lespiau --- drivers/g

Re: [Intel-gfx] [Beignet] [PATCH] drm/i915: Export total subslice and EU counts

On Thu, Mar 05, 2015 at 12:35:55PM +0800, Zhigang Gong wrote: > There is one minor conflict when apply the KMD patch to latest > drm-intel-nightly branch. It should be easy to fix. > > Another issue is that IMO, we should bump libdrm's version number > when increase these new APIs. Then in Beignet

Re: [Intel-gfx] [PATCH 0/6] SKL post-enable power well hook (v2)

2015-03-06 15:50 GMT-03:00 Damien Lespiau : > Here's a new spin of the series, restoring interrupt registers and DDI > translation tables when re-enabling power-wells. > > v2: > - Don't run the post-enable hook when the power well is already enabled > - Put the DDI patch with the rest of the se

Re: [Intel-gfx] [PATCH 11/11] drm/i915/skl: Enable the RPS interrupts programming

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5902 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 280/280

Re: [Intel-gfx] [PATCH 08/53] drm/i915: Update alloc_request to return the allocated request

On 06/03/2015 17:36, John Harrison wrote: On 06/03/2015 16:18, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 08:13:07PM +, Tomas Elf wrote: On 05/03/2015 15:46, John Harrison wrote: On 05/03/2015 15:27, Tomas Elf wrote: On 19/02/2015 17:17, john.c.harri...@intel.com wrote: From: John Harr

Re: [Intel-gfx] [PATCH] drm/i915: use in_interrupt() not in_irq() to check context

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5907 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4 275/275

Re: [Intel-gfx] [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code

On 03/06/2015 10:14 AM, Ville Syrjälä wrote: > On Fri, Mar 06, 2015 at 09:31:20AM -0800, Jesse Barnes wrote: >> On 03/05/2015 11:19 AM, ville.syrj...@linux.intel.com wrote: >>> From: Ville Syrjälä >> I wonder if we should be warning if the wm values we end up with exceed >> the mask size (the fact

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Fix computation of last_adjustment for RPS autotuning

On Fri, Mar 06, 2015 at 06:32:27PM +0100, Daniel Vetter wrote: > On Fri, Mar 06, 2015 at 03:06:26PM +, Chris Wilson wrote: > > Signed-off-by: Chris Wilson > > I might have impending w/e syndrome, but I can't see what you're fixing > any more. Can you please augment the commit message a bit?

[Intel-gfx] [PATCH] drm/i915/skl: port A fuse straps don't work on early SKL steppings

So try to enumerate eDP unconditionally in those cases. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 597c10b..88

Re: [Intel-gfx] [PATCH] drm/i915/skl: port A fuse straps don't work on early SKL steppings

On Fri, Mar 06, 2015 at 03:53:32PM -0800, Jesse Barnes wrote: > So try to enumerate eDP unconditionally in those cases. > > Signed-off-by: Jesse Barnes That's WaIgnoreDDIAStrap, I assumed it actually worked since my eDP panel was detected... I see it listed without a stepping check but I guess y

Re: [Intel-gfx] [PATCH 0/2] SSEU detection for CHV

On Fri, Feb 27, 2015 at 10:22:30AM -0800, jeff.mc...@intel.com wrote: > From: Jeff McGee > > These two patches add detection of available and enabled > slice/subslice/EU on CHV following the implementation recently > merged for SKL. They have been requested to help CHV users > determine their con

Re: [Intel-gfx] [PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5908 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -13 275/275

Re: [Intel-gfx] [PATCH] drm/i915/skl: port A fuse straps don't work on early SKL steppings

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5909 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 275/275

Re: [Intel-gfx] [PATCH 3/5] drm/i915/chv: Set min freq to efficient

>On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepak.s at >linux.intel.com wrote: >> From: Deepak S > linux.intel.com> >> >> After feedback from the hardware team, now we set the GPU m