Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6083
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 270/270
From: Deepak S
On CHV, since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Deepak S
Adding few of PM fixes and Improvements for CHV/VLV.
Addressed few comments.
Deepak S (5):
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915: Re-adjusting rc6 promotional timer for chv
drm/i915/chv: Set min freq to efficient frequency on chv
drm/i915/chv: Rem
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_drv.c | 6 -
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
v2: Change commit message
v3: set min_freq before id
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
Signed-off-by: Deepak S
Reviewed-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletion
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_r
Hi folks,
this is a patch against drm-intel-nightly that enables an apparently
undocumented feature of the intel VCH DVO chips. Bit 4 of the VR01
register controls an automatic dithering for 18bpp outputs which greatly
improves the visual image quality for 24bpp display buffers.
The bios of
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6085
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 270/270
