Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6125
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6124
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 272/272
Hi, Chandra
Yes, I agree
There is some noise pre-existing bugs, you can ignore it for now. We're
figuring out an way to filter them out
Thanks
--Shuang
> -Original Message-
> From: Konduru, Chandra
> Sent: Friday, April 3, 2015 1:21 AM
> To: He, Shuang; Gao, Ethan
On 02.04.2015 20:34, Chris Wilson wrote:
> On vblank instant-off systems, we can get into a situation where the cost
> of enabling and disabling the vblank IRQ around a drmWaitVblank query
> dominates. However, we know that if the user wants the current vblank
> counter, they are also very likely t
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6123
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 272/272
On Wed, Apr 01, 2015 at 07:59:29PM -0700, Chandra Konduru wrote:
> primary changes in this version are:
> - moved changes to state from commit patch to check path (Matt)
> - squashed few patches into others (Matt)
> - rebased colorkey related patches ontop of recent updates (Daniel)
> - rebased all
On Wed, Apr 01, 2015 at 07:59:48PM -0700, Chandra Konduru wrote:
> This patch enables skylake primary plane display scaling using shared
> scalers atomic desgin.
>
> v2:
> -use single copy of scaler limits (Matt)
>
> v3:
> -move detach_scalers to crtc commit path (Matt)
> -use values in plane_sta
On Wed, Apr 01, 2015 at 07:59:49PM -0700, Chandra Konduru wrote:
> This patch enables skylake sprite plane display scaling using shared
> scalers atomic desgin.
>
> v2:
> -use single copy of scaler limits (Matt)
>
> v3:
> -detaching scalers moved to crtc commit path (Matt)
>
> Signed-off-by: Cha
On Wed, Apr 01, 2015 at 07:59:42PM -0700, Chandra Konduru wrote:
> During readout_hw_state, rebuild crtc scaler_state from hw state:
> - crtc scaler id
> - scaler users
This patch doesn't look like it actually does what you're advertising
here. If your firmware or bootloader or whatever has pro
On Wed, Apr 01, 2015 at 07:59:39PM -0700, Chandra Konduru wrote:
> intel_atomic_setup_scalers sets up scalers based on staged scaling
> requests coming from a crtc and its planes. This function should be
> called from crtc level check path.
>
> If staged requests are supportable, function assigns
On Wed, Apr 01, 2015 at 07:59:38PM -0700, Chandra Konduru wrote:
> This helper function stages a scaler request for a plane/crtc into
> crtc_state->scaler_users (which is a bit field). It also performs
> required checks before staging any change into scaler_state.
>
> v2:
> -updates to use single
On Wed, Apr 01, 2015 at 07:59:40PM -0700, Chandra Konduru wrote:
> This function is called from commit path of a plane or crtc.
> It programs scaler registers to detach (aka. unbinds) scaler
> from requested plane or crtc if it isn't in use. It also resets
> scaler_id in crtc/plane state.
The last
On Wed, Apr 01, 2015 at 07:59:35PM -0700, Chandra Konduru wrote:
> This patch converts intel_plane_state->src rect from 16.16
> values into regular ints.
>
> This approach aligns with sprite_plane_state->src rects
> which are already in regular ints.
>
> Signed-off-by: Chandra Konduru
You're no
On Wed, Apr 01, 2015 at 07:59:37PM -0700, Chandra Konduru wrote:
> Helper function updates supported scaling ratios based on cdclk and
> crtc clocks.
>
> v2:
> -update single copy of scaling ratios (Matt)
>
> v3:
> -min scaling ratio is limited by either display engine limit or clocks,
> it is n
On Wed, Apr 01, 2015 at 07:59:30PM -0700, Chandra Konduru wrote:
> Adding drm helper function to return plane pointer from index where
> index is a returned by drm_plane_index.
>
> v2:
> -avoided nested loop by adding loop count (Daniel)
>
> Signed-off-by: Chandra Konduru
This should just have
On Wed, Apr 01, 2015 at 07:59:32PM -0700, Chandra Konduru wrote:
> skylake scaler structure definitions. scalers live in crtc_state as
> they are pipe resources. They can be used either as plane scaler or
> panel fitter.
>
> scaler assigned to either plane (for plane scaling) or crtc (for panel
>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6122
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 272/272
On Wed, Apr 01, 2015 at 08:20:44AM +0200, Daniel Vetter wrote:
> On Tue, Mar 31, 2015 at 09:59:22AM -0700, jeff.mc...@intel.com wrote:
> > From: Jeff McGee
> >
> > BXT uses a subset of the SKL fuse registers, because it has at
> > most 1 slice and at most 6 EU per subslice.
> >
> > Signed-off-by
On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Warn if the conditions to enter or exit DC6 are not satisfied such
> as support for runtime PM, state of power well, CSR loading etc.
>
> v2: Removed camelcase in functions and variables.
>
> v3: Do some minimal che
On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Enable runtime PM for Skylake platform
>
> v2: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
>
> Issue: VIZ-2819
> Signed-off-by: A.Sunil Kamath
> Signed-off-by: Suketu Shah
> Signed-off-by
On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers for DC6 as per details provided in skl_enable_dc6
> and skl_disable_dc6 implementations.
>
> Also Call POSTING_READ for every write to a register to ensure
> it is written to immediately
>
> v1: Remove
On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: "A.Sunil Kamath"
>
> This patch just implements the basic enable and disable
> functions of DC6 state which is needed for SKL platform.
>
> Its important to load SKL CSR program before calling enable.
>
> DC6 is a deeper power savi
On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Warn if the conditions to enter or exit DC5 are not satisfied such
> as support for runtime PM, state of power well, CSR loading etc.
>
> v2: Removed camelcase in functions and variables.
>
> v3: Do some minimal che
On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers as per expectations mentioned in gen9_enable_dc5
> and gen9_disable_dc5 patch.
>
> Also call POSTING_READ for every write to a register to ensure that
> its written immediately.
>
> v1: Remove POSTING_R
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6120
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 272/272
On 04/02/2015 11:42 AM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote:
>> I guess this is a lie for 8xx, but newer stuff takes care of this for
>> us.
>>
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
>> Signed-off-by: Jesse Barnes
>> ---
>>
On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote:
> I guess this is a lie for 8xx, but newer stuff takes care of this for
> us.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
> 1 fil
I guess this is a lie for 8xx, but newer stuff takes care of this for
us.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
Hi Shuang,
Looking at starting with '*':
*BYT igt@gem_exec_bad_domains@conflicting-write-domain PASS(9)
FAIL(1)PASS(1)
Above failure seems unrelated to my patch series. I suspect this
pre-exist before my changes.
Can you double check whether above failure is pre-existing before
any action
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6119
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 272/272
Jesse Barnes virtuousgeek.org> writes:
> Looks like it was introduced in:
>
> commit 650ad970a39f8b6164fe8613edc150f585315289
> Author: Imre Deak intel.com>
> Date: Fri Apr 18 16:35:02 2014 +0300
>
> drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending
> force-of
>
> b
On 31 March 2015 at 13:53, Joonas Lahtinen
wrote:
> Install the test programs by default so that they can be packaged.
>
> Tested with the testdisplay test so that it still runs after the
> modifications as it depends on a data file to be present. Need to
> pass -r option to enable QR code display
The tracing infrastructure is adding a macro TRACE_SYSTEM_STRING, and
hit the following build failure:
In file included from include/trace/define_trace.h:90:0,
from drivers/gpu/drm/.//radeon/radeon_trace.h:209,
from drivers/gpu/drm/.//radeon/radeon_trace
On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
> From: Vandana Kannan
>
> Add display clock/PHY initialization sequence as per BSpec.
>
> Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
> value with 624 MHz and returning 0 in case it exceeds.
>
> Note that t
On Thu, Apr 02, 2015 at 05:11:58PM +0100, Tvrtko Ursulin wrote:
> >+static struct drm_i915_gem_object *
> >+find_object_from_vma(struct drm_device *dev,
> >+ struct drm_i915_gem_userptr *args)
> >+{
> >+struct drm_i915_gem_object *obj = NULL;
> >+struct vm_area_struct *vma;
Hi,
Typo in subject, then below.
On 04/02/2015 04:04 PM, Chris Wilson wrote:
Once userptr becomes part of client API, it is almost a certainly that
eventually someone will try to create a new object from a mapping of
another client object, e.g.
new = vaImport(vaMap(old, &size), size);
(using
On 2 April 2015 at 13:54, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
Just two things from an i-g-t perspective: the new binary needs adding
to .gitignore and it would be good to include a short description of
the test using the
On Thu, Apr 02, 2015 at 10:24:02AM +0530, Jindal, Sonika wrote:
>
>
> On 4/1/2015 11:52 PM, Matt Roper wrote:
> >On Mon, Mar 30, 2015 at 02:04:57PM +0530, Sonika Jindal wrote:
> >>v2: Moving creation of property in a function, checking for 90/270
> >>rotation simultaneously (Chris)
> >>Letting pr
On ke, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: "A.Sunil Kamath"
>
> This patch just implements the basic enable and disable
> functions of DC5 state which is needed for both SKL and BXT.
>
> Its important to load respective CSR program before calling
> enable, which anyways will
On Thu, Apr 02, 2015 at 10:08:27AM +0530, Jindal, Sonika wrote:
>
>
> On 4/1/2015 11:51 PM, Matt Roper wrote:
> >On Mon, Mar 30, 2015 at 02:04:56PM +0530, Sonika Jindal wrote:
> >>Signed-off-by: Sonika Jindal
> >
> >It looks like this is dependent on Ville's patch
> >
> > [PATCH v2 6/9] drm/i9
From: Ville Syrjälä
../drivers/gpu/drm/i915/intel_pm.c:3185:45: warning: Initializer entry defined
twice
../drivers/gpu/drm/i915/intel_pm.c:3185:52: also defined here
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Thu, Apr 02, 2015 at 07:21:40PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Sometimes, i915 might call _wait_for when irq is disabled.
> If the cpu is the main cpu to process jiffies, jiffies
> wouldn't be increased as this cpu disables irq. Then,
> time_after(jiffies, timeout_
On ke, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: "A.Sunil Kamath"
>
> Display Context Save and Restore support is needed for
> various SKL Display C states like DC5, DC6.
>
> This implementation is added based on first version of DMC CSR program
> that we received from h/w team.
>
Once userptr becomes part of client API, it is almost a certainly that
eventually someone will try to create a new object from a mapping of
another client object, e.g.
new = vaImport(vaMap(old, &size), size);
(using a hypothethical API, not meaning to pick on anyone!)
Since this is actually fair
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6118
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 272/272
From: Deepak S
Sometimes, i915 might call _wait_for when irq is disabled.
If the cpu is the main cpu to process jiffies, jiffies
wouldn't be increased as this cpu disables irq. Then,
time_after(jiffies, timeout__) becomes meaningless. If
gunit doesn't work now, kernel wouldn't exit as the timeout
On Thu, Apr 02, 2015 at 06:54:34PM +0800, liu,lei wrote:
> From: "liu,lei"
>
> According DMT spec, vss of this mode should be 1393, vse should
> be 1396.
>
> VESA MONITOR TIMING STANDARD:
>
> Timing Name = 1856 x 1392 @ 75Hz
> Hor Total Time = 8.889; (usec) = 320 chars = 2560 Pixels
> Hor Sync
From: Deepak S
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
v2: add a new err_idr (Daniel)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/g
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915
Hi Chris:
I begin to understand that before the "prev" context object is unpinned,
it's set to active by i915_vma_move_to_active, so the shrinker will wait for
it. Thanks for the help. Every time I learned a lot from you. Thanks. :)
-Original Message-
From: Chris Wilson [mailto:ch..
From: Tvrtko Ursulin
This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
Similar to some other tests, it uses knowledge of the DRM
allocation policy in order to get two objects mapped adjacent
to each other. It is then possible to verify that the pad to
size flag will move them apart.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6113
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 272/272
Hi Dave -
A colorkey ioctl oops fix from Ville, cc: stable, and a backport of
Chris' 0-length batch allocation fix from drm-next.
BR,
Jani.
The following changes since commit e42391cd048809d903291d07f86ed3934ce138e9:
Linux 4.0-rc6 (2015-03-29 15:26:31 -0700)
are available in the git repos
Please prefix the subject with "drm/edid: " and send the patch to
dri-de...@lists.freedesktop.org.
In general, scripts/get_maintainer.pl will tell you where to send the
patches; intel-gfx is for stuff under drivers/gpu/drm/i915.
Thanks,
Jani.
On Thu, 02 Apr 2015, "liu,lei" wrote:
> From: "liu,
Reduce dependency on the staged config by using the atomic state
instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drive
Move towards atomic by using the atomic state instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_disp
These patches remove usage of the staged config from the modeset path
that I overlooked in my previous patch series.
Ander Conselvan de Oliveira (6):
drm/i915: Don't use staged config for VLV cdclk calculations
drm/i915: Don't use intel_crtc->new_config in pll calculation code
drm/i915: Remo
Now that we use a drm atomic state for the legacy modeset, it is
possible to get rid of the usage of intel_crtc->new_config in the
function intel_mode_max_pixclk().
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 55 +++-
1 f
It's not needed anymore, now that all the users were converted to using
an atomic state.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 31 ---
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 32 deletions(-)
diff
Reduce dependency on the staged config by using the atomic state
instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 35 +--
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_disp
For the conversion to atomic. The pre_enable() hooks are called as part
of the crtc enable sequence, at which point the staged config was
already made effective. Furthermore, the function actually changes
hardware state, so it should anyway deal with current and not staged
config.
Signed-off-by: A
On Thu, Apr 02, 2015 at 04:39:56PM +0530, Deepak S wrote:
>
>
> On Friday 27 March 2015 04:31 PM, Chris Wilson wrote:
> >This reverts commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
> >Author: Chris Wilson
> >Date: Thu Jun 12 10:28:55 2014 +0100
> >
> > drm/i915: Restrict GPU boost to the
On vblank instant-off systems, we can get into a situation where the cost
of enabling and disabling the vblank IRQ around a drmWaitVblank query
dominates. However, we know that if the user wants the current vblank
counter, they are also very likely to immediately queue a vblank wait
and so we can k
On Friday 27 March 2015 04:31 PM, Chris Wilson wrote:
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to comp
On Friday 27 March 2015 04:31 PM, Chris Wilson wrote:
This reverts commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
Author: Chris Wilson
Date: Thu Jun 12 10:28:55 2014 +0100
drm/i915: Restrict GPU boost to the RCS engine
The premise that media/blitter workloads are not affected by boos
On Thu, Apr 02, 2015 at 11:45:59AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
>
> Similar to some other tests, it uses knowledge of the DRM
> allocation policy in order to get two objects mapped adjacent
> to each other.
On Tue, 31 Mar 2015, Steven Honeyman wrote:
> On 31 March 2015 at 17:50, Matt Roper wrote:
>> On Tue, Mar 31, 2015 at 08:54:19AM +0200, Daniel Vetter wrote:
>>> Adding mailing lists (and hooray for me mixing up addresses, so now
>>> there's a disclaimer at the bottom).
>>> -Daniel
>>
>> It looks
On 04/01/2015 04:08 PM, Damien Lespiau wrote:
On Wed, Apr 01, 2015 at 01:18:25PM +0530, Animesh Manna wrote:
+struct intel_css_header {
Just a small question, what does CSS mean in this context? that's the
first time I see it.
CSS stands for "Code signing service". In case on Guc/Huc, firmwa
From: "liu,lei"
According DMT spec, vss of this mode should be 1393, vse should
be 1396.
VESA MONITOR TIMING STANDARD:
Timing Name = 1856 x 1392 @ 75Hz
Hor Total Time = 8.889; (usec) = 320 chars = 2560 Pixels
Hor Sync Start = 6.889; (usec) = 248 chars = 1984 Pixels
H Back Porch = 1.222; (use
On 04/01/2015 05:39 PM, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 05:31:16PM +0100, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 05:07:25PM +0100, Tvrtko Ursulin wrote:
On 04/01/2015 04:42 PM, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 04:14:52PM +0100, Tvrtko Ursulin wrote:
+ /* Re
From: Tvrtko Ursulin
This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
Similar to some other tests, it uses knowledge of the DRM
allocation policy in order to get two objects mapped adjacent
to each other. It is then possible to verify that the pad to
size flag will move them apart.
On Thursday 02 April 2015 02:52 AM, Jesse Barnes wrote:
Looks like it was introduced in:
commit 650ad970a39f8b6164fe8613edc150f585315289
Author: Imre Deak
Date: Fri Apr 18 16:35:02 2014 +0300
drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending
force-of
but I'm not su
On Thursday 02 April 2015 02:52 AM, Jesse Barnes wrote:
Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
reg. If it's unlocked, we can just restore the previous value, and if
it's locked (in case the BIOS re-programmed it for us) the write will be
ignored and we'll still h
On Thu, Apr 02, 2015 at 01:05:31PM +0300, Mika Kahola wrote:
> Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> into one function 'intel_modeset_global_pipes()'
>
> v2:
> - we don't modify 'disable_pipes', so passing this as a pointer
> is removed (based on Ville's comment
On Thu, Apr 02, 2015 at 10:35:08AM +0100, Chris Wilson wrote:
> Sometimes userspace wants a true overlay that is never clipped. In such
> cases, we need to disable the destination colorkey. However, it is
> currently unconditionally enabled in the overlay with no means of
> disabling. So rectify th
On Thu, Apr 02, 2015 at 02:02:17PM +0530, Praveen Paneri wrote:
> realloc will return NULL if failed to allocate the extra memory
> requested. Return from function if it fails.
NAK. Silently passing absolute addresses to the GPU to read and write is
not a good idea.
-Chris
--
Chris Wilson, Intel
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6112
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4 272/272
Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'
v2:
- we don't modify 'disable_pipes', so passing this as a pointer
is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
routin
Sometimes userspace wants a true overlay that is never clipped. In such
cases, we need to disable the destination colorkey. However, it is
currently unconditionally enabled in the overlay with no means of
disabling. So rectify that by always default to on, and extending the
UPDATE_ATTR ioctl to sup
On Tue, Mar 31, 2015 at 05:45:56PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 02:14:23PM +0300, Mika Kahola wrote:
> > Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> > into one function 'intel_modeset_global_pipes()'
> >
> > Signed-off-by: Mika Kahola
> > ---
>
Hi,
On 04/02/2015 05:54 AM, Jindal, Sonika wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f0bbc22..86ee0f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2318,6 +2318,28 @@ intel_fill_fb_ggt
On Thu, Apr 02, 2015 at 10:45:39AM +0200, Olivier Fourdan wrote:
> When using Xinerama, RandR is automatically disabled, and calling RR
> routines will trigger an assert() because the RR keys/resources are
> not set, leading to an Xserver abort.
>
> Hotplug makes little sense without RandR, so it'
When using Xinerama, RandR is automatically disabled, and calling RR
routines will trigger an assert() because the RR keys/resources are
not set, leading to an Xserver abort.
Hotplug makes little sense without RandR, so it's safer to just return
if RandR is not available.
Signed-off-by: Olivier F
On Mon, 30 Mar 2015, Daniel Vetter wrote:
> On Fri, Mar 27, 2015 at 07:59:40PM +0200, ville.syrj...@linux.intel.com wrote:
>> From: Ville Syrjälä
>>
>> The legcy colorkey ioctls are only implemented for sprite planes, so
>> reject the ioctl for primary/cursor planes. If we want to support
>> col
A call to SLLocate() is missing from the function drmSLLookupNeighbors()
Adding the same to fix this bug.
Signed-off-by: Praveen Paneri
---
xf86drmSL.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/xf86drmSL.c b/xf86drmSL.c
index edafe7b..9c6f65a 100644
--- a/xf86drmSL.c
+++ b/xf86drmSL.c
This patch adds check for various malloc/calloc function if they
were able to allocate memory as requested or not. Return
appropriate error if the allocation fails.
Signed-off-by: Praveen Paneri
---
intel/intel_bufmgr_fake.c | 4
intel/intel_bufmgr_gem.c | 3 +++
intel/intel_decode.c
Move the dereferencing below the check for valid ctx pointer.
Signed-off-by: Praveen Paneri
---
intel/intel_decode.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index b70d949..5dab9ca 100644
--- a/intel/intel_decode.c
+++ b/i
We must have upper bound on what we are going to write into a fixed
size buffer.
Signed-off-by: Praveen Paneri
---
intel/intel_decode.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 7d5cbe5..b70d949 100644
--- a/inte
Check on bo_fake before dereferencing the object in functions
evict_lru and evict_mru.
Signed-off-by: Praveen Paneri
---
intel/intel_bufmgr_fake.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c
index c48
If the allocation fails, return -ENOMEM. Handle the return value
at the caller funtion drmSLInsert() as well.
Signed-off-by: Praveen Paneri
---
xf86drmSL.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/xf86drmSL.c b/xf86drmSL.c
index 45f3906..edafe7b 100644
--- a/xf86drmSL.c
+++ b/xf8
This patch adds check on various drmMalloc() calls if they
were able to allocate memory as requested or not. Return
appropriate error if the allocation fails.
Signed-off-by: Praveen Paneri
---
xf86drm.c | 51 ---
1 file changed, 40 insertions(+), 1
HASH_RANDOM_INIT() can fail to allocate memory. In such case return an
invalid hash value (0x) from HashHash() function.
Caller functions check the hash value and act accordingly.
Signed-off-by: Praveen Paneri
---
xf86drmHash.c | 9 +
1 file changed, 9 insertions(+)
diff --git a
This patch set fixes various issues reported by a static
analysis tool.
Praveen Paneri (12):
intel: Validate bo_fake before using.
intel: Validate output of realloc()
intel: Use snprintf instead of sprintf
intel: Validate pointer before using
xf86drm: Avoid negative array index value
Return value of drmHashCreate() and drmGetEntry() functions
can be NULL. It should be validated before being used.
Signed-off-by: Praveen Paneri
---
xf86drm.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/xf86drm.c b/xf86drm.c
index 373113b..d3a002
realloc will return NULL if failed to allocate the extra memory
requested. Return from function if it fails.
Signed-off-by: Praveen Paneri
---
intel/intel_bufmgr_gem.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/intel/intel_bufmgr_ge
Variable retcode can be negative as well. Put the correct
condition on it before using it as array index.
Signed-off-by: Praveen Paneri
---
xf86drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xf86drm.c b/xf86drm.c
index e73cddd..1e25424 100644
--- a/xf86drm.c
+++ b/xf86
Validate the return value of SLCreateEntry() before using it.
Signed-off-by: Praveen Paneri
---
xf86drmSL.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xf86drmSL.c b/xf86drmSL.c
index acddb54..45f3906 100644
--- a/xf86drmSL.c
+++ b/xf86drmSL.c
@@ -139,6 +139,7 @@ void *drmSLCreate(void
On Fri, 27 Mar 2015, Daniel Vetter wrote:
> On Fri, Mar 27, 2015 at 09:10:02AM +0100, Daniel Vetter wrote:
>> It's completely unused and Tommi noticed that the #define is borked
>> since forever. I've done a git search in userspace and only found
>> broken definitions and no users anywhere.
>>
>>
On Wed, 2015-04-01 at 14:22 -0700, Jesse Barnes wrote:
> Looks like it was introduced in:
>
> commit 650ad970a39f8b6164fe8613edc150f585315289
> Author: Imre Deak
> Date: Fri Apr 18 16:35:02 2014 +0300
>
> drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending
> force-of
>
>
Hi Dave -
Here's a single drm core fix, cc: stable, that affects i915
users. Picked it up myself as explained in [1].
I'll still send a separate drm/i915 pull request.
BR,
Jani.
[1] http://mid.gmane.org/874mp6r6bk@intel.com
The following changes since commit bc465aa9d045feb0e13b4a8f32cc33
1 - 100 of 104 matches
Mail list logo
