On Fri, May 22, 2015 at 08:29:28AM +0200, Daniel Vetter wrote:
> On Thu, May 21, 2015 at 07:36:44PM +0300, Ville Syrjälä wrote:
> > On Mon, May 18, 2015 at 04:18:44PM -0700, Chandra Konduru wrote:
> > > There is a mplayer video failure reported with xv.
> > > This is because there is a request to d
On Thu, May 21, 2015 at 07:36:44PM +0300, Ville Syrjälä wrote:
> On Mon, May 18, 2015 at 04:18:44PM -0700, Chandra Konduru wrote:
> > There is a mplayer video failure reported with xv.
> > This is because there is a request to do both plane scaling
> > and colorkey. Because skl hw doesn't support p
On Thu, May 21, 2015 at 01:18:44PM -0700, Jesse Barnes wrote:
> On 05/19/2015 10:32 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > GTT caching was disabled by default on gen8 due to not working with
> > big pages. Some information suggests that it got fixed, but still
>
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On Thu, 21 May 2015, Mario Kleiner wrote:
> On 05/20/2015 10:36 AM, Daniel Vetter wrote:
>> In
>>
>> commit f02ad907cd9e7fe3a6405d2d005840912f1ed258
>> Author: Daniel Vetter
>> Date: Thu Jan 22 16:36:23 2015 +0100
>>
>> drm/atomic-helpers: Recover full cursor plane behaviour
>>
>> we've ad
Please keep the intel-gfx list in Cc.
What about the live-cd or some such with a more recent driver stack? Or
just try a recent kernel. v2.6.32 is 5+ years old.
BR,
Jani.
On Thu, 21 May 2015, "Carlson, Benjamin P." wrote:
>I only get the standard (old) VGA resolution options of 1024x768,
On Thu, 21 May 2015, Jim Bride wrote:
> On Thu, May 21, 2015 at 03:04:40PM +0300, Jani Nikula wrote:
>> On Thu, 21 May 2015, Ville Syrjälä wrote:
>> > On Wed, May 20, 2015 at 04:07:37PM -0700, Todd Previte wrote:
>> >> Hi Jim,
>> >>
>> >> I checked the BSpec as well and there's nothing indicatin
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On Thu, 2015-05-21 at 23:33 +0200, Daniel Vetter wrote:
> On Thu, May 21, 2015 at 12:53:03PM -0700, Rodrigo Vivi wrote:
> > We cannot let IPS enabled with no plane on the pipe:
> >
> > BSpec: "IPS cannot be enabled until after at least one plane has
> > been enabled for at least one vertical blank
On Thu, May 21, 2015 at 12:53:03PM -0700, Rodrigo Vivi wrote:
> We cannot let IPS enabled with no plane on the pipe:
>
> BSpec: "IPS cannot be enabled until after at least one plane has
> been enabled for at least one vertical blank." and "IPS must be
> disabled while there is still at least one p
On Thu, May 21, 2015 at 10:35:07PM +0530, Animesh Manna wrote:
>
>
> On 5/21/2015 5:41 PM, Daniel Vetter wrote:
> >On Thu, May 21, 2015 at 03:49:52PM +0530, Animesh Manna wrote:
> >>Before enabling dc5/dc6, used wait for completion instead of busy waiting.
> >>
> >>v1:
> >>- Based on review comme
On Thu, May 21, 2015 at 12:26:21PM -0700, Jesse Barnes wrote:
> On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_sdvo.c | 25 +
> > 1 file changed, 17 insertio
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On 05/21/2015 06:00 AM, Chris Wilson wrote:
> On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
>> On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
>>> On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson
On 05/19/2015 10:32 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> GTT caching was disabled by default on gen8 due to not working with
> big pages. Some information suggests that it got fixed, but still
> GTT caching has been left disabled by default. Or could be it just
> mea
On 05/19/2015 10:32 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> GEN8_L3SQCREG1 isn't saved in the context (verified by going through
> a context dump), and so we shouldn't be using the ring w/a code to
> initialize it. Also Bspec explicitly talks about MMIO and writing it
>
On 05/19/2015 10:32 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We're not using ilk_init_lp_watermarks() on BDW for some reason.
> Probably due to the BDW patches and the relevant WM patches landing
> roughlly at the same time. Fix it up.
>
> Signed-off-by: Ville Syrjälä
With this well documented we can remove that FIXME comment.
We just need to make sure that on primary -> sprite transition there
is no vblank time where ips gets alone on the pipe with absolutelly
no plane. If this happens even for a quickly momment IPS won't get
recovered and it might cause stran
As Daniel commented on
commit b7ffe1362c5f468b853223acc9268804aa92afc8
Author: Chris Wilson
Date: Mon Apr 27 13:41:24 2015 +0100
drm/i915: Free RPS boosts for all laggards
it is better to be explicit when sharing hardcoded values such as
throttle/boost timeouts. Make it so!
Signed-off-by
When Daniel applied the RPS patches, only then did I realise that I
hadn't send the fresh series that incorporated the bit of feedback and
more importantly a couple of bug fixes!
Hopefully better late than never...
And now with the RPS in, we can get on to lots of fun patches to speed
up execbuff
In commit 1854d5ca0dd7a9fc11243ff220a3e93fce2b4d3e
Author: Chris Wilson
Date: Tue Apr 7 16:20:32 2015 +0100
drm/i915: Deminish contribution of wait-boosting from clients
we removed an atomic timer based check for allowing waitboosting and
moved it below the mutex taken during RPS. However,
To allow the user finer control over waitboosting, allow them to set the
frequency we request for the boost. This also them allows to effectively
disable the boosting by setting the boost request to a low frequency.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +
After allocating from the slab cache, we then need to free the request
back into the slab cache upon error (and not call kfree as that leads
to eventual memory corruption).
Fixes regression from
commit efab6d8dd158fdccbe6a030f89fbf9ca0a9564e4
Author: Chris Wilson
Date: Tue Apr 7 16:20:57 2015 +
We cannot let IPS enabled with no plane on the pipe:
BSpec: "IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank." and "IPS must be
disabled while there is still at least one plane enabled on the
same pipe as IPS.
However this shortcut path to mak
> Hm something seems to be deeply wrong here. And the oops you've captured
> still doesn't include the debug messages before things go boom. Can you
> please replace the WARN_ON in my previous patch with a BUG_ON? That should
> stop the machine at least and hopefully prevents it all from going boo
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> BSpec says we should disable all ports after the pipe on PCH
> platforms. Do so. Fixes a pipe off timeout on ILK now caused by
> the transcoder B workaround.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Currently the IBX transcoder B workarounds are not working correctly.
> Well, the HDMI one seems to be working somewhat, but the DP one is
> definitely busted.
>
> After a bit of experimentation it looks like
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> On IBX the SDVO/HDMI register write may be masked when enabling the
> port, so it may need to written twice. The HDMI code does this, but
> the SDVO code does not. Add the workaround to the SDVO code as well.
>
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Follow the BSpec sequence for the CRT port as well on PCH platforms,
> ie. disable the pipe before the port.
>
> Didn't bother looking at DDI in detail yet, so leave that one be even
> though the CRT is a PCH
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Bspec says we should disable the FDI RX/TX before disabling the PCH
> ports. Do so.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 +++--
> 1 file changed, 3 insertions(+),
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 25 +
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
>
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Currently we're always enabling enhanced framing on CPT even if the sink
> doesn't support it. Fix this up by actaully looking at what the sink
> tells us.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gp
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> intel_dp.c is a mess with all the checks for different
> platform/PCH variants and ports. Try to clean it up by recognizing
> the following facts:
> - IVB port A, and CPT port B/C/D are always the special cases
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Define a TRANS_DP_PIPE_TO_PORT() to make the CPT DP .get_hw_state()
> pipe readout neater.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c |
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> IBX can have problems with the first write to the port register getting
> masked when enabling the port. We are trying to apply the workaround
> also when disabling the port where it's not needed, and we also t
On 05/05/2015 07:17 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The IBX 12bpc port enable toggle is only relevant when enabling
> the port, not when disabling it. Also this code doesn't actually
> toggle anything, and essentially just writes the port register
> one extra ti
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[Cc'ing Chris, not sure if he saw the updated version to give his r-b]
On 05/06/2015 03:15 AM, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> This patch series adds support for creating/using Stolen memory backed
> objects.
>
> Despite being a unified memory architecture
On 05/04/2015 07:16 AM, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 12:22:56PM +0100, Chris Wilson wrote:
>> On Thu, Apr 30, 2015 at 01:28:46PM +0300, Joonas Lahtinen wrote:
>>> On ma, 2015-04-27 at 20:43 +0100, Chris Wilson wrote:
On Mon, Apr 27, 2015 at 06:35:54PM +0100, Thomas Wood wrote
On Thu, May 21, 2015 at 03:04:40PM +0300, Jani Nikula wrote:
> On Thu, 21 May 2015, Ville Syrjälä wrote:
> > On Wed, May 20, 2015 at 04:07:37PM -0700, Todd Previte wrote:
> >> Hi Jim,
> >>
> >> I checked the BSpec as well and there's nothing indicating that these
> >> two bits are mutually exclu
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Instead of having a PERF_EVENT_IOC_FLUSH ioctl this instead allows
userspace to use fsync for flushing pmu samples, as suggested by Ingo
Molnar - thanks.
For reference I've also pushed a patch to my Mesa branch to test
this: https://github.com/rib/mesa wip/rib/oa-hsw-4.0.0
- Robert
--- >8 ---
T
>From: Konduru, Chandra
>
>> >
>> > Hi Daniel,
>> > NV12 programming is documented in bspec under display planes "Plane
>> > Planar YUV programming". There it talks about aux_dist which is the
>> > distance between y and uv planes expecting uv to be after y.
>>
>> Bspec talks about wrap-around, whi
On 5/21/2015 5:41 PM, Daniel Vetter wrote:
On Thu, May 21, 2015 at 03:49:52PM +0530, Animesh Manna wrote:
Before enabling dc5/dc6, used wait for completion instead of busy waiting.
v1:
- Based on review comment from Daniel replaced mutex and related
implementation with completion. In current
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On Thu, May 21, 2015 at 04:24:00PM +, Konduru, Chandra wrote:
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -4499,9 +4499,11 @@ skl_update_scaler_users(
> > > rotation = DRM_ROTATE_0;
> > > }
> > >
> > > - need_scaling = i
On Thu, May 21, 2015 at 05:11:57PM +0100, Damien Lespiau wrote:
> On Thu, May 21, 2015 at 06:58:48PM +0300, Ville Syrjälä wrote:
> > > > Hmm, actually are we not calling the skl_init_cdclk() on boot at all? I
> > > > see
> > > > it only in the resume path.
> > >
> > > Yes that's correct, we alway
On Mon, May 18, 2015 at 04:18:44PM -0700, Chandra Konduru wrote:
> There is a mplayer video failure reported with xv.
> This is because there is a request to do both plane scaling
> and colorkey. Because skl hw doesn't support plane scaling
> and colorkey at the same time, request is failed which i
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, May 21, 2015 4:08 PM
> To: Mika Kuoppala
> Cc: intel-gfx@lists.freedesktop.org; m...@iki.fi; Barbalho, Rafael
> Subject: Re: [Intel-gfx] [PATCH 02/20] drm/i915: Force PD restore on dirty
> pp
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4499,9 +4499,11 @@ skl_update_scaler_users(
> > rotation = DRM_ROTATE_0;
> > }
> >
> > - need_scaling = intel_rotation_90_or_270(rotation) ?
> > - (src_h != dst_w || src
On Thu, May 21, 2015 at 06:58:48PM +0300, Ville Syrjälä wrote:
> > > Hmm, actually are we not calling the skl_init_cdclk() on boot at all? I
> > > see
> > > it only in the resume path.
> >
> > Yes that's correct, we always have display intialized by the firmware on
> > big core as far as I know (
> > > > > > This patch adds NV12 as supported format to
> > > > > > intel_framebuffer_init and performs various checks.
> > > > > >
> > > > > > Signed-off-by: Chandra Konduru
> > > > > > Testcase: igt/kms_nv12
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/intel_display.c | 27
> > > +
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Bin confirmed that, with the patch ,the issue didn't exist now.
Need a reviewer so the patch can be lined up for merge.
Ville or anyone in cc list?
-Chandra
> -Original Message-
> From: Konduru, Chandra
> Sent: Monday, May 18, 2015 4:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kondur
On Thu, May 21, 2015 at 04:49:40PM +0100, Damien Lespiau wrote:
> On Thu, May 21, 2015 at 06:44:53PM +0300, Ville Syrjälä wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index d602db2..cacb07b 100644
> > > --- a/drivers/gpu/drm/i915/intel_d
On Thu, May 21, 2015 at 04:37:48PM +0100, Damien Lespiau wrote:
> We need to re-init the display hardware when going out of suspend. This
> includes:
>
> - Hooking the PCH to the reset logic
> - Restoring CDCDLK
> - Enabling the DDB power
>
> Among those, only the CDCDLK one is a bit tricky
On Thu, May 21, 2015 at 04:20:04PM +0300, Ville Syrjälä wrote:
> On Wed, May 20, 2015 at 07:12:25PM -0700, Matt Roper wrote:
> > Various places in the driver need the ability to schedule actions to run
> > on a future vblank (updating watermarks, unpinning buffers, etc.). The
> > long term goal is
On Thu, May 21, 2015 at 06:44:53PM +0300, Ville Syrjälä wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index d602db2..cacb07b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2510,6 +2510,7 @@
On Thu, May 21, 2015 at 05:04:15PM +0300, Ville Syrjälä wrote:
> On Wed, May 20, 2015 at 07:12:17PM -0700, Matt Roper wrote:
> > Various places in the atomic plane code obtain the CRTC via
> > plane_state->crtc. But plane_state->crtc is NULL when disabling the
> > plane, so the code will fall back
On Thu, May 21, 2015 at 04:37:48PM +0100, Damien Lespiau wrote:
> We need to re-init the display hardware when going out of suspend. This
> includes:
>
> - Hooking the PCH to the reset logic
> - Restoring CDCDLK
> - Enabling the DDB power
>
> Among those, only the CDCDLK one is a bit tricky
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) ha
On Thu, May 21, 2015 at 04:22:55PM +0100, Chris Wilson wrote:
> On Thu, May 21, 2015 at 04:21:46PM +0200, Daniel Vetter wrote:
> > Hm right. What about emphasising this a bit more in the comment:
> >
> > /*
> > * Empirical evidence indicates that we need a write barrier to
> > * make
On Thu, May 21, 2015 at 04:21:46PM +0200, Daniel Vetter wrote:
> Hm right. What about emphasising this a bit more in the comment:
>
> /*
>* Empirical evidence indicates that we need a write barrier to
>* make sure write-combined writes (both to the gtt, but also to
>*
On Thu, May 21, 2015 at 05:37:40PM +0300, Mika Kuoppala wrote:
> As there is flushing involved when we have done the cpu
> write, make functions for mapping for cpu space. Make macros
> to map any type of paging structure.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gt
On Thu, May 21, 2015 at 05:37:39PM +0300, Mika Kuoppala wrote:
> When we setup page directories and tables, we point the entries
> to a to the next level scratch structure. Make this generic
> by introducing a fill_page_dma which maps and flushes. We also
> need 32 bit variant for legacy gens.
>
>
On Thu, May 21, 2015 at 05:37:30PM +0300, Mika Kuoppala wrote:
> Force page directory reload when ppgtt va->pa
> mapping has changed. Extend dirty rings mechanism
> for gen > 7 and use it to force pd restore in execlist
> mode when vm has been changed.
>
> Some parts of execlist context update cle
On Thu, May 21, 2015 at 05:37:44PM +0300, Mika Kuoppala wrote:
> During review of dynamic page tables series, I was able
> to hit a lite restore bug with execlists. I assume that
> due to incorrect pd, the batch run out of legit address space
> and into the scratch page area. The ACTHD was increasi
On Thu, May 21, 2015 at 04:30:34PM +0200, Nicolas Kalkhof wrote:
> Hi Daniel,
>
> > Ah, Chris hunch against my claim that this is impossible was spot-on. Can
> > you please try the below hack please and grab dmesg? Hopefully the kernel
> > won't die any more at least.
>
> Unfortunately the patch
All our paging structures have struct page and dma address
for that page.
Add struct for page/dma address pairs and use it to make
the setup and teardown for different paging structures
identical.
Include the page directory offset also in the struct for legacy
gens. Rename it to clearly point out
On Wed, May 20, 2015 at 02:45:16PM +0100, Damien Lespiau wrote:
> The macros we use there are the magic ones that can take either dev or
> dev_priv. We'd like to move as much as possible towards dev_priv though.
>
> Signed-off-by: Damien Lespiau
Patches 2 and 3 look fine to me.
Reviewed-by: Vil
On Wed, May 20, 2015 at 02:45:18PM +0100, Damien Lespiau wrote:
> We need to re-init the display hardware when going out of suspend. This
> includes:
>
> - Hooking the PCH to the reset logic
> - Restoring CDCDLK
> - Enabling the DDB power
>
> Among those, only the CDCDLK one is a bit tricky
Every time we allocate page structure, we fill it out
it to point into lower level scratch structure. But
as we have already setup scratch page directory and
scratch page table in when ppgtt was initialized, take
advantage of that and do a page copy from those.
Signed-off-by: Mika Kuoppala
---
d
Free the scratch page if dma mapping fails.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0ff381e..e4775d8 100644
--- a/d
Make paging structure type agnostic *_px macros to access
page dma struct, the backing page and the dma address.
This makes the code less cluttered on internals of
i915_page_dma.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +---
driv
Check the allocation area against the known end
of address space instead of against fixed value.
v2: Return ENODEV on internal bugs (Chris)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git
We can have exactly 4GB sized ppgtt with 32bit system.
size_t is inadequate for this.
Signed-off-by: Mika Kuoppala
---
drivers/char/agp/intel-gtt.c| 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 42 ++---
drivers/gpu/drm/i915/i915_gem.c | 6 +++---
d
Write page directory entry without using superfluous
indirect function. Also remove unused device parameter
from the encode function.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/dr
When we touch gen8+ page maps, mark them dirty like we
do with previous gens.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i9
All the paging structures are now similar and mapped for
dma. The unmapping is taken care of by common accessors, so
don't overload the reader with such details.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++-
1 file changed, 15 inserti
Dynamic page table allocation might wake the shrinker
when memory is requested for page table structures.
As this happens when we try to allocate the virtual address
during binding, our vma might be among the targets for eviction.
We should do i915_vma_pin() and do pin early in there like Chris
sug
Lay out scratch page structure in similar manner than other
paging structures. This allows us to use the same tools for
setup and teardown.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 91 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 9 ++
This has slipped in somewhere but it was harmless
as we check the page pointer before teardown.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index
Force page directory reload when ppgtt va->pa
mapping has changed. Extend dirty rings mechanism
for gen > 7 and use it to force pd restore in execlist
mode when vm has been changed.
Some parts of execlist context update cleanup based on
work by Chris Wilson.
v2: Add comment about lite restore (Ch
When we setup page directories and tables, we point the entries
to a to the next level scratch structure. Make this generic
by introducing a fill_page_dma which maps and flushes. We also
need 32 bit variant for legacy gens.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6
Scratch page is part of i915_address_space due to that we
have only one of that. Move other scratch entities into
the same struct. This is a preparatory patch for having
only one instance of each scratch_pt/pd.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 65 +++
As there is flushing involved when we have done the cpu
write, make functions for mapping for cpu space. Make macros
to map any type of paging structure.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++--
1 file changed, 35 insertions
We are always allocating a single page. No need to be verbose so
remove the suffix.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i91
During review of dynamic page tables series, I was able
to hit a lite restore bug with execlists. I assume that
due to incorrect pd, the batch run out of legit address space
and into the scratch page area. The ACTHD was increasing
due to scratch being all zeroes (MI_NOOPs). And as gen8
address spac
Hi,
My take on cleaning up more of the i915_gem_gtt.c.
The goal is to have generic tools to allocate and map
any type of paging structure.
And at the end we will have one instance of each scratch
chain type (scratch pd->pte->page) across all ppgtts,
saving 2 pages of memory per ppgtt.
Mika Kuopp
As we use one scratch page for all ppgtt instances, we can
use one scratch page table and scratch directory across
all ppgtt instances, saving 2 pages + structs per ppgtt.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 288 +++-
1 file chan
The legacy mode mm switch and the execlist context assigment
needs dma address for the page directories.
Introduce a function that encapsulates the scratch_pd dma
fallback if no pd is found.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++
drivers/gpu/drm/i915/i9
On Thu, May 21, 2015 at 3:35 AM, Ville Syrjälä
wrote:
> On Thu, May 21, 2015 at 01:25:28PM +0300, Jani Nikula wrote:
>> On Thu, 21 May 2015, Daniel Vetter wrote:
>> > On Wed, May 20, 2015 at 11:50:17PM +0300, Ville Syrjälä wrote:
>> >> On Wed, May 20, 2015 at 08:38:25PM +, Vivi, Rodrigo wrote
Hi Daniel,
> Ah, Chris hunch against my claim that this is impossible was spot-on. Can
> you please try the below hack please and grab dmesg? Hopefully the kernel
> won't die any more at least.
Unfortunately the patch doesn't keep my machine from crashing.
image of stack trace: http://imgur.com
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6437
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, May 21, 2015 at 02:13:01PM +0100, Chris Wilson wrote:
> On Thu, May 21, 2015 at 03:07:54PM +0200, Daniel Vetter wrote:
> > On Thu, May 21, 2015 at 02:00:34PM +0100, Chris Wilson wrote:
> > > On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
> > > > On Mon, May 11, 2015 at 04:25:
On 05/20/2015 10:36 AM, Daniel Vetter wrote:
In
commit f02ad907cd9e7fe3a6405d2d005840912f1ed258
Author: Daniel Vetter
Date: Thu Jan 22 16:36:23 2015 +0100
drm/atomic-helpers: Recover full cursor plane behaviour
we've added a hack to atomic helpers to never to vblank waits for
cursor up
On Wed, May 20, 2015 at 07:12:15PM -0700, Matt Roper wrote:
> We never removed the sprite watermark updates from our low-level
> foo_update_plane() functions; since our hardware updates happen under
> vblank evasion, we're not supposed to be calling potentially sleeping
> functions there (since int
On Wed, May 20, 2015 at 07:12:17PM -0700, Matt Roper wrote:
> Various places in the atomic plane code obtain the CRTC via
> plane_state->crtc. But plane_state->crtc is NULL when disabling the
> plane, so the code will fall back to looking at the old CRTC value in
> plane->crtc in that case. This
On Wed, May 20, 2015 at 07:12:15PM -0700, Matt Roper wrote:
> We never removed the sprite watermark updates from our low-level
> foo_update_plane() functions; since our hardware updates happen under
> vblank evasion, we're not supposed to be calling potentially sleeping
> functions there (since int
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