On Fri, Jun 05, 2015 at 03:58:23PM -0700, Rodrigo Vivi wrote:
Due to RTL Bug, GAM does not support enabling GTT cache when
big pages are also turned on. This leads to GAM reporting
incorrect data and address.
We don't use big pages, so we can leave GTT caching enabled until we
support them
On Mon, Jun 08, 2015 at 06:03:19PM +0100, Tomas Elf wrote:
When submitting semaphores in execlist mode the hang checker crashes in this
function because it is only runnable in ring submission mode. The reason this
is of particular interest to the TDR patch series is because we use semaphores
On 06/08/2015 07:10 PM, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai minu.mat...@intel.com)
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
In preparation for per-engine reset add way for setting context reset stats.
OPEN QUESTIONS:
1. How do we deal with get_reset_stats and the GL robustness interface when
introducing per-engine resets?
a. Do we set context
The original idea of preallocating the OLR was implemented in
9d773091 drm/i915: Preallocate next seqno before touching the ring
and the sequence of operations was to allocate the OLR, then wrap past
the end of the ring if necessary, then wait for space if necessary.
But subsequently
On 08/06/15 19:40, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 07:00:49PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 08:34:51PM +0300, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 06:12:47PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:08:00PM +0100, Dave Gordon wrote:
On
On Mon, Jun 08, 2015 at 06:03:23PM +0100, Tomas Elf wrote:
@@ -4089,11 +4130,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct
drm_file *file)
unsigned reset_counter;
int ret;
- ret = i915_gem_wait_for_error(dev_priv-gpu_error);
- if (ret)
-
On Mon, Jun 08, 2015 at 06:03:24PM +0100, Tomas Elf wrote:
Now that i915_wait_request takes per-engine hang recovery into account it is
more likely to fail and return -EAGAIN or -EIO due to hung engines (unlike
before when it would only fail if a full GPU reset was imminent). What this
means
On Mon, Jun 08, 2015 at 07:00:49PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 08:34:51PM +0300, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 06:12:47PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:08:00PM +0100, Dave Gordon wrote:
On 08/06/15 17:28, Imre Deak wrote:
-Original Message-
From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
Sent: Friday, June 05, 2015 11:39 PM
To: Konduru, Chandra; Roper, Matthew D
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/24] drm/i915: Do not add planes from
On Mon, Jun 08, 2015 at 06:12:47PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:08:00PM +0100, Dave Gordon wrote:
On 08/06/15 17:28, Imre Deak wrote:
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion
On Mon, Jun 08, 2015 at 08:42:20PM +0300, Abdiel Janulgue wrote:
On 06/08/2015 07:10 PM, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai
On Mon, Jun 08, 2015 at 06:03:28PM +0100, Tomas Elf wrote:
1. The i915_wedged_set function allows us to schedule three forms of hang
recovery:
a) Legacy hang recovery: By passing e.g. -1 we trigger the legacy full
GPU reset recovery path.
b) Single engine hang recovery:
On Mon, Jun 08, 2015 at 08:34:51PM +0300, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 06:12:47PM +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:08:00PM +0100, Dave Gordon wrote:
On 08/06/15 17:28, Imre Deak wrote:
By running igt/store_dword_loop_render on BXT we can hit a
From: Paulo Zanoni paulo.r.zan...@intel.com
This is a new test that should exercise the frontbuffer tracking
feature of the Kernel in a number of different ways. We use different
drawing methods, we use the primary, cursor and sprite planes, we can
test both on single and dual pipes, also on
Due to a coherency issue on BXT-A1 we can't guarantee a coherent view of
cached GPU mappings, so fall back to uncached mappings. Note that this
still won't fix cases where userspace expects a coherent view without
synchronizing (via a set domain call). It still makes sense to limit the
kernel's
Running some basic igt tests on BXT A1 stepping uncovered a coherency
problem where a cached CPU mapping won't be updated by a GPU store via a
snooped mapping. While I opened an internal ticket to investigate this
further this patchset is an attempt to work around the problem until a
better
v2:
- add a subtest for uncached mappings too for LLC platforms where the
default is cached mapping (Chris)
Signed-off-by: Imre Deak imre.d...@intel.com
---
tests/gem_storedw_batches_loop.c | 21 +
1 file changed, 21 insertions(+)
diff --git
On Mon, Jun 08, 2015 at 06:08:00PM +0100, Dave Gordon wrote:
On 08/06/15 17:28, Imre Deak wrote:
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion time is not
seen by the CPU. This results in __i915_wait_request
When submitting semaphores in execlist mode the hang checker crashes in this
function because it is only runnable in ring submission mode. The reason this
is of particular interest to the TDR patch series is because we use semaphores
as a mean to induce hangs during testing (which is the
This change introduces support for TDR-style per-engine reset as a initial,
less intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. Initially we're only
supporting gen8 but adding support for gen7 is straight-forward since
On ma, 2015-06-08 at 18:08 +0100, Dave Gordon wrote:
On 08/06/15 17:28, Imre Deak wrote:
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion time is not
seen by the CPU. This results in __i915_wait_request seeing the
On ma, 2015-06-08 at 18:09 +0100, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 08:07:29PM +0300, Imre Deak wrote:
v2:
- add a subtest for uncached mappings too for LLC platforms where the
default is cached mapping (Chris)
Signed-off-by: Imre Deak imre.d...@intel.com
---
i915_gem_wedge now returns a positive result in three different cases:
1. Legacy: A hang has been detected and full GPU reset has been promoted.
2. Per-engine recovery:
a. A single engine reference can be passed to the function, in which
case only that engine will be checked. If
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion time is not
seen by the CPU. This results in __i915_wait_request seeing the stale
seqno and not completing the request (not considering the lost
interrupt/GPU reset
This patch series introduces the following features:
* Feature 1: TDR (Timeout Detection and Recovery) for gen8 execlist mode.
TDR is an umbrella term for anything that goes into detecting and recovering
from GPU hangs and is a term more widely used outside of the upstream driver.
This feature
Now that i915_wait_request takes per-engine hang recovery into account it is
more likely to fail and return -EAGAIN or -EIO due to hung engines (unlike
before when it would only fail if a full GPU reset was imminent). What this
means is that the display driver might see more frequent failures that
There used to be a work queue separating the error handler from the hang
recovery path, which was removed a while back in this commit:
commit b8d24a06568368076ebd5a858a011699a97bfa42
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Wed Jan 28 17:03:14 2015 +0200
1. The i915_wedged_set function allows us to schedule three forms of hang
recovery:
a) Legacy hang recovery: By passing e.g. -1 we trigger the legacy full
GPU reset recovery path.
b) Single engine hang recovery: By passing an engine ID in the interval
of [0,
Defined trace points and sprinkled the usage of these throughout the
TDR/watchdog implementation.
The following trace points are supported:
1. trace_i915_tdr_gpu_recovery:
Called at the onset of the full GPU reset recovery path.
2. trace_i915_tdr_engine_recovery:
Watchdog timeout (or media engine reset as it is sometimes called, even
though the render engine is also supported) is a feature that allows userland
applications to enable hang detection on individual batch buffers. The
detection mechanism itself is mostly bound to the hardware and the only thing
The TDR ULT used to validate this patch series requires a special uevent for
full GPU resets in order to distinguish between different kinds of resets.
Signed-off-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 29 ++---
1 file changed, 22
On Mon, Jun 08, 2015 at 08:07:29PM +0300, Imre Deak wrote:
v2:
- add a subtest for uncached mappings too for LLC platforms where the
default is cached mapping (Chris)
Signed-off-by: Imre Deak imre.d...@intel.com
---
tests/gem_storedw_batches_loop.c | 21 +
1 file
In preparation for per-engine reset add way for setting context reset stats.
OPEN QUESTIONS:
1. How do we deal with get_reset_stats and the GL robustness interface when
introducing per-engine resets?
a. Do we set context that cause per-engine resets as guilty? If so, how
does
On Sat, Jun 06, 2015 at 05:21:41PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 6/6/2015 6:30 AM, Matt Roper wrote:
On Thu, Jun 04, 2015 at 07:12:35PM +0530, Kausal Malladi wrote:
From: Kausal Malladi kausal.mall...@intel.com
This patch adds a new structure in DRM layer for Gamma
On Sat, Jun 06, 2015 at 05:34:45PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 6/6/2015 6:31 AM, Matt Roper wrote:
On Thu, Jun 04, 2015 at 07:12:37PM +0530, Kausal Malladi wrote:
From: Kausal Malladi kausal.mall...@intel.com
The atomic CRTC set infrastructure is not available yet.
Hi Jani,
On Fri, 05 Jun 2015 11:03:20 +0300 Jani Nikula jani.nik...@intel.com wrote:
On Fri, 05 Jun 2015, m...@ellerman.id.au mich...@ozlabs.org wrote:
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/intel_ringbuffer.c between commit 4f47c99a9be7
On Sat, Jun 06, 2015 at 05:24:46PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 6/6/2015 6:30 AM, Matt Roper wrote:
On Thu, Jun 04, 2015 at 07:12:36PM +0530, Kausal Malladi wrote:
From: Kausal Malladi kausal.mall...@intel.com
This patch adds a new function to update color blob
The offload screens on an nvidia gpu show dirt on them, this is due to the
stuff not being flushed fully back to the CPU side and into main memory,
for the secondary GPU to pick it up from.
This is the hack I used to have in UXA, which works here, however I'm sure
this isn't acceptable for
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/intel_ringbuffer.c between commit 4f47c99a9be7 (drm/i915:
Move WaBarrierPerformanceFixDisable:skl to skl code from chv code) from the
drm-intel-fixes tree and commit b62adbd1ea1f (drm/i915/bxt: Move
[Since this has been publicly reported, I'm moving secur...@kernel.org to Bcc]
On Tue, May 5, 2015 at 2:39 PM, Rebecca N. Palmer
rebecca_pal...@zoho.com wrote:
Repeating those tests[1] on linux-next 20150505 gave the same results,
but having seen the intermittent no window title bar problem
Hey,
Op 04-06-15 om 14:47 schreef Maarten Lankhorst:
snip
@@ -12505,53 +12515,37 @@ static void update_scanline_offset(struct
intel_crtc *crtc)
crtc-scanline_offset = 1;
}
-static int intel_modeset_setup_plls(struct drm_atomic_state *state)
+static void
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai minu.mat...@intel.com)
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
Hi,
Although most of this patches were alread reviewed, I am resending them
due to additional changes suggested by Jani Nikula. In addition
Mesa folks want RS to be working with hiccups on GEN8 as well so
I added the necessary support for that platform as well.
Changes since last posting:
- Make
Also clarify comments on context size that the extra state for
Resource Streamer is included.
v2: Don't remove the extended save/restore enabled for older
platforms. (Ville)
Use new MI_SET_CONTEXT defines for HSW RS save/restore state
instead of extended save/restore. (Daniel)
v3: Add
Ensures that the batch buffer is executed by the resource streamer
v2: Don't skip 115 for the exec flags (Jani Nikula).
Add I915_PARAM_HAS_RESOURCE_STREAMER to check if kernel has RS support
baked in (Kenneth Graunke).
Testcase: igt/gem_exec_params
Cc: Jani Nikula jani.nik...@intel.com
On Mon, Jun 08, 2015 at 12:12:41PM +0300, Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Fri, May 22, 2015 at 08:17:22PM +0300, Mika Kuoppala wrote:
We initialize the internal read pointer to zero on init/reset,
but only the reset will actually zero the write
On Mon, Jun 08, 2015 at 12:12:41PM +0300, Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Fri, May 22, 2015 at 08:17:22PM +0300, Mika Kuoppala wrote:
We initialize the internal read pointer to zero on init/reset,
but only the reset will actually zero the write
Chris Wilson ch...@chris-wilson.co.uk writes:
On Fri, May 22, 2015 at 08:17:22PM +0300, Mika Kuoppala wrote:
We initialize the internal read pointer to zero on init/reset,
but only the reset will actually zero the write pointer.
This means that on module reload we might re-read context
On Mon, Jun 08, 2015 at 01:15:39PM +0300, Ville Syrjälä wrote:
On Mon, Jun 08, 2015 at 12:12:41PM +0300, Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Fri, May 22, 2015 at 08:17:22PM +0300, Mika Kuoppala wrote:
We initialize the internal read pointer to zero on
This change is needed for some hardware composer tests in chv.
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Friday, June 5, 2015 2:08 PM
To: Mathai, Minu
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Correcting the
On Mon, 08 Jun 2015, Mathai, Minu minu.mat...@intel.com wrote:
This change is needed for some hardware composer tests in chv.
As Ville said, this #define is not used by the upstream kernel on
byt/chv. Maybe you have some out-of-tree patches using that?
BR,
Jani.
-Original Message-
terribly sorry for the typos:
On 06/08/2015 01:04 PM, Abdiel Janulgue wrote:
Although most of this patches were alread reviewed, I am resending them
*already
due to additional changes suggested by Jani Nikula. In addition
Mesa folks want RS to be working with hiccups on GEN8 as well so
On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai minu.mat...@intel.com)
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Abdiel Janulgue
Signed-off-by: Imre Deak imre.d...@intel.com
---
tests/gem_storedw_batches_loop.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/gem_storedw_batches_loop.c b/tests/gem_storedw_batches_loop.c
index dcc11a5..8706b80 100644
--- a/tests/gem_storedw_batches_loop.c
+++
On Mon, Jun 08, 2015 at 07:29:30PM +0300, Imre Deak wrote:
Signed-off-by: Imre Deak imre.d...@intel.com
---
tests/gem_storedw_batches_loop.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/gem_storedw_batches_loop.c
b/tests/gem_storedw_batches_loop.c
index
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