Tomas Elf writes:
> On 16/06/2015 18:10, Chris Wilson wrote:
>> On Tue, Jun 16, 2015 at 04:39:23PM +0300, Mika Kuoppala wrote:
>>> In order for skl+ hardware to guarantee that no context switch
>>> takes place during reset and that current context is properly
>>> saved, the driver needs to notify
Hey,
Op 17-06-15 om 00:12 schreef Matt Roper:
> On Mon, Jun 08, 2015 at 06:59:38AM +0200, Maarten Lankhorst wrote:
>> Hey,
>>
>> Op 06-06-15 om 00:08 schreef Matt Roper:
>>> We need to call drm_atomic_set_mode_for_crtc() rather than copying the
>>> mode in manually. As of commit
>>>
>>> c
From: Dave Airlie
Add new verbs GET_DP_STREAM_ID and SET_DP_STREAM_ID from Intel docs.
get stream id and print in proc
split ELD to be per device not per pin
handle pd/eldv per device not per pin
setup codec->dp_mst earlier.
Signed-off-by: Dave Airlie
---
include/sound/hda_verbs.h | 2 +
so
From: Dave Airlie
This breaks MST audio, as it appears the hw doesn't
operate like the code believes.
What seems to happen if we have 3 pins, 5, 6, 7
and 6 is connected to 3 devices and 5/7 are connected
to 0 devices, then devices 5/7 act always as if they
are equivalent to pin 6 device 0.
So I
From: Dave Airlie
This just adds enables for the codecs and debugfs
support for mst connectors to print the audio info.
This relies on patches to the audio code to do anything
more useful.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +
drivers/gpu/drm/i
From: Dave Airlie
This adds code to initialise the SDP streams
for a sink in the simplest ordering.
I've no idea how you'd want to control the
ordering at this level, so don't bother
until someone comes up with a use case.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_dp_mst_topology.c |
Hi guys,
Since the audio folks have ignored me mostly, I'm sending these patches
as-is, I'd like to get the GPU side merged, and hopefully provoke
some action from the Intel audio people, otherwise I guess I get to
ship these in Fedora/RHEL and everyone else can do what they like.
Dave.
On Wed, May 20, 2015 at 8:39 PM, Shobhit Kumar wrote:
> On Thu, May 7, 2015 at 12:49 PM, Shobhit Kumar wrote:
>> On Wed, May 6, 2015 at 5:44 PM, Thierry Reding
>> wrote:
>>> On Tue, May 05, 2015 at 03:08:36PM +0530, Shobhit Kumar wrote:
The Crystalcove PMIC controls PWM signals and this dr
2001-01-02 4:58 GMT-02:00 Paulo Zanoni :
> From: Paulo Zanoni
>
> Release early, release often!
>
> So patch 1 is not really FBC locking but it's another trivial patch from
> December which I wanted to stop carrying around.
>
> Patches 2 and 3 are the real locking thing. I know they could have bee
From: Paulo Zanoni
We first set the threshold value when we're allocating the CFB, and
then later at {ilk,gen7}_fbc_enable() we increment it in case we're
using 16bpp. While that is correct, it is dangerous: if we rework the
code a little bit in a way that allows us to call intel_fbc_enable()
wit
From: Paulo Zanoni
Release early, release often!
So patch 1 is not really FBC locking but it's another trivial patch from
December which I wanted to stop carrying around.
Patches 2 and 3 are the real locking thing. I know they could have been just a
single patch, but I decided to split them for
From: Paulo Zanoni
We now have dev_priv->fbc.lock and it should be enough to protect
everything related to FBC.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 --
drivers/gpu/drm/i915/intel_display.c | 18 ++
drivers/gpu/drm/i915/intel_drv.h |
From: Paulo Zanoni
Make sure we're not gonna have weird races in really weird cases where
a lot of different CRTCs are doing rendering and modesets at the same
time.
v2:
- Rebase (6 months later)
- Also lock debugfs and stolen.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debug
On Mon, Jun 08, 2015 at 06:59:38AM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 06-06-15 om 00:08 schreef Matt Roper:
> > We need to call drm_atomic_set_mode_for_crtc() rather than copying the
> > mode in manually. As of commit
> >
> > commit 99cf4a29fa24461bbfe22125967188a18383eb5c
> >
Jesse-Daniel:
Can you take a look at this and let us know your thoughts please?
Thanks.
Annie Matheson
Intel Corporation
Phone: (503) 712-0586
Email: annie.j.mathe...@intel.com
-Original Message-
From: Sharma, Shashank
Sent: Monday, June 15, 2015 8:12 PM
To: Matheson, Annie J; Daniel
On Tue, 16.06.15 12:37, Chris Wilson (ch...@chris-wilson.co.uk) wrote:
> On Tue, Jun 16, 2015 at 01:17:29PM +0200, Lennart Poettering wrote:
> > On Tue, 16.06.15 10:14, Chris Wilson (ch...@chris-wilson.co.uk) wrote:
> >
> > > The biggest change here is 4.1 stopped forcing the probe from sysfs
> >
On Tue, 16.06.15 13:47, Daniel Vetter (dan...@ffwll.ch) wrote:
> > But what does that actually mean? should logind ever echo "detect"
> > itself into the file? Should it follow uevents for the files? How
> > should treat this file?
>
> Ok here's how this is supposed to work:
> - If anything chang
On Tue, 16.06.15 12:25, Daniel Vetter (dan...@ffwll.ch) wrote:
> > The biggest change here is 4.1 stopped forcing the probe from sysfs
> > precisely because systemd was hitting them so often for illogical
> > reasons (being docked depends on having the lid open and an
> > external display connecte
On Tue, Jun 16, 2015 at 08:25:25PM +0100, Arun Siluvery wrote:
> v3: Length defined in current definitions of LRM, LRR instructions is not
> correct.
> Correct and use existing definitions and also move them out of command parser
> placeholder to appropriate place.
Not that it wasn't correct. Com
On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
> + /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
> + if (IS_BROADWELL(ring->dev)) {
> + struct drm_i915_private *dev_priv = ring->dev->dev_private;
dev_priv = to_i915(ring->dev);
> +
> + cmd[ind
On Tue, Jun 16, 2015 at 08:25:24PM +0100, Arun Siluvery wrote:
> @@ -1085,6 +1085,8 @@ static int gen8_init_indirectctx_bb(struct
> intel_engine_cs *ring,
> uint32_t index;
> struct page *page;
> uint32_t *cmd;
> + u32 scratch_addr;
> + unsigned long flags = 0;
flags can
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
> +static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
> +{
> + int ret;
> + struct drm_device *dev = ring->dev;
You only use it once, keeping it as a local seems counter-intuitive.
> + WARN_ON(ring->id
On Tue, Jun 16, 2015 at 08:25:20PM +0100, Arun Siluvery wrote:
> +static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
> + uint32_t offset,
> + uint32_t *num_dwords)
> +{
> + uint32_t index;
> + struct page *page;
On 16/06/2015 18:10, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 04:39:23PM +0300, Mika Kuoppala wrote:
In order for skl+ hardware to guarantee that no context switch
takes place during reset and that current context is properly
saved, the driver needs to notify and query hw before commencing
wi
On 16/06/2015 14:39, Mika Kuoppala wrote:
In order for skl+ hardware to guarantee that no context switch
takes place during reset and that current context is properly
saved, the driver needs to notify and query hw before commencing
with reset.
We will only proceed with reset if all engines repor
On Tue, Jun 16, 2015 at 06:32:22PM +0100, Tomas Elf wrote:
> On 16/06/2015 17:55, Chris Wilson wrote:
> >On Tue, Jun 16, 2015 at 04:43:55PM +0100, Tomas Elf wrote:
> >>On 16/06/2015 14:43, Daniel Vetter wrote:
> >>>On Mon, Jun 08, 2015 at 06:03:20PM +0100, Tomas Elf wrote:
> The TDR ULT used to
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 19 +
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw
v2: Add LRI commands to set/reset bit that invalidates coherent lines,
update WA to include programming restrictions and exclude CHV as
it is not required (Ville)
Signed-off-by: Rafael Barbalho
Signed-off-by: A
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
be applied using normal means. Each context has two registers to l
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break any future users of existing definitions (Michel)
v3: Length defined in current def
From Gen8+ we have some workarounds that are applied Per context and
they are applied using special batch buffers called as WA batch buffers.
HW executes them at specific stages during context save/restore.
The patches in this series adds this framework to i915.
I did some basic testing on BDW by
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.
Signed-off-by: Michel Thierry
Signed-off-by: Aru
On 06/16/2015 05:26 AM, Paulo Zanoni wrote:
> 2015-06-16 9:23 GMT-03:00 Paulo Zanoni :
>> 2015-06-16 5:34 GMT-03:00 Daniel Vetter :
>>> Can I get an ack on this please? The audio folks already move ahead
>>>
>>> http://permalink.gmane.org/gmane.linux.alsa.devel/139831
>>>
>>> Would be embarassing i
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
This is my first post to a mailing list... I hope it works out. I
couldn't find more details on how to do it.
I'm getting the same error message as described in the original post,
expect for the register (address?). As proposed in the dmesg output I
On 16/06/2015 17:55, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 04:43:55PM +0100, Tomas Elf wrote:
On 16/06/2015 14:43, Daniel Vetter wrote:
On Mon, Jun 08, 2015 at 06:03:20PM +0100, Tomas Elf wrote:
The TDR ULT used to validate this patch series requires a special uevent for
full GPU resets
On Tue, Jun 16, 2015 at 04:39:23PM +0300, Mika Kuoppala wrote:
> In order for skl+ hardware to guarantee that no context switch
> takes place during reset and that current context is properly
> saved, the driver needs to notify and query hw before commencing
> with reset.
>
> We will only proceed
On 6/15/2015 4:00 PM, Daniel Vetter wrote:
On Mon, Jun 01, 2015 at 02:03:15PM +0300, Ville Syrjälä wrote:
On Fri, May 29, 2015 at 07:10:53PM +0200, Daniel Vetter wrote:
On Fri, May 29, 2015 at 01:59:01PM +0300, Ville Syrjälä wrote:
On Fri, May 29, 2015 at 04:06:53PM +0530, Gaurav K Singh wro
On 16/06/2015 17:50, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 04:46:05PM +0100, Tomas Elf wrote:
On 16/06/2015 14:44, Daniel Vetter wrote:
On Mon, Jun 08, 2015 at 06:03:19PM +0100, Tomas Elf wrote:
When submitting semaphores in execlist mode the hang checker crashes in this
function because
On 6/15/2015 4:03 PM, Daniel Vetter wrote:
On Sat, Jun 13, 2015 at 12:24:57PM +0530, Mohan Marimuthu, Yogesh wrote:
On 5/29/2015 10:51 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:07:03PM +0530, Gaurav K Singh wrote:
During enable sequence for MIPI encoder in command mode, enable
MIP
On 5/29/2015 10:50 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 07:16:36PM +0200, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:06:59PM +0530, Gaurav K Singh wrote:
During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Si
On 5/29/2015 10:53 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 07:14:43PM +0200, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:06:58PM +0530, Gaurav K Singh wrote:
vblank interrupt should be disabled before starting the disable
sequence for MIPI command mode. Otherwise when pipe is dis
On Tue, Jun 16, 2015 at 04:43:55PM +0100, Tomas Elf wrote:
> On 16/06/2015 14:43, Daniel Vetter wrote:
> >On Mon, Jun 08, 2015 at 06:03:20PM +0100, Tomas Elf wrote:
> >>The TDR ULT used to validate this patch series requires a special uevent for
> >>full GPU resets in order to distinguish between d
On Tue, Jun 16, 2015 at 04:46:05PM +0100, Tomas Elf wrote:
> On 16/06/2015 14:44, Daniel Vetter wrote:
> >On Mon, Jun 08, 2015 at 06:03:19PM +0100, Tomas Elf wrote:
> >>When submitting semaphores in execlist mode the hang checker crashes in this
> >>function because it is only runnable in ring subm
On Tue, Jun 16, 2015 at 06:21:53PM +0200, Daniel Vetter wrote:
> On Tue, Jun 16, 2015 at 01:10:33PM +0100, Chris Wilson wrote:
> > On Mon, Jun 15, 2015 at 06:34:51PM +0200, Daniel Vetter wrote:
> > > On Thu, Jun 11, 2015 at 09:01:08PM +0100, Chris Wilson wrote:
> > > > On Thu, Jun 11, 2015 at 07:14
On Tue, Jun 16, 2015 at 01:10:33PM +0100, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 06:34:51PM +0200, Daniel Vetter wrote:
> > On Thu, Jun 11, 2015 at 09:01:08PM +0100, Chris Wilson wrote:
> > > On Thu, Jun 11, 2015 at 07:14:28PM +0300, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From:
On Tue, Jun 16, 2015 at 04:10:19PM +0100, Tvrtko Ursulin wrote:
>
>
> On 06/16/2015 02:53 PM, Chris Wilson wrote:
> >On Tue, Jun 16, 2015 at 02:32:40PM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 06/16/2015 12:48 PM, Chris Wilson wrote:
> >>>On Tue, Jun 16, 2015 at 12:31:23PM +0100, Tvrtko Ursulin w
On 16/06/2015 14:49, Daniel Vetter wrote:
On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
In preparation for per-engine reset add way for setting context reset stats.
OPEN QUESTIONS:
1. How do we deal with get_reset_stats and the GL robustness interface when
introducing per-engine re
On Tue, Jun 16, 2015 at 02:54:49PM +0100, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 03:48:09PM +0200, Daniel Vetter wrote:
> > On Mon, Jun 08, 2015 at 06:33:59PM +0100, Chris Wilson wrote:
> > > On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
> > > > In preparation for per-engine res
On 16/06/2015 14:44, Daniel Vetter wrote:
On Mon, Jun 08, 2015 at 06:03:19PM +0100, Tomas Elf wrote:
When submitting semaphores in execlist mode the hang checker crashes in this
function because it is only runnable in ring submission mode. The reason this
is of particular interest to the TDR pat
On 16/06/2015 14:43, Daniel Vetter wrote:
On Mon, Jun 08, 2015 at 06:03:20PM +0100, Tomas Elf wrote:
The TDR ULT used to validate this patch series requires a special uevent for
full GPU resets in order to distinguish between different kinds of resets.
Signed-off-by: Tomas Elf
Why duplicate
On 06/16/2015 02:53 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 02:32:40PM +0100, Tvrtko Ursulin wrote:
On 06/16/2015 12:48 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 12:31:23PM +0100, Tvrtko Ursulin wrote:
That is partially correct, I do see it as problematic since I
assumed someo
On Tue, Jun 16, 2015 at 04:39:23PM +0300, Mika Kuoppala wrote:
> In order for skl+ hardware to guarantee that no context switch
> takes place during reset and that current context is properly
> saved, the driver needs to notify and query hw before commencing
> with reset.
>
> We will only proceed
On Tue, Jun 16, 2015 at 02:45:39PM +0100, Dave Gordon wrote:
> On 15/06/15 11:53, Chris Wilson wrote:
> > On Mon, Jun 15, 2015 at 11:33:37AM +0100, Dave Gordon wrote:
> >> On 13/06/15 09:28, Chris Wilson wrote:
> >>> On Fri, Jun 12, 2015 at 06:30:56PM -0300, Paulo Zanoni wrote:
> From: Paulo Z
On Tue, Jun 16, 2015 at 03:48:09PM +0200, Daniel Vetter wrote:
> On Mon, Jun 08, 2015 at 06:33:59PM +0100, Chris Wilson wrote:
> > On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
> > > In preparation for per-engine reset add way for setting context reset
> > > stats.
> > >
> > > OPEN Q
On Tue, Jun 16, 2015 at 02:32:40PM +0100, Tvrtko Ursulin wrote:
>
> On 06/16/2015 12:48 PM, Chris Wilson wrote:
> >On Tue, Jun 16, 2015 at 12:31:23PM +0100, Tvrtko Ursulin wrote:
> >>That is partially correct, I do see it as problematic since I
> >>assumed someone will modeset with this fb/object
On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
> In preparation for per-engine reset add way for setting context reset stats.
>
> OPEN QUESTIONS:
> 1. How do we deal with get_reset_stats and the GL robustness interface when
> introducing per-engine resets?
>
> a. Do we set conte
On Tue, Jun 16, 2015 at 03:40:16PM +0200, Daniel Vetter wrote:
> On Mon, Jun 15, 2015 at 09:03:09PM +, Konduru, Chandra wrote:
> > > >
> > > > Cdclk < crtc_clock is not allowed and suggests a different problem
> > > > elsewhere.
> > > >
> > > > It is more robust and safe to assume no scaling i
On Mon, Jun 08, 2015 at 06:33:59PM +0100, Chris Wilson wrote:
> On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
> > In preparation for per-engine reset add way for setting context reset stats.
> >
> > OPEN QUESTIONS:
> > 1. How do we deal with get_reset_stats and the GL robustness inter
On 15/06/15 11:53, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 11:33:37AM +0100, Dave Gordon wrote:
>> On 13/06/15 09:28, Chris Wilson wrote:
>>> On Fri, Jun 12, 2015 at 06:30:56PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni
We tried to fix this in the following commit:
>>>
On Mon, Jun 08, 2015 at 06:03:19PM +0100, Tomas Elf wrote:
> When submitting semaphores in execlist mode the hang checker crashes in this
> function because it is only runnable in ring submission mode. The reason this
> is of particular interest to the TDR patch series is because we use semaphores
On Mon, Jun 08, 2015 at 06:03:20PM +0100, Tomas Elf wrote:
> The TDR ULT used to validate this patch series requires a special uevent for
> full GPU resets in order to distinguish between different kinds of resets.
>
> Signed-off-by: Tomas Elf
Why duplicate the uevent we send out from i915_reset
In order for skl+ hardware to guarantee that no context switch
takes place during reset and that current context is properly
saved, the driver needs to notify and query hw before commencing
with reset.
We will only proceed with reset if all engines report that they
are ready for reset.
As we skip
On Mon, Jun 15, 2015 at 09:03:09PM +, Konduru, Chandra wrote:
> > >
> > > Cdclk < crtc_clock is not allowed and suggests a different problem
> > > elsewhere.
> > >
> > > It is more robust and safe to assume no scaling is possible in this case.
> > >
> > > Signed-off-by: Tvrtko Ursulin
> > > C
From: Tvrtko Ursulin
These are the display call sites so should use the proper helper.
Also requires intel_plane_obj_offset to assume normal view when
plane pointer is not available.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 6 --
drivers/gpu/drm/i915/intel_
From: Tvrtko Ursulin
There is no need to "recompute" it every time since it is guaranteed
to be static for the lifetime of a frame buffer being assigned to a
plane for display purposes.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 17 +++--
drivers/gpu/d
From: Tvrtko Ursulin
We don't need the plane but just it's state and so it will be more
handy to pass it in directly.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 13 +++--
drivers/gpu/drm/i915/intel_drv.h | 6 --
drivers/gpu/drm/i915/intel_sprite.c
On 06/16/2015 12:48 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 12:31:23PM +0100, Tvrtko Ursulin wrote:
That is partially correct, I do see it as problematic since I
assumed someone will modeset with this fb/object at some point, and
there will be state available then, which won't have the
On Tue, 16 Jun 2015, Jani Nikula wrote:
> On Wed, 03 Jun 2015, Mika Kahola wrote:
>> From: Ville Syrjälä
>>
>> Add support for changing cdclk frequency during runtime on BDW. The
>> procedure is quite a bit different on BDW from the one on HSW, so
>> add a separate function for it.
>>
>> Also wi
On Wed, 03 Jun 2015, Mika Kahola wrote:
> From: Ville Syrjälä
>
> Add support for changing cdclk frequency during runtime on BDW. The
> procedure is quite a bit different on BDW from the one on HSW, so
> add a separate function for it.
>
> Also with IPS enabled the actual pixel rate mustn't excee
This will let userspace know whether Resource Streamer is supported
in the kernel.
v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
I915_PARAM_HAS_GPU_RESET.
v3: Only advertise RS support for hardware that supports it.
Suggested-by: Kenneth Graunke
Cc: Kenneth Graunke
Signed-off-by
On 06/16/2015 12:40 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 10:26:40AM +0100, Tvrtko Ursulin wrote:
On 06/15/2015 07:36 PM, Dave Gordon wrote:
From: Alex Dai
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
2015-06-16 9:23 GMT-03:00 Paulo Zanoni :
> 2015-06-16 5:34 GMT-03:00 Daniel Vetter :
>> Can I get an ack on this please? The audio folks already move ahead
>>
>> http://permalink.gmane.org/gmane.linux.alsa.devel/139831
>>
>> Would be embarassing if we are late to the party we organized ourselves ..
On Tue, Jun 16, 2015 at 02:18:55PM +0200, Daniel Vetter wrote:
> Maybe someone should look at per-buffer locks before trying to split up
> the low-level hw locks ;-)
Per-vm then per-buffer. Adding more locked operations to execbuf is
scary though, with some workloads perf highlights the cost of th
2015-06-16 5:34 GMT-03:00 Daniel Vetter :
> Can I get an ack on this please? The audio folks already move ahead
>
> http://permalink.gmane.org/gmane.linux.alsa.devel/139831
>
> Would be embarassing if we are late to the party we organized ourselves ...
The situation is already embarassing for us :
On Tue, Jun 16, 2015 at 03:02:58PM +0300, Abdiel Janulgue wrote:
> This will let userspace know whether Resource Streamer is supported
> in the kernel.
>
> v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
> I915_PARAM_HAS_GPU_RESET.
>
> Suggested-by: Kenneth Graunke
> Cc: Kenneth Gr
On Tue, Jun 16, 2015 at 12:03:45PM +0100, Dave Gordon wrote:
> On 15/06/15 21:41, Chris Wilson wrote:
> > On Mon, Jun 15, 2015 at 07:11:37PM +0100, Dave Gordon wrote:
> >>> It still applies. If you submit say 1024 interrupted execbuffers they
> >>
> >> What is an interrupted execbuffer? AFAICT we h
On Mon, Jun 15, 2015 at 06:34:51PM +0200, Daniel Vetter wrote:
> On Thu, Jun 11, 2015 at 09:01:08PM +0100, Chris Wilson wrote:
> > On Thu, Jun 11, 2015 at 07:14:28PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > When the GPU gets reset __i915_wait_request(
This will let userspace know whether Resource Streamer is supported
in the kernel.
v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
I915_PARAM_HAS_GPU_RESET.
Suggested-by: Kenneth Graunke
Cc: Kenneth Graunke
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_dma.c | 3 +
On Mon, Jun 15, 2015 at 05:28:20PM -0500, Micah Fedke wrote:
> ---
Commit message must be above the --- line, otherwise it gets cut off. Also
we tend to follow the signe-off-by procedures as documented in
http://developercertificate.org/
> A second swing at non-intel GPU support in igt. This pa
On Tue, Jun 16, 2015 at 12:31:23PM +0100, Tvrtko Ursulin wrote:
>
> On 06/16/2015 12:22 PM, Chris Wilson wrote:
> >On Tue, Jun 16, 2015 at 12:18:49PM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 06/16/2015 12:02 PM, Chris Wilson wrote:
> >>>On Tue, Jun 16, 2015 at 11:17:11AM +0100, Tvrtko Ursulin wrot
On Tue, Jun 16, 2015 at 01:22:00PM +0200, Lennart Poettering wrote:
> B1;4002;0cOn Tue, 16.06.15 12:25, Daniel Vetter (dan...@ffwll.ch) wrote:
>
> > > The biggest change here is 4.1 stopped forcing the probe from sysfs
> > > precisely because systemd was hitting them so often for illogical
> > > r
On Mon, Jun 15, 2015 at 07:36:27PM +0100, Dave Gordon wrote:
> + if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
> + PIN_OFFSET_BIAS | GUC_WOPCM_SIZE_VALUE)) {
> + drm_gem_object_unreference(&obj->base);
> + return NULL;
> + }
Another question is shoul
On Tue, Jun 16, 2015 at 10:26:40AM +0100, Tvrtko Ursulin wrote:
>
> On 06/15/2015 07:36 PM, Dave Gordon wrote:
> >From: Alex Dai
> >
> >Allocate a GEM object to hold GuC log data. A debugfs interface
> >(i915_guc_log_dump) is provided to print out the log content.
> >
> >Issue: VIZ-4884
> >Signed
On Tue, Jun 16, 2015 at 01:17:29PM +0200, Lennart Poettering wrote:
> On Tue, 16.06.15 10:14, Chris Wilson (ch...@chris-wilson.co.uk) wrote:
>
> > The biggest change here is 4.1 stopped forcing the probe from sysfs
> > precisely because systemd was hitting them so often for illogical
> > reasons (
On 06/16/2015 12:22 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 12:18:49PM +0100, Tvrtko Ursulin wrote:
On 06/16/2015 12:02 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 11:17:11AM +0100, Tvrtko Ursulin wrote:
On 05/28/2015 03:09 PM, Daniel Vetter wrote:
On Thu, May 28, 2015 at 01:36
Convert 'broadwell_modeset_global_pipes()' into atomic
mode setting.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/inte
Max CD clock for Broadwell platform is added to
'intel_mode_max_pixclk()' function. This patch
removes the need for 'ilk_max_pixel_rate()' function.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 45 +++-
1 file changed, 14 insertions(+), 31
This patch series add support for atomic mode setting
for Broadwell platform. In addition, the max CD clock
computation is unified into one function 'intel_mode_max_pixclk()'.
The modeset for global pipes is proposed to be computed
in a single function 'intel_modeset_global_pipes()'
Mika Kahola (
Combine global pipe modesetting for Valleyview,
Broxton, and Broadwell. This removes some of the
repetitive code that exists in routines
'valleyview_modeset_global_pipes()' and
'broadwell_modeset_global_pipes()'. The naming
changed to 'intel_modeset_global_pipes()'.
Signed-off-by: Mika Kahola
---
On Tue, Jun 16, 2015 at 12:18:49PM +0100, Tvrtko Ursulin wrote:
>
> On 06/16/2015 12:02 PM, Chris Wilson wrote:
> >On Tue, Jun 16, 2015 at 11:17:11AM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 05/28/2015 03:09 PM, Daniel Vetter wrote:
> >>>On Thu, May 28, 2015 at 01:36:54PM +0100, Chris Wilson wrote
B1;4002;0cOn Tue, 16.06.15 12:25, Daniel Vetter (dan...@ffwll.ch) wrote:
> > The biggest change here is 4.1 stopped forcing the probe from sysfs
> > precisely because systemd was hitting them so often for illogical
> > reasons (being docked depends on having the lid open and an
> > external displa
On 06/16/2015 12:02 PM, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 11:17:11AM +0100, Tvrtko Ursulin wrote:
On 05/28/2015 03:09 PM, Daniel Vetter wrote:
On Thu, May 28, 2015 at 01:36:54PM +0100, Chris Wilson wrote:
On Thu, May 28, 2015 at 02:24:40PM +0200, Daniel Vetter wrote:
On Thu, May 2
On Tue, 16.06.15 10:14, Chris Wilson (ch...@chris-wilson.co.uk) wrote:
> The biggest change here is 4.1 stopped forcing the probe from sysfs
> precisely because systemd was hitting them so often for illogical
> reasons (being docked depends on having the lid open and an
> external display connecte
On Tue, Jun 16, 2015 at 12:02:00PM +0100, Chris Wilson wrote:
> fbdev is a little special. All that we actually require is a plain
> ggtt_pin to ensure that the fb is still around for panics. We can leave
> the plane state in modesetting. We have have full control over the
> struct we associated wi
On 15/06/15 21:41, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:11:37PM +0100, Dave Gordon wrote:
>>> It still applies. If you submit say 1024 interrupted execbuffers they
>>
>> What is an interrupted execbuffer? AFAICT we hold the struct_mutex while
>> stuffing the ringbuffer so we can only ev
On Tue, Jun 16, 2015 at 11:17:11AM +0100, Tvrtko Ursulin wrote:
>
> On 05/28/2015 03:09 PM, Daniel Vetter wrote:
> >On Thu, May 28, 2015 at 01:36:54PM +0100, Chris Wilson wrote:
> >>On Thu, May 28, 2015 at 02:24:40PM +0200, Daniel Vetter wrote:
> >>>On Thu, May 28, 2015 at 09:58:30AM +0100, Tvrtko
On Tue, 2015-06-16 at 10:34 +0200, Daniel Vetter wrote:
> Can I get an ack on this please? The audio folks already move ahead
>
> http://permalink.gmane.org/gmane.linux.alsa.devel/139831
>
> Would be embarassing if we are late to the party we organized ourselves ...
> -Daniel
>
>
Mengdong, Lib
Ensures that the batch buffer is executed by the resource streamer
v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
Testcase: igt/gem_exec_params
Cc: Jani Nikula
Reviewed-by: Chris Wilson
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++
i
This will let userspace know whether Resource Streamer is supported
in the kernel.
Suggested-by: Kenneth Graunke
Cc: Kenneth Graunke
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a
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