+Ben.
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
and use it to initialize the align variable in drm_intel_bo.
In case of YF/YS tiled buffers libdrm need not know about the tiling
format because these buffers don't have hardware support to be tiled
or detiled
+Ben
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index
On Wed, Jun 10, 2015 at 1:47 AM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Tue, Jun 09, 2015 at 02:59:33PM -0700, Anuj Phogat wrote:
This patch is on the list for 8 weeks now. Please take a look so I can push
it upstream.
Could I suggest you nominate a mesa team member working on SKL
On Mon, Jun 15, 2015 at 12:33:37PM +0200, Maarten Lankhorst wrote:
Requisites:
- [PATCH] drm/atomic: pass old crtc state to atomic_begin/flush.
This patch series converts plane updates and cdclk updates to atomic,
but still doesn't touch the hw readout code, which was regressing a lot.
On Thu, Jun 18, 2015 at 8:43 PM, Rodrigo Vivi rodrigo.v...@intel.com wrote:
By Spec we should just mask memup and hotplug detection
for hardware tracking cases. However we always masked
LPSP that is for low power tracking support because
without it PSR was constantly exiting and never really
On Mon, Jun 08, 2015 at 05:58:23PM -0700, Matt Roper wrote:
On Sat, Jun 06, 2015 at 05:34:45PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 6/6/2015 6:31 AM, Matt Roper wrote:
On Thu, Jun 04, 2015 at 07:12:37PM +0530, Kausal Malladi wrote:
From: Kausal Malladi
On Fri, Jun 19, 2015 at 1:32 PM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Thu, Jun 18, 2015 at 8:43 PM, Rodrigo Vivi rodrigo.v...@intel.com wrote:
By Spec we should just mask memup and hotplug detection
for hardware tracking cases. However we always masked
LPSP that is for low power
Hi,
Please consider pulling i915 to linux-firmware.git and let me know if
there is anything else I should do differently on the pull request.
Besides what I had requested already there is a new minor version of dmc
available.
Thanks in advance,
Rodrigo.
The following changes since commit
On Thu, 2015-06-18 at 16:50 +0100, Damien Lespiau wrote:
On Thu, Jun 18, 2015 at 03:45:44PM +0100, Antoine, Peter wrote:
Not a blocker. It gets a little more interesting, as the L3CC
registers are shared across all engines, but is only saved in the RCS
context. But, it is reset on the
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Jani Nikula
On Wed, 17 Jun 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jun 17, 2015 at 02:01:57PM +1000, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
Hi Paul,
On Fri, Jun 19, 2015 at 12:11 AM, Paul Bolle pebo...@tiscali.nl wrote:
Hi Shobhit,
On Thu, 2015-06-18 at 23:24 +0530, Shobhit Kumar wrote:
On Fri, May 1, 2015 at 2:42 AM, Paul Bolle pebo...@tiscali.nl wrote:
On Wed, 2015-04-29 at 19:30 +0530, Shobhit Kumar wrote:
---
Internal requirement for the alignment is that it must be a
power-of-two, so enforce rejection at the user interface to execbuffer
(which allows the caller to specify a stricter-than-expected alignment
criterion).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
On 16/06/15 10:40, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:24PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
The new node provides access to the status of the common uC loader
code and the GuC-specific loader; also the scratch registers used
for communicatio between
On Thu, Jun 18, 2015 at 07:07:46PM +0100, Dave Gordon wrote:
On 18/06/15 13:10, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
On 17/06/15 13:02, Daniel Vetter wrote:
Domain handling is required for all gem objects, and the resulting bugs if
you don't for
On 18/06/15 15:49, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 01:11:34PM +0100, Dave Gordon wrote:
On 17/06/15 13:05, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
Current devices may contain one or more programmable microcontrollers
that need to have a
On Thu, Jun 18, 2015 at 06:33:29PM +0100, Arun Siluvery wrote:
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break any future
On 19 June 2015 at 19:54, Lin, Mengdong mengdong@intel.com wrote:
Hi Takashi/Dave,
Shall we move or cc this discussion on audio driver side to ALSA ML?
Oops I thought I had cc'ed these patches to alsa-devel as well when I sent them.
I think we also need to decide how to manage PCM
On Mon, Jun 15, 2015 at 05:18:40PM +0200, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 02:37:58PM +0100, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 03:03:39PM +0200, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 01:35:21PM +0100, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 02:29:28PM
On older gen, pre-Ironlake, parts there is no hardwired pin to report
the presence of an LVDS panel. Instead, we have to rely on the VBT to
declare whether the machine has a panel or not. Though notoriously
unreliable, so far we have erred on the side of false-positives and have
required a list of
Exclude active GPU pages from the purview of the background shrinker
(kswapd), as these cause uncontrollable GPU stalls. Given that the
shrinker is rerun until the freelists are satisfied, we should have
opportunity in subsequent passes to recover the pages once idle. If the
machine does run out
On Fri, Jun 19, 2015 at 10:52:15AM +0100, Chris Wilson wrote:
An interesting point was raised in some recent patches to document the
various widths of the register subfields. I disagreed with that patch in
that it transformed illegal values into some random potentially harmful
valid value (and
On 17/06/15 13:18, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But in the case of GuC-based
batch submission, we can't do that until any required
An interesting point was raised in some recent patches to document the
various widths of the register subfields. I disagreed with that patch in
that it transformed illegal values into some random potentially harmful
valid value (and not transforming an invalid value would end up writing
bits in
At Fri, 19 Jun 2015 20:33:39 +1000,
Dave Airlie wrote:
On 19 June 2015 at 19:54, Lin, Mengdong mengdong@intel.com wrote:
Hi Takashi/Dave,
Shall we move or cc this discussion on audio driver side to ALSA ML?
Oops I thought I had cc'ed these patches to alsa-devel as well when I sent
This must be done in advance, and during crtc_disable all scalers
can be force disabled.
This means intel_atomic_setup_scalers is only called in 1 place now,
during crtc_check.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 14
Always read out plane state, and do an initial modeset in modeset_gem_init.
---
drivers/gpu/drm/i915/i915_dma.c | 12 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/intel_atomic.c | 7 -
Now that we read out the full atomic state we can force fastboot without hacks.
The only thing that we worry about is preventing a modeset. This can be easily
done by calculating if sw state matches hw state, with exception for pfit and
pipe size. Since the original fastboot code only touched pipe
Use for_each_crtc_state to only touch affected crtc's.
In order to make sure that the initial power is still set
correctly we make sure modeset_update_crtc_power_domains is called
during the initial modeset.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
Calculate all state using a normal transition, but afterwards fudge
crtc-state-active back to its old value. This should still allow
state restore in setup_hw_state to work properly.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 74
To make this work we load the new hardware state into the
atomic_state, then swap it with the sw state.
This lets us change the force restore path in setup_hw_state()
to use a single call to intel_mode_set() to restore all the
previous state.
As a nice bonus this kills off encoder-new_encoder,
And get rid of things that are no longer true. This function is only
used for forcing a modeset when encoder properties are changed.
All the existing state is fine in this case, only setting mode_changed
will force a full recalculation here, and take all the state needed.
Signed-off-by: Maarten
The only thing missing after part 3 is restoring atomic readout and making
suspend/restore. With fixes for all identified causes of regressions from
atomic suspend being done in convert to atomic, part 3 it's time to worry
about getting atomic suspend/restore working again.
I do this in a few
On Thu, Jun 18, 2015 at 06:33:28PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)
Ok, so this is the first use of scratch object. I would like to move the
test for existence
On 16/06/15 10:35, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
+static int i915_gem_context_first_open(struct drm_device *dev)
+{
+struct drm_i915_private *dev_priv = dev-dev_private;
+int ret;
+
+/*
+ * We can't enable contexts until
On 19/06/2015 10:27, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 06:33:24PM +0100, Arun Siluvery wrote:
Totally minor worries now.
+/**
+ * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
+ *
+ * @ring: only applicable for RCS
+ * @wa_ctx_batch: page in which WA are loaded
+
Hi,
On 19 June 2015 at 09:02, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
+ if (crtc-state-enable) {
+ intel_mode_from_pipe_config(crtc-mode,
+ to_intel_crtc_state(crtc-state));
+
On Thu, Jun 18, 2015 at 06:33:24PM +0100, Arun Siluvery wrote:
Totally minor worries now.
+/**
+ * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
+ *
+ * @ring: only applicable for RCS
+ * @wa_ctx_batch: page in which WA are loaded
+ * @offset: This is for future use in
Hi Takashi/Dave,
Shall we move or cc this discussion on audio driver side to ALSA ML?
I think we also need to decide how to manage PCM devices for DP MST.
Now the HD-A driver create a PCM device for each pin, and the substream
number is 1 for each PCM. Now with DP MST enabled, each pin can
On Fri, Jun 19, 2015 at 10:48:24AM +0100, Siluvery, Arun wrote:
variable names were getting too long and caused difficulties in
indentation so tried to shorten them, will change this part.
It's a trade off. I was thinking we wouldn't need to use the full form
that often so the extra characters
Just to fill in the info on this one.
We don't have Haswell Lenovo t440s atm, so could you share more info?
- Dell U2410 should support both HDMI and DP input. But I guess it cannot
support DP MST, right?
- Are you connecting this monitor a DP cable?
Which DDI port is used? DDI B, C or D?
On Fri, Jun 19, 2015 at 06:08:08AM +0200, Maarten Lankhorst wrote:
Op 18-06-15 om 11:25 schreef Daniel Vetter:
We use the same check already in the atomic core, so might as well
make this official. And it's also reused in e.g. i915.
Motivated by Maarten's idea to extract a
On 18/06/15 21:12, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 10:53:10AM -0700, Yu Dai wrote:
On 06/15/2015 01:30 PM, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:23PM +0100, Dave Gordon wrote:
+ /* Set the source address for the new blob */
+ offset =
On Fri, Jun 19, 2015 at 01:48:13PM +1000, Dave Airlie wrote:
On 18 June 2015 at 16:04, Jani Nikula jani.nik...@intel.com wrote:
Hi Dave, i915 fixes for drm-next/v4.2.
BR,
Jani.
And my gcc says:
/home/airlied/devel/kernel/drm-next/drivers/gpu/drm/i915/intel_display.c:
In function
On Fri, Jun 19, 2015 at 08:17:55AM +0200, Mikko Rapeli wrote:
When trying to hibernate a Lenovo T60 the half moon led keeps blinking and
devices does not power off since commit da2bc1b9db3.
T60 chip details:
00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS,
943/940GM
On Fri, 2015-06-19 at 17:44 +0200, Daniel Vetter wrote:
I wonder whether we shouldn't do this unconditionally for gen4 and earlier
for Lenovo ... Anyway this needs Cc: sta...@vger.kernel.org and is for
Jani to pick up.
Thanks for figuring out what's been broken here.
-Daniel
On 18/06/2015 14:29, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 1:21 PM, John Harrison
john.c.harri...@intel.com wrote:
I'm still confused by what you are saying in the above referenced email.
Part of it is about the sanity checks failing to handle the wrapping case
correctly which has been
We've never figured out the magic trick to make irq vs. seqno
updates coherent, only tricks to make it work. And since
commit 094f9a54e35500739da185cdb78f2e92fc379458
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Wed Sep 25 17:34:55 2013 +0100
drm/i915: Fix __wait_seqno to use true
On Thu, Jun 18, 2015 at 04:58:06PM +0200, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 12:42:55PM +0100, Chris Wilson wrote:
I understand the merit in trying the reset a few times before giving up,
it would just need a bit of restructuring to try the reset before
clearing gem state
From: John Harrison john.c.harri...@intel.com
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write
On Fri, Jun 19, 2015 at 06:43:04PM +0200, Daniel Vetter wrote:
We've never figured out the magic trick to make irq vs. seqno
updates coherent, only tricks to make it work. And since
commit 094f9a54e35500739da185cdb78f2e92fc379458
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Wed Sep
On 15/06/15 22:32, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:27PM +0100, Dave Gordon wrote:
+static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device
*dev,
+u32 size)
+{
+struct drm_i915_gem_object *obj;
+
+
From: Akash Goel akash.g...@intel.com
This patch series adds the changes for supporting the Ring frequency table
programming and retrieving the efficient frequency (aka RPe) value from the
pcode for SKL.
Addressed review comments from Ville, Daniel added r-b tag from
Rodrigo on the 3 patches
From: Akash Goel akash.g...@intel.com
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.
v2: Replaced the conditional
From: Akash Goel akash.g...@intel.com
Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL
v2: Removed the check for avoiding ring frequency programming
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)
Cc: Chris Wilson
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw
v2: Add LRI commands to set/reset bit that invalidates coherent lines,
update WA to include programming restrictions and exclude CHV as
it is not required (Ville)
v3: Avoid unnecessary read when it can be done
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
be applied using normal means. Each context has two registers to
From Gen8+ we have some workarounds that are applied Per context and
they are applied using special batch buffers called as WA batch buffers.
HW executes them at specific stages during context save/restore.
The patches in this series adds this framework to i915.
I did some basic testing on BDW by
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific
On Fri, Jun 19, 2015 at 06:37:14PM +0100, Arun Siluvery wrote:
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.
v2:
On 16/06/15 10:22, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:31PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to
On 19/06/15 18:02, Dave Gordon wrote:
On 15/06/15 22:32, Chris Wilson wrote:
[snip]
Try to keep comments to explain why rather than what. Most of the
comments here fall into the i++; // postincrement i category.
-Chris
Most of the what comments in this file are associated with accesses to
From: Akash Goel akash.g...@intel.com
Ring frequency table programming is not required on BXT. Added separate
checks to enable the programming only for SKL skip for BXT.
Issue: VIZ-5144
Signed-off-by: Akash Goel akash.g...@intel.com
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
---
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.
v2: Check for valid scratch page before
On Fri, Jun 19, 2015 at 06:37:11PM +0100, Arun Siluvery wrote:
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
be applied using normal means. Each context has two registers to
From: Akash Goel akash.g...@intel.com
Updated the i915_ring_freq_table debugfs function to add
the broxton check, so as to disallow the read of ring frequency
table for it.
Issue: VIZ-5144
Signed-off-by: Akash Goel akash.g...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file
From: Akash Goel akash.g...@intel.com
Corrected the platform checks in i915_ring_freq_table debugfs function
so as to allow the read of ring frequency table for BDW and disallow for VLV
v2: Simplified the checks to avoid the double negation (Daniel)
Issue: VIZ-5144
Signed-off-by: Akash Goel
From: Akash Goel akash.g...@intel.com
Updated the i915_ring_freq_table debugfs function to support the read
of ring frequency table, through Punit interface, for SKL also.
Issue: VIZ-5144
Signed-off-by: Akash Goel akash.g...@intel.com
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
---
On Fri, Jun 19, 2015 at 06:37:10PM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
On 15/06/15 22:55, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:29PM +0100, Dave Gordon wrote:
+/* Get valid workqueue item and return it back to offset */
+static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
+{
+struct guc_process_desc *desc;
+void
On Fri, Jun 19, 2015 at 06:37:12PM +0100, Arun Siluvery wrote:
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
On Fri, Jun 19, 2015 at 09:16:09PM +0200, Daniel Vetter wrote:
We've never figured out the magic trick to make irq vs. seqno
updates coherent, only tricks to make it work. And since
commit 094f9a54e35500739da185cdb78f2e92fc379458
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Wed Sep
Since we only support modesetting by default (disabling modesetting on
the command line prevents i915.ko from loading), having a parameter to
disable modesstting by default is superfluous, i.e. saying
CONFIG_DRM_I915_KMS=n is equivalent to CONFIG_DRM_I915=n.
Signed-off-by: Chris Wilson
Hi all,
New -testing cycle with cool stuff:
- refactoring hpd irq handlers (Jani)
- polish skl dpll code a bit (Damien)
- dynamic cdclk adjustement (Ville Mika)
- fix up 12bpc hdmi and enable it for real again (Ville)
- extend hsw cmd parser to be useful for atomic configuration (Franscico
We've never figured out the magic trick to make irq vs. seqno
updates coherent, only tricks to make it work. And since
commit 094f9a54e35500739da185cdb78f2e92fc379458
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Wed Sep 25 17:34:55 2013 +0100
drm/i915: Fix __wait_seqno to use true
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