On Thu, Jun 18, 2015 at 07:28:26PM +0100, Dave Gordon wrote:
On 18/06/15 15:31, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
On 17/06/15 13:02, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave Gordon wrote:
On 15/06/15 21:09, Chris
On Tue, Jun 23, 2015 at 10:45:51PM +0200, Daniel Vetter wrote:
Hi all,
DaveI have been discussing connector hotplug and unplugging around DP MST and
if there's one thing that's clear it's that we don't even really know where
all
the problems are. Hence first step is to figure that out. One
On Wed, Jun 24, 2015 at 08:28:13AM +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 04:44:52PM -0700, Anuj Phogat wrote:
On Mon, Jun 22, 2015 at 1:04 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Mon, Jun 22, 2015 at 09:51:08PM +0200, Daniel Vetter wrote:
On Mon, Jun 22, 2015
On 06/16/2015 03:41 PM, Abdiel Janulgue wrote:
This will let userspace know whether Resource Streamer is supported
in the kernel.
v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
I915_PARAM_HAS_GPU_RESET.
v3: Only advertise RS support for hardware that supports it.
Ping. Any
On Tue, Jun 23, 2015 at 04:44:52PM -0700, Anuj Phogat wrote:
On Mon, Jun 22, 2015 at 1:04 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Mon, Jun 22, 2015 at 09:51:08PM +0200, Daniel Vetter wrote:
On Mon, Jun 22, 2015 at 11:47:02AM -0700, Anuj Phogat wrote:
and use it to initialize
On 16/06/15 10:28, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:32PM +0100, Dave Gordon wrote:
This provides a means of reading status and counts relating
to GuC actions and submissions.
Anything that ends to ease debugging also tends to ease
postmortem error analysis...
So maybe
On Wed, Jun 24, 2015 at 09:09:03AM +0100, Chris Wilson wrote:
Akash noticed that we were recursing from the call to
intel_runtime_pm_get() inside intel_mark_busy() when we were already
waking the device (through another intel_runtime_pm_get()). In
intel_mark_busy() we know the device is awake
On Wed, Jun 24, 2015 at 10:40:02AM +0200, Daniel Vetter wrote:
On Wed, Jun 24, 2015 at 09:09:03AM +0100, Chris Wilson wrote:
Akash noticed that we were recursing from the call to
intel_runtime_pm_get() inside intel_mark_busy() when we were already
waking the device (through another
It's probably allowed to leave old_fb set to garbage when unlocking,
but to prevent undefined behavior unset it just in case.
Also crtc_state-event could be NULL on memory allocation failure,
in which case event_space is increased for no reason.
Signed-off-by: Maarten Lankhorst
This change updates the old_fb pointer only after acquiring the plane lock,
if there are no properties the fb cannot have been changed either, so
this works out correctly.
Found in a discussion with Rob Clark.
Cc: Rob Clark robdcl...@gmail.com
Signed-off-by: Maarten Lankhorst
Akash noticed that we were recursing from the call to
intel_runtime_pm_get() inside intel_mark_busy() when we were already
waking the device (through another intel_runtime_pm_get()). In
intel_mark_busy() we know the device is awake and purpose of the
reference here is to simply keep the device
On ti, 2015-06-23 at 12:57 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Currently object size is returned for the rotated VMA size which can be
bigger than the rotated view itself. Since the binding code pads all
excess size with scratch pages the only minor
On ke, 2015-06-24 at 09:55 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It is only used in logging and it doesn't need to exist on its own.
Also it was misleading to log view size as object size.
v2: Improve commit message. (Joonas Lahtinen)
Reviewed-by:
On Wed, Jun 24, 2015 at 08:44:47AM +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 10:45:51PM +0200, Daniel Vetter wrote:
Hi all,
DaveI have been discussing connector hotplug and unplugging around DP MST
and
if there's one thing that's clear it's that we don't even really know
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It is only used in logging and it doesn't need to exist on its own.
Also it was misleading to log view size as object size.
v2: Improve commit message. (Joonas Lahtinen)
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Joonas Lahtinen
On Wed, Jun 24, 2015 at 08:41:02AM +0100, Dave Gordon wrote:
On 15/06/15 21:20, Chris Wilson wrote:
+ struct ida ctx_ids;
+ uint32_t log_flags;
+ int db_cacheline;
+ DECLARE_BITMAP(doorbell_bitmap, I915_MAX_DOORBELLS);
+
+ /* Action status statistics */
+ uint64_t
On ti, 2015-06-23 at 12:57 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This way data is available as soon as the view is passed into the call chain.
v2: Store size in bytes instead of pages under the appropriate name. (Chris
Wilson)
Reviewed-by: Joonas
On 15/06/15 21:20, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
intel_guc_api.h contains the subset of the GuC interface that we
will need for submission of commands through the GuC. These MUST
be kept in sync with the
On Tue, Jun 23, 2015 at 11:18:05PM +0200, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 10:30:36AM +0100, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 11:23:17AM +0200, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 10:00:51AM +0100, Chris Wilson wrote:
On Thu, Jun 18, 2015 at 10:30:23AM
On Tue, Jun 23, 2015 at 10:46:00PM +0200, Daniel Vetter wrote:
Now that dp mst hotplug takes all locks we can amend the locking rules
for the iterators. This is needed before we can roll these out in the
atomic code to avoid getting burried in WARNINGs.
Signed-off-by: Daniel Vetter
On Wed, Jun 24, 2015 at 10:40:02AM +0200, Daniel Vetter wrote:
On Wed, Jun 24, 2015 at 09:09:03AM +0100, Chris Wilson wrote:
Akash noticed that we were recursing from the call to
intel_runtime_pm_get() inside intel_mark_busy() when we were already
waking the device (through another
On ti, 2015-06-23 at 12:57 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It is only used in logging and it doesn't need to exist on its own.
Comment below.
Reviewed-by: Joonas Lahtinen joonas.lahti...@linux.intel.com
Signed-off-by: Tvrtko Ursulin
On Wed, Jun 24, 2015 at 08:57:23AM +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 10:46:00PM +0200, Daniel Vetter wrote:
Now that dp mst hotplug takes all locks we can amend the locking rules
for the iterators. This is needed before we can roll these out in the
atomic code to avoid
On 06/24/2015 08:38 AM, Joonas Lahtinen wrote:
On ti, 2015-06-23 at 12:57 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It is only used in logging and it doesn't need to exist on its own.
Comment below.
Reviewed-by: Joonas Lahtinen
On Tue, Jun 23, 2015 at 04:37:19PM -0700, Anuj Phogat wrote:
On Mon, Jun 22, 2015 at 12:49 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jun 22, 2015 at 10:21:46AM -0700, Ben Widawsky wrote:
On Fri, Jun 19, 2015 at 03:52:01PM -0700, Anuj Phogat wrote:
+Ben
On Fri, Apr 10, 2015 at
On Wed, Jun 24, 2015 at 08:33:50AM +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 04:37:19PM -0700, Anuj Phogat wrote:
On Mon, Jun 22, 2015 at 12:49 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jun 22, 2015 at 10:21:46AM -0700, Ben Widawsky wrote:
On Fri, Jun 19, 2015 at
On Tue, Jun 23, 2015 at 04:48:11PM -0700, Yu Dai wrote:
On 06/23/2015 04:33 AM, Dave Gordon wrote:
On 17/06/15 13:41, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 02:22:19PM +0200, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 09:20:44AM +0100, Dave Gordon wrote:
On 16/06/15 10:24,
On Tue, Jun 23, 2015 at 01:52:27PM +0200, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 01:05:41PM +0300, Jani Nikula wrote:
On Fri, 19 Jun 2015, Daniel Vetter daniel.vet...@ffwll.ch wrote:
We've never figured out the magic trick to make irq vs. seqno
updates coherent, only tricks to make
On ke, 2015-06-24 at 15:37 +0530, Jindal, Sonika wrote:
On 6/18/2015 7:55 PM, Imre Deak wrote:
Although we have a fixed setting for the PLL9 and EBB4 registers, it
still makes sense to check them together with the rest of PLL registers.
While at it also remove a redundant comment about
On 6/18/2015 7:55 PM, Imre Deak wrote:
This functionality will be needed by the next patch adding HW readout
support for DDI ports on BXT, so factor it out.
No functional change.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 18 ++
On Wed, Jun 24, 2015 at 01:19:10PM +0300, Imre Deak wrote:
On ke, 2015-06-24 at 15:37 +0530, Jindal, Sonika wrote:
On 6/18/2015 7:55 PM, Imre Deak wrote:
@@ -2427,8 +2431,8 @@ static void bxt_ddi_pll_enable(struct
drm_i915_private *dev_priv,
temp =
On 6/24/2015 11:29 AM, Chris Wilson wrote:
If we are in an interactive session, enable the locale. This allows for
features like setting thousand separators for printing large values. By
only enabling it for interactive terminals, we avoid changing outputs
for the test scripts (leaving them as
On Wed, Jun 24, 2015 at 01:18:48PM +0100, John Harrison wrote:
On 23/06/2015 21:00, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 04:43:24PM +0100, John Harrison wrote:
On 23/06/2015 14:24, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 12:38:01PM +0100, John Harrison wrote:
On 22/06/2015 21:12,
On 6/18/2015 7:55 PM, Imre Deak wrote:
Although we have a fixed setting for the PLL9 and EBB4 registers, it
still makes sense to check them together with the rest of PLL registers.
While at it also remove a redundant comment about 10 bit clock enabling.
Signed-off-by: Imre Deak
On Tue, Jun 23, 2015 at 01:21:28PM +0100, Michel Thierry wrote:
Changed size from u32 to u64 to support +4GB.
48-bit PPGTT test cases may need extra memory available.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
lib/igt_aux.h | 2 +-
lib/intel_os.c | 6 +++---
2 files
On ke, 2015-06-24 at 15:46 +0530, Jindal, Sonika wrote:
On 6/18/2015 7:55 PM, Imre Deak wrote:
This functionality will be needed by the next patch adding HW readout
support for DDI ports on BXT, so factor it out.
No functional change.
Signed-off-by: Imre Deak imre.d...@intel.com
On Wed, Jun 24, 2015 at 12:04:58PM +0300, Joonas Lahtinen wrote:
On ti, 2015-06-23 at 12:57 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Currently object size is returned for the rotated VMA size which can be
bigger than the rotated view itself. Since the
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: cfbcbcf86a2fe9e6841abf3ba798f62de5f14c68
commit: 3c77ff539bce5ab9fe3c5da7929d311a44919b8c [273/275] drm/i915: Remove
mostly unused variable in intel_rotate_fb_obj_pages
config: i386-randconfig-x0-06242021 (attached as
On Tue, 2015-06-23 at 10:06 +0200, Takashi Iwai wrote:
At Tue, 23 Jun 2015 07:51:22 +,
Kaskinen, Tanu wrote:
(Added pulseaudio-discuss to CC.)
On Mon, 2015-06-22 at 17:44 +0200, Takashi Iwai wrote:
At Mon, 22 Jun 2015 15:21:16 +,
Kaskinen, Tanu wrote:
On Mon,
If we are in an interactive session, enable the locale. This allows for
features like setting thousand separators for printing large values. By
only enabling it for interactive terminals, we avoid changing outputs
for the test scripts (leaving them as the C locale).
Signed-off-by: Chris Wilson
Add a new test which executes dummy workloads on the GPU. Use same
method as with gem_concurrent_{blit,all} not to interfere with
standard command line parsing.
Also adds {render,blt}-forked subtests to gem_ringfill.
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Signed-off-by: Joonas Lahtinen
On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause reprogramming of the hardware.
v2(Matt): Return 19.2 MHz when DE PLL
Looks good to me.
Reviewed-by: Sonika Jindal sonika.jin...@intel.com
On 6/18/2015 7:55 PM, Imre Deak wrote:
For the purpose of state checking we only care about the DPLL HW flags
that we actually program, so mask off the ones that we don't.
This fixes one set of DPLL state check failures.
Looks good to me:
Reviewed-by: Sonika Jindal sonika.jin...@intel.com
On 6/18/2015 7:55 PM, Imre Deak wrote:
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: cfbcbcf86a2fe9e6841abf3ba798f62de5f14c68
commit: 3c77ff539bce5ab9fe3c5da7929d311a44919b8c [273/275] drm/i915: Remove
mostly unused variable in intel_rotate_fb_obj_pages
config: i386-randconfig-x0-06241944 (attached as
On 23/06/2015 21:00, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 04:43:24PM +0100, John Harrison wrote:
On 23/06/2015 14:24, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 12:38:01PM +0100, John Harrison wrote:
On 22/06/2015 21:12, Daniel Vetter wrote:
On Fri, Jun 19, 2015 at 05:34:12PM
On Wed, Jun 24, 2015 at 01:23:48PM +0100, Tvrtko Ursulin wrote:
On 06/24/2015 01:00 PM, kbuild test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: cfbcbcf86a2fe9e6841abf3ba798f62de5f14c68
commit: 3c77ff539bce5ab9fe3c5da7929d311a44919b8c [273/275]
On Wed, 2015-06-24 at 12:41 +, Kaskinen, Tanu wrote:
On Tue, 2015-06-23 at 10:06 +0200, Takashi Iwai wrote:
At Tue, 23 Jun 2015 07:51:22 +,
Kaskinen, Tanu wrote:
(Added pulseaudio-discuss to CC.)
On Mon, 2015-06-22 at 17:44 +0200, Takashi Iwai wrote:
At Mon, 22 Jun
On Tue, Jun 23, 2015 at 07:45:42AM +0200, Sedat Dilek wrote:
I have seen this typo once and added an entry to codespell's dictionary.txt
file.
$ diff -uprN /usr/share/codespell/dictionary.txt.orig
/usr/share/codespell/dictionary.txt
--- /usr/share/codespell/dictionary.txt.orig
On Wed, Jun 24, 2015 at 02:13:08PM +0300, Joonas Lahtinen wrote:
Add a new test which executes dummy workloads on the GPU. Use same
method as with gem_concurrent_{blit,all} not to interfere with
standard command line parsing.
Planning to add a combinatorial explosion? If not just add the few
On Mon, Jun 22, 2015 at 11:35:51PM +0300, Imre Deak wrote:
Depending on the platform the port clock fed to the pipe can be the PLL's
post-divided fast clock rate or a /5 divided version of it. To make this
more obvious across the platforms calculate this port clock along with
the rest of the
On Fri, Jun 19, 2015 at 10:19:04AM +0100, Dave Gordon wrote:
On 17/06/15 13:18, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But in the case of
This patch is for I-G-T, sorry for mishap, generated in remote machine.
On ke, 2015-06-24 at 14:13 +0300, Joonas Lahtinen wrote:
Add a new test which executes dummy workloads on the GPU. Use same
method as with gem_concurrent_{blit,all} not to interfere with
standard command line parsing.
On Wed, Jun 24, 2015 at 03:49:22PM +0300, Ville Syrjälä wrote:
On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause
On Thu, Jun 18, 2015 at 07:28:26PM +0100, Dave Gordon wrote:
We don't need coherency as such. The buffer is filled (once only) by
the CPU (so I should put a set-to-cpu-domain between the allocate and
fill stages?) Once it's filled, the CPU need not read or write it ever
again.
Then before
On android platforms with 1Gb RAM gem_fence_thrash was failing
with an out of memory error.
This patch causes gem_close() to be called when a handle is
no longer required rather than relying on the cleanup when
the fd is closed. This greatly improves the memory footprint
of the test allowing it to
On Fri, Jun 19, 2015 at 09:43:11AM +0100, Dave Gordon wrote:
On 18/06/15 15:49, Daniel Vetter wrote:
On Thu, Jun 18, 2015 at 01:11:34PM +0100, Dave Gordon wrote:
On 17/06/15 13:05, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
Current devices may
Looks good to me:
Reviewed-by: Sonika Jindal sonika.jin...@intel.com
On 6/24/2015 3:49 PM, Imre Deak wrote:
On ke, 2015-06-24 at 15:37 +0530, Jindal, Sonika wrote:
On 6/18/2015 7:55 PM, Imre Deak wrote:
Although we have a fixed setting for the PLL9 and EBB4 registers, it
still makes sense
Hi all,
Ok top post on this firmware loading problem. First to note imo is that
off the over 80 request_firmware calls in drm drivers only one (outside of
i915) uses request_firmware_nowait. And none of the other have async
firmware loading implemented with their own driver. That was kinda my
On Wed, Jun 24, 2015 at 02:16:05PM +0200, Daniel Vetter wrote:
- For async gem init it's tempting to repurpose the gpu reset code with
all the existing synchronization: We'd only need to set the
RESET_IN_PROGRESS flag synchronously and then run a gpu reset after the
firmware is loaded,
On Wed, Jun 24, 2015 at 04:10:24PM -0300, Danilo Cesar Lemes de Paula wrote:
Functions, Structs and Parameters definitions on kernel documentation
are pure cosmetic, it only highlights the element.
To ease the navigation in the documentation we should use links inside
those tags so readers
2015-06-18 15:54 GMT-03:00 Paulo Zanoni przan...@gmail.com:
2015-06-18 15:43 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
With a reliable frontbuffer tracking and all instability corner cases solved
let's re-enabled PSR by default on all supported platforms.
Are we now passing all the PSR
On Wed, 2015-06-24 at 18:48 -0300, Paulo Zanoni wrote:
2015-06-18 15:54 GMT-03:00 Paulo Zanoni przan...@gmail.com:
2015-06-18 15:43 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
With a reliable frontbuffer tracking and all instability corner cases
solved
let's re-enabled PSR by default
Thank you guys!
Annie Matheson
Intel Corporation
Phone: (503) 712-0586
Email: annie.j.mathe...@intel.com
-Original Message-
From: Malladi, Kausal
Sent: Wednesday, June 24, 2015 8:41 AM
To: Roper, Matthew D; Sharma, Shashank
Cc: Matheson, Annie J; R, Dhanya p;
On 06/22/2015 11:53 PM, Daniel Vetter wrote:
On Mon, Jun 22, 2015 at 02:19:51PM -0700, Jesse Barnes wrote:
On 06/17/2015 08:10 AM, Daniel Vetter wrote:
On Wed, Jun 17, 2015 at 05:28:20PM +0300, Jani Nikula wrote:
On Wed, 17 Jun 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
Here's an idea
On Wed, 2015-06-24 at 14:06 +0100, Liam Girdwood wrote:
On Wed, 2015-06-24 at 12:41 +, Kaskinen, Tanu wrote:
On Tue, 2015-06-23 at 10:06 +0200, Takashi Iwai wrote:
At Tue, 23 Jun 2015 07:51:22 +,
Kaskinen, Tanu wrote:
(Added pulseaudio-discuss to CC.)
On Mon,
After Chris' Enable locale dependent output to a terminal patch,
we can put thousand separators into these long long outputs.
sed s/%ll/%'ll/g
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
lib/intel_os.c| 4 ++--
overlay/cpu-top.c | 2 +-
overlay/overlay.c | 4 ++--
Changed size from u32 to u64 to support +4GB.
48-bit PPGTT test cases may need extra memory available.
v2: Use thousands separator (Chris)
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
lib/igt_aux.h | 2 +-
lib/intel_os.c | 6 +++---
2
On Wed, Jun 24, 2015 at 05:41:08AM +0800, Zhi Wang wrote:
Hi Experts:
Recently we found that when i915 module got unloaded, when we were
debugging some bugs in XenGT. It would not reset HW under execlist mode.
I'm not sure if this is an issue. But if we keep loading/unloading
module
Hi Experts:
Recently we found that when i915 module got unloaded, when we were
debugging some bugs in XenGT. It would not reset HW under execlist mode.
I'm not sure if this is an issue. But if we keep loading/unloading
module with the different submission mode, e.g. from execlist mode to
On 6/11/2015 3:23 PM, Mika Kuoppala wrote:
Joonas Lahtinen joonas.lahti...@linux.intel.com writes:
On pe, 2015-05-22 at 20:04 +0300, Mika Kuoppala wrote:
Check the allocation area against the known end
of address space instead of against fixed value.
v2: Return ENODEV on internal bugs
On 6/11/2015 6:50 PM, Mika Kuoppala wrote:
When we setup page directories and tables, we point the entries
to a to the next level scratch structure. Make this generic
by introducing a fill_page_dma which maps and flushes. We also
need 32 bit variant for legacy gens.
v2: Fix flushes and handle
On 6/11/2015 5:30 PM, Mika Kuoppala wrote:
Michel Thierry michel.thie...@intel.com writes:
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Lay out scratch page structure in similar manner than other
paging structures. This allows us to use the same tools for
setup and teardown.
Signed-off-by:
Hi,
suspend/resume results in the backlight not coming back to life
on my X40 laptop with an “Display controller: Intel Corporation
82852/855GM Integrated Graphics Device”.
I bisected the issue. Apparently, commit
b0cd324faed23d10d66ba6ade66579c681feef6f introduced the problem.
Author: Jani
On Wed, Jun 24, 2015 at 02:40:31PM +0100, Michel Thierry wrote:
Changed size from u32 to u64 to support +4GB.
48-bit PPGTT test cases may need extra memory available.
v2: Use thousands separator (Chris)
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Michel Thierry
On Wed, Jun 24, 2015 at 01:23:42PM +0100, Michel Thierry wrote:
On 6/24/2015 11:29 AM, Chris Wilson wrote:
If we are in an interactive session, enable the locale. This allows for
features like setting thousand separators for printing large values. By
only enabling it for interactive terminals,
On 6/11/2015 6:50 PM, Mika Kuoppala wrote:
As there is flushing involved when we have done the cpu
write, make functions for mapping for cpu space. Make macros
to map any type of paging structure.
v2: Make it clear tha flushing kunmap is only for ppgtt (Ville)
v3: Flushing fixed (Ville,
On Saturday 20 June 2015 04:20 AM, Matt Roper wrote:
On Mon, Jun 08, 2015 at 05:58:23PM -0700, Matt Roper wrote:
On Sat, Jun 06, 2015 at 05:34:45PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 6/6/2015 6:31 AM, Matt Roper wrote:
On Thu, Jun 04, 2015 at 07:12:37PM +0530, Kausal Malladi
On 24/06/2015 13:45, Daniel Vetter wrote:
On Wed, Jun 24, 2015 at 01:18:48PM +0100, John Harrison wrote:
On 23/06/2015 21:00, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 04:43:24PM +0100, John Harrison wrote:
On 23/06/2015 14:24, Daniel Vetter wrote:
On Tue, Jun 23, 2015 at 12:38:01PM
From: John Harrison john.c.harri...@intel.com
An earlier patch was added to reserve space in the ring buffer for the
commands issued during 'add_request()'. The initial version was
pessimistic in the way it handled buffer wrapping and would cause
premature wraps and thus waste ring space.
This
From: Ville Syrjälä ville.syrj...@linux.intel.com
Try to update the watermarks on the right side of the plane update. This
is just a temporary hack until we get the proper two part update into
place. However in the meantime this might have some chance of at least
working.
Signed-off-by: Ville
From: Ville Syrjälä ville.syrj...@linux.intel.com
Read out the current watermark settings from the hardware at driver init
time. This will allow us to compare the newly calculated values against
the currrent ones and potentially avoid needless WM updates.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
So here we go again. Yet another attempt at making CHV watermarks sane.
This time we totally back to a memory latency based approach so that DDR DVFS
and PM5 can be enabled safely.
I also opted to follow the same path for VLV to avoid too much
From: Ville Syrjälä ville.syrj...@linux.intel.com
The hardware supposedly ignores the WM1 watermarks while the PND
deadline mode is enabled, but clear out the register just in case.
This is what the other OS does, and it does make register dumps look
more consistent when we don't have partial WM1
From: Ville Syrjälä ville.syrj...@linux.intel.com
Allow tweaking the VLV/CHV memory latencies thorugh sysfs, like we do
for ILK+.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++-
1 file changed, 19 insertions(+), 5
From: Ville Syrjälä ville.syrj...@linux.intel.com
Turns out the VLV/CHV system agent doesn't understand memory
latencies, so trying to rely on the PND deadline mechanism is not
going to fly especially when DDR DVFS is enabled. Currently we try to
avoid the problems by lying to the system agent
From: Ville Syrjälä ville.syrj...@linux.intel.com
Enabling PM5/DDR DVFS with multiple active pipes isn't a validated
configuration. It does seem to work most of the time at least, but
there is clearly an additional risk of underruns, so let's not play
with fire.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control
register (enable bit at least, not quite sure about the rest). So in
order to have the plane enable/disable when we want we need to first
kick the hardware out of cxsr.
From: Ville Syrjälä ville.syrj...@linux.intel.com
Let's keep the cursor control register at 0 when the cursor is disabled.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä ville.syrj...@linux.intel.com
In order to get decnet memory self refresh residency on VLV, flip it
over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS
so it's a bit simpler.
I'm not sure the currently memory latency used for CHV is really
appropriate for
From: Ville Syrjälä ville.syrj...@linux.intel.com
Consider which planes are active and compute the FIFO split based on the
relative data rates. Since we only consider the pipe src width rather
than the plane width when computing watermarks it seems best to do the
same when computing the FIFO
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently we don't have any real indication when a pipe gets
enabled/disabled. Add some.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Ville Syrjälä ville.syrj...@linux.intel.com
We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to
make sure things are really kicked off.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 5 +
1 file changed, 5
From: Ville Syrjälä ville.syrj...@linux.intel.com
Avoid some 'switch (plane-type)' by storing the fronbuffer_bits in
intel_plane.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 75 ++--
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