The Crystalcove PMIC provides three PWM signals and this driver exports
one of them on the BYT platform which is used to control backlight for
DSI panel. This is platform device implementation of the drivers/mfd
cell device for CRC PMIC.
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use the newer gpiod interface(Alexandre)
v3: Remove the redundant checks and unused code
On Thu, Jun 25, 2015 at 09:58:22AM -0700, Rodrigo Vivi wrote:
We cannot let IPS enabled with no plane on the pipe:
BSpec: IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank. and IPS must be
disabled while there is still at least one plane
On Thu, Jun 25, 2015 at 06:35:20PM +0300, Mika Kuoppala wrote:
Maintain base page handling functions in order of
alloc, free, init. No functional changes.
v2: s/Introduce/Maintain (Michel)
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Reviewed-by: Michel Thierry
On Thu, Jun 25, 2015 at 06:35:18PM +0300, Mika Kuoppala wrote:
+static int setup_scratch(struct i915_address_space *vm)
+{
+ struct i915_address_space *ggtt_vm = to_i915(vm-dev)-gtt.base;
+
+ if (i915_is_ggtt(vm))
+ return setup_scratch_ggtt(vm);
+
+ vm-scratch_page
On Thu, 28 May 2015, Rodrigo Vivi rodrigo.v...@intel.com wrote:
We cannot let IPS enabled with no plane on the pipe:
BSpec: IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank. and IPS must be
disabled while there is still at least one plane
On Fri, 26 Jun 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jun 25, 2015 at 09:58:22AM -0700, Rodrigo Vivi wrote:
We cannot let IPS enabled with no plane on the pipe:
BSpec: IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank. and IPS
On Thu, 25 Jun 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jun 25, 2015 at 06:39:30PM +0300, Mika Kuoppala wrote:
Michel Thierry michel.thie...@intel.com writes:
If for some reason [1], the page directory/table does not exist,
clear_range
would end up in an infinite while loop.
On Fri, Jun 26, 2015 at 11:22:30AM +0100, Derek Morton wrote:
gem_fenced_exec_thrash was not freeing any resources between
subtests. On 1Gb android systems this resulted in the test
failing with an OOM error.
Added cleanup code to free BOs at the end of each subtest.
Signed-off-by: Derek
On 06/26/2015 02:32 PM, Shobhit Kumar wrote:
The Crystalcove PMIC provides three PWM signals and this driver exports
one of them on the BYT platform which is used to control backlight for
DSI panel. This is platform device implementation of the drivers/mfd
cell device for CRC PMIC.
CC: Samuel
Hi Emil,
Thanks your time and suggestions.
We actually have the complete implementation ready with us, but we wanted to
know if community is agreeing to the design itself.
In fact that was our plan ahead, that if we don’t get enough comments on the
design, we will start pushing the patches.
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula jani.nik...@intel.com
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore backlight hist ctl registers
which tried to make our driver more
On to, 2015-06-25 at 14:54 -0700, Bob Paauwe wrote:
Broxton is using a different register and different bit ordering
for rps status capabilities.
Also GT perf freqency register is different for Broxton so update
that.
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
---
From: John Harrison john.c.harri...@intel.com
There is a construct in the linux kernel called 'struct fence' that is intended
to keep track of work that is executed on hardware. I.e. it solves the basic
problem that the drivers 'struct drm_i915_gem_request' is trying to address. The
request
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status should be
set on demand rather than polled. That is, there should not be a need for a
'signaled' function to be called everytime the status is queried. Instead,
'something' should
From: John Harrison john.c.harri...@intel.com
Added the '_complete' trace event which occurs when a fence/request is signaled
as complete. Also moved the notify event from the IRQ handler code to inside the
notify function itself.
For: VIZ-5190
Signed-off-by: John Harrison
From: John Harrison john.c.harri...@intel.com
The change to the implementation of i915_gem_request_completed() means that the
lazy coherency flag is no longer used. This can now be removed to simplify the
interface.
For: VIZ-5190
Signed-off-by: John Harrison john.c.harri...@intel.com
---
On Fri, Jun 26, 2015 at 01:58:11PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status should
be
set on demand rather than polled. That is, there should not be a need for a
'signaled'
On Tue, 2015-06-23 at 10:51 +0300, Tanu Kaskinen wrote:
(Added pulseaudio-discuss to CC.)
On Mon, 2015-06-22 at 17:44 +0200, Takashi Iwai wrote:
At Mon, 22 Jun 2015 15:21:16 +,
Kaskinen, Tanu wrote:
On Mon, 2015-06-22 at 14:29 +0100, Liam Girdwood wrote:
Btw, the topology
Hi Shashank,
On 25 June 2015 at 17:19, Sharma, Shashank shashank.sha...@intel.com wrote:
Gentle reminder for the review and comments.
For those who prefer having the design available with the mail, I am
attaching a PDF copy of the design document with this mail.
Perhaps I'm not hte best
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula jani.nik...@intel.com
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore backlight hist ctl registers
which tried to make our driver more
Daniel Vetter dan...@ffwll.ch writes:
On Thu, Jun 25, 2015 at 06:35:18PM +0300, Mika Kuoppala wrote:
+static int setup_scratch(struct i915_address_space *vm)
+{
+struct i915_address_space *ggtt_vm = to_i915(vm-dev)-gtt.base;
+
+if (i915_is_ggtt(vm))
+return
A safer way to update the PDPx registers is sending lri commands, added
in the ring before the batchbuffer start. Otherwise, the ctx must be idle
before trying to change anything (but the ring-tail) in the ctx image. An
example where the ctx won't be idle is lite-restore.
This patch depends on
gem_fenced_exec_thrash was not freeing any resources between
subtests. On 1Gb android systems this resulted in the test
failing with an OOM error.
Added cleanup code to free BOs at the end of each subtest.
Signed-off-by: Derek Morton derek.j.mor...@intel.com
---
tests/gem_fenced_exec_thrash.c |
On Fri, Jun 26, 2015 at 01:54:18PM +0300, Jani Nikula wrote:
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula jani.nik...@intel.com
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore
Add forking subtests to gem_ringfill. Tests cause consistent GPU
hangs on SKL.
v2: Removed noop parts.
v3:
- Allow executing the tests in order too (Chris Wilson).
- Rename the tests to -forked-1
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
101 - 126 of 126 matches
Mail list logo
