On Mon, Jun 29, 2015 at 11:50:23AM +0300, Ander Conselvan De Oliveira wrote:
On Fri, 2015-06-26 at 19:05 +0200, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 06:28:39PM +0300, Ander Conselvan De Oliveira wrote:
Hi all,
I've been looking into creating custom fields in Bugzilla to help
From: Thulasimani, Sivakumar sivakumar.thulasim...@intel.com
HPD storm is detected in intel_hpd_irq_handler and disabled for respective
port immediately but polling is enabled only in i915_hotplug_work_func and
not in i915_digport_work_func. This will result in disabled hpd never enabled
back
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Wed, 03 Jun 2015, Mika Kahola mika.kah...@intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add support for changing cdclk frequency
On Mon, 15 Jun 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Mon, Jun 15, 2015 at 02:02:23PM +0200, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 08:53:02AM +0100, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 09:44:15AM +0300, Jani Nikula wrote:
On Wed, 03 Jun 2015, Chris Wilson
On Mon, 2015-06-29 at 13:26 +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 01:19:05PM +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 11:50:23AM +0300, Ander Conselvan De Oliveira wrote:
Here's what I got so far, after updating with your suggestions.
i915 platform:
ALL
On Mon, Jun 29, 2015 at 02:31:22PM +0300, Ander Conselvan De Oliveira wrote:
On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
Hi all,
I've been looking into creating custom fields in Bugzilla to help sort
our bugs in a more manageable way.
[...]
So I would
On Mon, Jun 29, 2015 at 02:42:25PM +0300, Jani Nikula wrote:
On Mon, 29 Jun 2015, Mika Kahola mika.kah...@intel.com wrote:
On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Tue, 16 Jun 2015, Jani Nikula
On Mon, 2015-06-29 at 12:34 +0100, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 02:31:22PM +0300, Ander Conselvan De Oliveira wrote:
On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
Hi all,
I've been looking into creating custom fields in Bugzilla to help sort
On Mon, 29 Jun 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Mon, Jun 29, 2015 at 02:40:15PM +0300, Jani Nikula wrote:
On Thu, 07 May 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
On Tue, May 05, 2015 at 09:17:29AM
Hi,
Nick Hoath nicholas.ho...@intel.com writes:
From: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 5 +
1 file changed, 5 insertions(+)
On 06/29/2015 03:07 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations
On 29/06/2015 15:08, Mika Kuoppala wrote:
Hi,
Nick Hoath nicholas.ho...@intel.com writes:
From: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 5
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6654
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations done on
different BO mapped in that region, triggering invalidate.
Signed-off-by: Michał Winiarski
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL. Having VGA mode enabled even in unused
DPLLs can cause problems for CHV, so it
On 29/06/15 12:39, Jani Nikula wrote:
On Wed, 06 May 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On 29/04/15 17:10, yu@intel.com wrote:
From: Alex Dai yu@intel.com
This is to avoid bad IO access caused by writing NOOP to
On Fri, 2015-06-26 at 14:43 -0700, Linus Torvalds wrote:
On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie airl...@linux.ie wrote:
This is the main drm pull request for v4.2.
It seems to work ok for me, but it causes quite a few new warnings on
my Sony VAIO Pro laptop. It's (once more) a
The old style of memory interleaving swizzled upto the end of the
first even bank of memory, and then used the remainder as unswizzled on
the unpaired bank - i.e. swizzling is not constant for all memory. This
causes problems when we try to migrate memory and so the kernel prevents
migration at
Nick Hoath (2):
drm/i915/bxt: Enable WaOCLCoherentLineFlush
drm/i915/bxt: Clean up bxt_init_clock_gating
Rafael Barbalho (2):
drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable
drm/i915/bxt: Enable WaDSRefCountFullforceMissDisable
drivers/gpu/drm/i915/i915_reg.h | 1 +
On Tue, Jun 23, 2015 at 08:36:30AM +0200, Andreas Lampersperger wrote:
When the i915.ko identify an eDP output on a valleyview
board, it should be more slackly. The reason for that is,
that BIOS DATA TABLES generated with intel BMP (Binary
Modification Program) do not set bits for NOT_HDMI or
The section id is generated from the section title and is used to create
the html output filename, which therefore causes problems if it includes
a '/' character.
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/intel_mmio.c | 1 +
1 file
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Cc: Rafael Barbalho rafael.barba...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
From: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
From: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations done on
different BO mapped in that region,
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the REF to the VLV ref clock selection bit.
On Mon, 29 Jun 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Jun 28, 2015 at 02:18:16PM +0100, Chris Wilson wrote:
In needs_ilk_vtd_wa(), we pass in the GPU device but compared it against
the ids for the mobile GPU and the mobile host bridge. That latter is
impossible and so likely was
On Thu, 07 May 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
[ 1572.417121] BUG: unable to handle kernel NULL pointer dereference at
(null)
[
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations done on
different BO mapped in that region, triggering invalidate.
Signed-off-by: Michał Winiarski michal.winiar...@intel.com
---
tests/gem_userptr_blits.c | 83
Michał Winiarski found a really evil way to trigger a struct_mutex
deadlock with userptr. He found that if he allocated a userptr bo and
then GTT mmaped another bo, or even itself, at the same address as the
userptr using MAP_FIXED, he could then cause a deadlock any time we then
had to invalidate
On Mon, 29 Jun 2015, Mika Kahola mika.kah...@intel.com wrote:
On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Wed, 03 Jun 2015, Mika Kahola
On Friday 26 June 2015 10:46 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:44PM +0530, Ramalingam C wrote:
Display Refresh Rate Switching (DRRS) is a power conservation feature
which enables swtching between low and high refresh rates,
dynamically, based on the usage scenario to save
On Fri, 26 Jun 2015, Jani Nikula jani.nik...@intel.com wrote:
Some 855gm models (at least ThinkPad X40) regressed because of
commit b0cd324faed23d10d66ba6ade66579c681feef6f
Author: Jani Nikula jani.nik...@intel.com
Date: Wed Nov 12 16:25:43 2014 +0200
drm/i915: don't save/restore
On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote:
On Wed, 03 Jun 2015, Mika Kahola mika.kah...@intel.com wrote:
From: Ville Syrjälä
On Wed, 06 May 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On 29/04/15 17:10, yu@intel.com wrote:
From: Alex Dai yu@intel.com
This is to avoid bad IO access caused by writing NOOP to wrap the
ring buffer whilst ring is
On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
Hi all,
I've been looking into creating custom fields in Bugzilla to help sort
our bugs in a more manageable way.
[...]
So I would like to hear what other people think about this. Specially,
about what should be in the
On Mon, 2015-06-29 at 14:47 +0300, Jani Nikula wrote:
On Mon, 29 Jun 2015, Ander Conselvan De Oliveira conselv...@gmail.com wrote:
i915 features:
display - atomic
display - audio
display - DP
display - DP MST
display - DSI
display - eDP
display - FBC
display - HDMI
From: Ville Syrjälä ville.syrj...@linux.intel.com
DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
to either pipe B or C. So do that to make pixel repeat work on pipes
B and C. Pipe A is fine without any tricks.
From: Ville Syrjälä ville.syrj...@linux.intel.com
Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the REF to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consistency.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
While trawling the w/a database I spotted a workaround we didn't
have related to CHV DPLL pixel multiuplier setting. So I set forth
to implement it, and while doing that I ended up cleaning up the
VLV/CHV DPLL handling a bit. This also touched the
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems for CHV. So let's just
pull the code to configure those bits into the disp2d well enable hook.
With the DPLL disable code also fixed
From: Ville Syrjälä ville.syrj...@linux.intel.com
The BIOS maybe leave the DSI PLL enabled even if the port is disabled.
The PLL doesn't seem to like being reconfigured while it's enabled so
make sure it's disabled before doing that.
The better fix would be to expose all PLLs independently of
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in intel_dsi_get_config(). This avoids spurious
state checker warnings. We already did it this way for DPLL_MD, but do
it for DPLL too.
Toss in a WARN to
Looks fine to me.
Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com
On 06/25/2015 11:11 AM, David Weinehall wrote:
This patch adds support for 0.85V VccIO on Skylake Y,
separate buffer translation tables for Skylake U,
and support for I_boost for the entries that needs this.
On Fri, Jun 26, 2015 at 02:52:34PM +0300, Joonas Lahtinen wrote:
Add forking subtests to gem_ringfill. Tests cause consistent GPU
hangs on SKL.
v2: Removed noop parts.
v3:
- Allow executing the tests in order too (Chris Wilson).
- Rename the tests to -forked-1
Cc: Mika Kuoppala
On Thu, Jun 18, 2015 at 10:42:40AM +0200, Patrik Jakobsson wrote:
This set of patches adds a dispatcher for handling DRM ioctls. The
kernel headers for DRM might not be available on all distributions
so we depend on libdrm for those. If libdrm is not available we fall
back on the kernel
On Friday 26 June 2015 10:38 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:53PM +0530, Ramalingam C wrote:
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the same vrefresh, then userspace
activities based on vsync will go for toss.
On Sun, 28 Jun 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Sun, Jun 28, 2015 at 09:19:26AM +0100, Chris Wilson wrote:
The old style of memory interleaving swizzled upto the end of the
first even bank of memory, and then used the remainder as unswizzled on
the unpaired bank - i.e.
On Mon, Jun 29, 2015 at 01:19:05PM +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 11:50:23AM +0300, Ander Conselvan De Oliveira wrote:
On Fri, 2015-06-26 at 19:05 +0200, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 06:28:39PM +0300, Ander Conselvan De Oliveira
wrote:
Hi all,
On Mon, Jun 29, 2015 at 02:40:15PM +0300, Jani Nikula wrote:
On Thu, 07 May 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
[ 1572.417121] BUG: unable to handle
From: Ville Syrjälä ville.syrj...@linux.intel.com
The pipe A power well is the disp2d well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the checks for pipe A vs.
others and just assume it's always pipe A.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
We do the exact same steps around the disp2d/pipe A power well
enable/disable on VLV and CHV. Refactor the shared code into
some helpers.
Note that this means we now call vlv_power_sequencer_reset() before
turning off the power well, whereas
From: Ville Syrjälä ville.syrj...@linux.intel.com
We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL. Having VGA mode enabled even in unused
DPLLs can cause problems for CHV, so it seems wiser to always keep it
disabled. And let's just do that on
From: Ville Syrjälä ville.syrj...@linux.intel.com
The VLV and CHV DPLL disable and update are almost identical in
how the DPLL/DPLL_MD registers need to be set up. But the code
looks more different than it really is. Try to bring them into
line.
Signed-off-by: Ville Syrjälä
On Mon, 29 Jun 2015, Ander Conselvan De Oliveira conselv...@gmail.com wrote:
On Fri, 2015-06-26 at 14:43 -0700, Linus Torvalds wrote:
On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie airl...@linux.ie wrote:
This is the main drm pull request for v4.2.
It seems to work ok for me, but it causes
On Mon, Jun 29, 2015 at 07:46:18PM +0530, Sivakumar Thulasimani wrote:
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL.
On Friday 26 June 2015 10:42 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:54PM +0530, Ramalingam C wrote:
For all the connectors drrs init is invoked. drrs_init will
initialize the drrs for those connectors that support DRRS.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
Makes it really hard to reason about these since there are dependency
loops. Also if you touch them and don't know what you're doing you get
to keep all the pieces.
Also sweep over all options and mark everything which isn't clearly
just a harmless debug helper thing of one of the official
On Mon, Jun 29, 2015 at 03:15:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 03:07 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backing the userptr object is freed by the user,
Hi,
On Mon, Jun 15, 2015 at 11:49:52AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
We had two failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls drm_framebuffer_remove,
which grabs the struct mutex and intelfb_create (caller of
Nick Hoath nicholas.ho...@intel.com writes:
On 29/06/2015 15:08, Mika Kuoppala wrote:
Hi,
Nick Hoath nicholas.ho...@intel.com writes:
From: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
Signed-off-by: Nick Hoath
Hi Jani,
On Mon, Jun 29, 2015 at 02:24:19PM +0300, Jani Nikula wrote:
On Mon, 15 Jun 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
There wasn't, I just rewrote it incorrectly. There's also a
drm_framebuffer_remove() called by intelfb_alloc which needs to be moved
out of the mutex. A
On Friday 26 June 2015 10:41 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:55PM +0530, Ramalingam C wrote:
During the DRRS state transitions we are modifying the clock and
hence the vrefresh rate.
So we need to update the drm_crtc-mode and the adjusted
mode in intel_crtc. So that
On Mon, Jun 29, 2015 at 02:46:41PM +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 02:42:25PM +0300, Jani Nikula wrote:
On Mon, 29 Jun 2015, Mika Kahola mika.kah...@intel.com wrote:
On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
On Tue, 16 Jun 2015, Jani Nikula
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6655
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Nick Hoath nicholas.ho...@intel.com writes:
Add stepping check for A0 workarounds, and remove the associated
FIXME tags.
Split out unrelated WAs for later condition checking.
v2: Fixed format (PeterL)
v3: Corrected stepping check for WaDisableSDEUnitClockGating
- Ignoring comment,
On Mon, 29 Jun 2015, Dave Gordon david.s.gor...@intel.com wrote:
On 29/06/15 12:39, Jani Nikula wrote:
On Wed, 06 May 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On 29/04/15 17:10, yu@intel.com wrote:
From: Alex Dai
Hi All,
More i915 WARN splats. This one on a machine with Linus' latest tree
as of this morning.
josh
[7.906372] [drm] Replacing VGA console driver
[7.935724] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[7.942359] [drm] Driver supports precise vblank timestamp
On Mon, Jun 29, 2015 at 03:56:07PM +0100, Tvrtko Ursulin wrote:
Yes. But I would prefer MAP_FIXED to be the first invalidate, but that
looks like we then need to leak the ptr.
If it used mmap instead of posix_memalign and no free then what
would it leak? MAP_FIXED would be guaranteed first
On 06/29/2015 03:25 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:15:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 03:07 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory
Hi,
On 06/29/2015 03:39 PM, Lukas Wunner wrote:
Hi,
On Mon, Jun 15, 2015 at 11:49:52AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
We had two failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls drm_framebuffer_remove,
which grabs the
On Mon, Jun 29, 2015 at 05:50:09PM +0300, Jani Nikula wrote:
On Mon, 29 Jun 2015, Ander Conselvan De Oliveira conselv...@gmail.com wrote:
On Fri, 2015-06-26 at 14:43 -0700, Linus Torvalds wrote:
On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie airl...@linux.ie wrote:
This is the main drm
On Mon, Jun 29, 2015 at 04:52:14PM +0530, Ramalingam C wrote:
On Friday 26 June 2015 10:46 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:44PM +0530, Ramalingam C wrote:
- Static DRRS and generalized seamless DRRS are imo separate features and
we should split the patch series.
From: John Harrison john.c.harri...@intel.com
An earlier patch was added to reserve space in the ring buffer for the
commands issued during 'add_request()'. The initial version was
pessimistic in the way it handled buffer wrapping and would cause
premature wraps and thus waste ring space.
This
On Mon, Jun 29, 2015 at 05:44:40PM +0300, Jani Nikula wrote:
On Mon, 29 Jun 2015, Dave Gordon david.s.gor...@intel.com wrote:
On 29/06/15 12:39, Jani Nikula wrote:
On Wed, 06 May 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On
On Mon, Jun 29, 2015 at 12:17:33PM +0100, Chris Wilson wrote:
Michał Winiarski found a really evil way to trigger a struct_mutex
deadlock with userptr. He found that if he allocated a userptr bo and
then GTT mmaped another bo, or even itself, at the same address as the
userptr using MAP_FIXED,
On Mon, Jun 29, 2015 at 02:31:22PM +0300, Ander Conselvan De Oliveira wrote:
On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
Hi all,
I've been looking into creating custom fields in Bugzilla to help sort
our bugs in a more manageable way.
[...]
So I would
On Mon, Jun 29, 2015 at 01:35:06PM +0300, Antti Koskipää wrote:
Looks fine to me.
Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com
On 06/25/2015 11:11 AM, David Weinehall wrote:
This patch adds support for 0.85V VccIO on Skylake Y,
separate buffer translation tables for
On Mon, Jun 29, 2015 at 05:18:21PM +0530, Ramalingam C wrote:
On Friday 26 June 2015 10:38 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:53PM +0530, Ramalingam C wrote:
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the same
This code is all dead code since we want to go up to DC6, always.
Cc: A.Sunil Kamath sunil.kam...@intel.com
Cc: Suketu Shah suketu.j.s...@intel.com
Cc Animesh Manna animesh.ma...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Damien Lespiau
Currently, when the firwmare isn't loaded, we don't enable DC6
(obviously!) but the disable path tries unconditionally to disable DC6.
[drm:i915_power_well_enable] enabling power well 1
[drm:i915_power_well_enable] enabling MISC IO power well
[drm:i915_power_well_enable] enabling power well 2
On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
This code is all dead code since we want to go up to DC6, always.
On BXT DC6 is not available, so we can only go to DC5. It's disabled on
BXT atm, since runtime PM isn't enabled either.
Cc: A.Sunil Kamath sunil.kam...@intel.com
Cc:
On Mon, Jun 29, 2015 at 07:54:42PM +0300, Imre Deak wrote:
On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
This code is all dead code since we want to go up to DC6, always.
On BXT DC6 is not available, so we can only go to DC5. It's disabled on
BXT atm, since runtime PM isn't
On Mon, Jun 29, 2015 at 08:28:53PM +0530, Ramalingam C wrote:
On Friday 26 June 2015 10:41 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:55PM +0530, Ramalingam C wrote:
During the DRRS state transitions we are modifying the clock and
hence the vrefresh rate.
So we need to update
On Mon, Jun 29, 2015 at 04:30:40PM +0530, Sivakumar Thulasimani wrote:
From: Thulasimani, Sivakumar sivakumar.thulasim...@intel.com
HPD storm is detected in intel_hpd_irq_handler and disabled for respective
port immediately but polling is enabled only in i915_hotplug_work_func and
not in
On Mon, Jun 29, 2015 at 03:25:52PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in intel_dsi_get_config(). This avoids spurious
state checker warnings.
On Mon, Jun 29, 2015 at 06:42:11PM +0200, Daniel Vetter wrote:
On Mon, Jun 29, 2015 at 03:25:52PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in
On Mon, Jun 29, 2015 at 07:56:05PM +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 06:42:11PM +0200, Daniel Vetter wrote:
On Mon, Jun 29, 2015 at 03:25:52PM +0300, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV don't use the DPLL
On Mon, 2015-06-29 at 17:59 +0100, Damien Lespiau wrote:
On Mon, Jun 29, 2015 at 07:54:42PM +0300, Imre Deak wrote:
On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
This code is all dead code since we want to go up to DC6, always.
On BXT DC6 is not available, so we can only go
On Thu, 18 Jun 2015 10:42:45 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
This patch adds many of the DRM and KMS ioctls. The rest can be added as
needed.
* drm.c: Decode DRM_IOCTL_VERSION
* drm.c: Decode DRM_IOCTL_GET_UNIQUE
* drm.c: Decode DRM_IOCTL_GET_MAGIC
* drm.c:
But DC5 needed for BXT
- Sunil
-Original Message-
From: Lespiau, Damien
Sent: Monday, June 29, 2015 10:15 PM
To: intel-gfx@lists.freedesktop.org
Cc: Kamath, Sunil; Shah, Suketu J
Subject: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
This code is all dead code since we want to go up
On Mon, Jun 29, 2015 at 08:08:59PM +0300, Imre Deak wrote:
On Mon, 2015-06-29 at 17:59 +0100, Damien Lespiau wrote:
On Mon, Jun 29, 2015 at 07:54:42PM +0300, Imre Deak wrote:
On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
This code is all dead code since we want to go up to
On Thu, 18 Jun 2015 10:42:44 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
There are more ioctls to add but the ones in this patch are most
commonly used.
* Makefile.am: Add compilation of drm_i915.c
* drm.c: Dispatch i915 ioctls
* drm_i915.c: Decode
On Mon, 29 Jun 2015 12:47:20 +0200
Patrik Jakobsson patrik.jakobs...@linux.intel.com wrote:
On Thu, Jun 18, 2015 at 10:42:40AM +0200, Patrik Jakobsson wrote:
This set of patches adds a dispatcher for handling DRM ioctls. The
kernel headers for DRM might not be available on all distributions
Hi Tvrtko,
On Mon, Jun 29, 2015 at 04:15:08PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 03:39 PM, Lukas Wunner wrote:
On Mon, Jun 15, 2015 at 11:49:52AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
We had two failure modes here:
1.
Deadlock in
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6657
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
From: Ville Syrjälä ville.syrj...@linux.intel.com
Stolen gets trashed during hibernation, so storing contexts there
is not a very good idea. On my IVB machines this leads to a totally
dead GPU on resume. A reboot is required to resurrect it. So let's
not store contexts where they will get
Michał Winiarski found a really evil way to trigger a struct_mutex
deadlock with userptr. He found that if he allocated a userptr bo and
then GTT mmaped another bo, or even itself, at the same address as the
userptr using MAP_FIXED, he could then cause a deadlock any time we then
had to invalidate
On Friday 26 June 2015 10:20 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:45PM +0530, Ramalingam C wrote:
EDP specific DRRS implementation is removed to implement a
generic DRRS stack extentable accross the supportable encoders.
Signed-off-by: Ramalingam C ramalinga...@intel.com
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6646
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
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