Hi Gurus:
Recently we found that the wait_for() marco in intel_drv.h looks
will cause dead lock. wait_for() macro will try to wait jiffies change
in a condition check loop, but when local cpu interrupt is disabled, it
seems the jiffies will never change under a uni-processor environment.
And
Since we may conceivably encounter situations where the upper part of the
64bit register changes between reads, for example when a timestamp
counter overflows, change the WARN into a retry loop.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Michał Winiarski michal.winiar...@intel.com
Hi Dave,
Next batch of i915 fixes. Note that the compat32 patch here needs the drm
core one to be actually useful, I'll send you that one with a separate
drm-fixes pull request. One revert because a fix in -rc2 did break
existing userspace.
Cheers, Daniel
The following changes since commit
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register when read using a single instruction, split the
read into two instructions. Since the read here is of automatically
incrementing timestamp counters, we also have to be very careful in
order to make sure
From: Sourab Gupta sourab.gu...@intel.com
This patch adds the routines which insert commands for capturing OA
snapshots into the ringbuffer of RCS engine.
The command MI_REPORT_PERF_COUNT can be used to capture snapshots of OA
counters, which is inserted at BB boundaries.
While inserting the
From: Sourab Gupta sourab.gu...@intel.com
This patch introduces flags and adds support for having pid output with the
timestamp samples and forwarding them through perf.
When the userspace expresses its interest in listening to the pid through a
gen pmu attr field during event init, the samples
From: Sourab Gupta sourab.gu...@intel.com
This patch enables userspace to specify tags (per workload), provided via
execbuffer ioctl, which could be added to timestamps samples, to help
associate samples with the corresponding workloads.
There may be multiple stages within a single context, from
From: Sourab Gupta sourab.gu...@intel.com
This patch introduces flags and adds support for having ring id output with
the timestamp samples and forwarding them through perf.
When the userspace expresses its interest in listening to the ring id
through a gen pmu attr field during event init, the
From: Sourab Gupta sourab.gu...@intel.com
This patch adds support for retrieving MMIO register values alongwith
timestamps and forwarding them to userspace through perf.
The userspace can request upto 8 MMIO register values to be dumped.
The addresses of upto 8 MMIO registers can be passed
From: Sourab Gupta sourab.gu...@intel.com
This patch adds the routines through which one can insert commands in the
ringbuf for capturing timestamps, which are used to insert these commands
around the batchbuffer.
While inserting the commands, we keep a reference of associated request.
This will
On Wed, Jul 15, 2015 at 01:34:29PM +0530, Jindal, Sonika wrote:
On 7/15/2015 12:05 PM, Jindal, Sonika wrote:
On 7/14/2015 7:52 PM, Imre Deak wrote:
On ti, 2015-07-14 at 11:18 +0530, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to
On Wed, Jul 15, 2015 at 02:16:56PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
Currently the context ids are specific to a drm file instance, as opposed
to being globally unique. There are some usecases, which may require
globally unique context ids. For
On Wed, Jul 15, 2015 at 02:17:03PM +0530, sourab.gu...@intel.com wrote:
@@ -802,7 +808,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_CONSTANTS_REL_SURFACE (26) /* gen4/5 only */
__u64 flags;
__u64 rsvd1; /* now used for context info */
- __u64 rsvd2;
+ __u64
On Wed, Jul 15, 2015 at 02:17:03PM +0530, sourab.gu...@intel.com wrote:
+/** Inform the kernel that tag is passed through rsvd2 field of
+ * execbuffer args
+ */
+#define I915_EXEC_TAG(115)
No need. The tag is always passed along, if this flag isn't set then it
is
On Wed, Jul 15, 2015 at 02:17:03PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
This patch enables userspace to specify tags (per workload), provided via
execbuffer ioctl, which could be added to OA reports, to help associate
reports with the corresponding
On Wed, Jul 15, 2015 at 08:50:44AM +0100, Chris Wilson wrote:
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register when read using a single instruction, split the
read into two instructions. Since the read here is of automatically
incrementing
On 7/15/2015 12:05 PM, Jindal, Sonika wrote:
On 7/14/2015 7:52 PM, Imre Deak wrote:
On ti, 2015-07-14 at 11:18 +0530, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to check the external panel connection and DDIC HPD
logic for edp panel.
On Mon, Jun 22, 2015 at 12:54 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing
On Wed, Jul 15, 2015 at 08:59:52AM +0100, Chris Wilson wrote:
On Wed, Jul 15, 2015 at 08:50:44AM +0100, Chris Wilson wrote:
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register when read using a single instruction, split the
read into two
From: Sourab Gupta sourab.gu...@intel.com
This patch adds the mechanism for forwarding the timestamp data to
userspace using the Gen PMU perf event interface.
The timestamps will be captured in a gem buffer object. The metadata
information (ctx_id right now) pertaining to snapshot is maintained
From: Sourab Gupta sourab.gu...@intel.com
The current perf PMU driver is specific for collection of OA counter
statistics (which may be done in a periodic or asynchronous way). Since
this enables us (and limits us) to render ring, we have no means for
collection of data pertaining to other rings.
Hi Dave,
Compared to the old drm-fixes pull request just added the compat32 patch
from Tvrtko.
Cheers, Daniel
The following changes since commit e24ff467e12e1560de753313976c46e84fa6306a:
drm/crtc: Fix edid length computation (2015-07-04 00:52:34 +0200)
are available in the git repository
From: Sourab Gupta sourab.gu...@intel.com
This patch handles the event stop and destroy callbacks taking into account
the fact that there may be commands scheduled on GPU which may utilize the
destination buffer.
The event stop would just set the event state, and stop forwarding data to
From: Sourab Gupta sourab.gu...@intel.com
This is an updated patch set (changes list at end), which builds upon the
multi context OA patch set introduced earlier at:
http://lists.freedesktop.org/archives/intel-gfx/2015-July/071697.html
The OA unit, as such, is specific to render ring and can't
On Wed, Jul 15, 2015 at 02:21:40PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
This patch adds the mechanism for forwarding the timestamp data to
userspace using the Gen PMU perf event interface.
The timestamps will be captured in a gem buffer object. The
From: Sourab Gupta sourab.gu...@intel.com
This is an updated patch series(changes list at end), which adds support for
capturing OA counter snapshots for multiple contexts, by inserting
MI_REPORT_PERF_COUNT commands into CS, and forwarding these snapshots to
userspace using perf interface.
This
From: Sourab Gupta sourab.gu...@intel.com
Currently the context ids are specific to a drm file instance, as opposed
to being globally unique. There are some usecases, which may require
globally unique context ids. For e.g. a system level GPU profiler tool may
lean upon the context ids to
From: Sourab Gupta sourab.gu...@intel.com
This patch introduces flags and adds support for having pid output with the
OA reports generated through the RCS commands.
When the userspace expresses its interest in listening to the pid through
an oa_attr field during event init, the OA reports
From: Sourab Gupta sourab.gu...@intel.com
This patch enables userspace to specify tags (per workload), provided via
execbuffer ioctl, which could be added to OA reports, to help associate
reports with the corresponding workloads.
There may be multiple stages within a single context, from a
From: Sourab Gupta sourab.gu...@intel.com
This patch introduces a mode of capturing OA counter reports belonging to
multiple contexts, which can be mapped back to individual contexts. The OA
reports captured in this way are synchronized with Render command stream.
There may be usecases wherein
From: Sourab Gupta sourab.gu...@intel.com
The periodic reports and the RCS based reports are collected in two
separate buffers. While forwarding to userspace, these have to be sent to
single perf event ringbuffer. From a userspace perspective, it is good to
have the reports in the single buffer
From: Sourab Gupta sourab.gu...@intel.com
In the periodic OA sampling mode, the event stop would stop forwarding
samples to userspace, and disables OA synchronously. The buffer is
destroyed eventually in event destroy callback. But when we have in flight
RPC commands scheduled on GPU (like in
From: Sourab Gupta sourab.gu...@intel.com
This patch adds the mechanism for forwarding the CS based OA snapshots
through the perf event interface.
The OA snapshots will be captured in a gem buffer object. The metadata
information (ctx_id right now) pertaining to snapshot is maintained in a
list,
tree: git://anongit.freedesktop.org/drm-intel topic/drm-fixes
head: 0acc813c90a9e7ed22a41eed84218be459116e07
commit: 0acc813c90a9e7ed22a41eed84218be459116e07 [5/5] drm: Provide compat
ioctl for addfb2.1
config: x86_64-randconfig-x003-201528 (attached as .config)
reproduce:
git checkout
Argh, I screwed up this doesn't even compile ...
-Daniel
On Wed, Jul 15, 2015 at 10:52 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Hi Dave,
Compared to the old drm-fixes pull request just added the compat32 patch
from Tvrtko.
Cheers, Daniel
The following changes since commit
On Tue, Jul 14, 2015 at 01:37:32PM -0700, Greg KH wrote:
On Tue, Jul 14, 2015 at 11:22:35AM +0200, Daniel Vetter wrote:
On Mon, Jul 13, 2015 at 09:36:45AM -0700, jay.p.pa...@intel.com wrote:
From: Jay Patel jay.p.pa...@intel.com
NOTE: This is an interim solution which is targeted
On 7/14/2015 7:52 PM, Imre Deak wrote:
On ti, 2015-07-14 at 11:18 +0530, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to check the external panel connection and DDIC HPD
logic for edp panel.
Signed-off-by: Sonika Jindal
On Tue, Jun 30, 2015 at 05:06:47PM +0300, Imre Deak wrote:
commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
Author: Imre Deak imre.d...@intel.com
Date: Thu Oct 23 19:23:26 2014 +0300
drm/i915: add poweroff_late handler
introduced a regression on old platforms during hibernation. A
On Wed, Jul 15, 2015 at 09:03:33AM -0700, Marc MERLIN wrote:
kernel: 3.19.8
xserver-xorg-video-intel 2:2.99.917-1 on debian
X.Org X Server 1.17.1
Actually I forgot to mention:
Thinkpad T540p
[ 39406.173] (--) intel(0): Integrated Graphics Chipset: Intel(R) HD Graphics
4600
And I do get
Hey there,
I've been discussing with Daniel Vetter about adding Markdown support to
kernel-doc.
There were some discussions about improving documentation flexibility and
although there were no
consensus at the time I believe (and I think others might agree) that Markdown
is best suit for this
Nick Hoath nicholas.ho...@intel.com writes:
v2: Patch leakage fixed
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
3 files changed, 6
Currently we both set mode-private_flags to some value and also use
the pipe_config quirk. But since the pipe_config quirk isn't tied to
the lifetime of the mode object we need to check both.
Simplify this by only using mode.private_flags and stop using the
INHERITED_MODE quirk. Also for clarity
Now that we recompute the pipe config for all CRTCs that have changed
we don't have problems with stale configuration data for the global
pfit and can remove this hack. Yay!
Cc: Maarten Lankhorst maarten.lankho...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
Fastboot should only downgrade a modeset if we have a match, not be
used to upgrade to a full modeset. Otherwise we can only use it in a
very restricted way: Initial modeset when the request mode is the
preferred one of the panel and there's still a pfit active. And that
only works because our
On Wed, Jul 15, 2015 at 01:51:05PM +0300, Mika Kuoppala wrote:
Nick Hoath nicholas.ho...@intel.com writes:
v2: Patch leakage fixed
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Queued for -next, thanks for the patch.
-Daniel
On (07/14/15 17:11), Daniel Vetter wrote:
Have you forwarded to a more recent -nightly? I just merged a patch which
might have fixed this ...
Hello,
yep, I use the most recent -next usually (update it everyday),
when it boots. I can't reproduce the problem so far, hopefully
the commit you
On Wed, 2015-07-15 at 09:40 +, Chris Wilson wrote:
On Wed, Jul 15, 2015 at 02:21:40PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
This patch adds the mechanism for forwarding the timestamp data to
userspace using the Gen PMU perf event interface.
On Tue, Jul 14, 2015 at 04:29:13PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Use the appropriate call.
I know there's a discussion about whether we need this call here at
all, but removing the call means we'll only update FBC after we get
the page flip IRQ. So
On Wed, Jul 15, 2015 at 02:17:01PM +0530, sourab.gu...@intel.com wrote:
+void i915_oa_insert_cmd(struct intel_ringbuffer *ringbuf, u32 ctx_id)
You need to pass in the request here instead.
A better name would be i915_oa_emit_perf_report(). insert_cmd() is a
little too generic (i.e. which cmd do
On (07/15/15 11:51), Michel Dänzer wrote:
On 14.07.2015 22:41, Sergey Senozhatsky wrote:
sometimes `xset dpms force off' just turns off the panel for a second,
sometimes -- until I generate a `wakeup' event (key press, etc.)
FWIW, the former case is because releasing the enter key
On Wed, Jul 15, 2015 at 11:30:13AM +, Gupta, Sourab wrote:
On Wed, 2015-07-15 at 09:40 +, Chris Wilson wrote:
static void gen_pmu_flush_snapshots(struct drm_i915_private *dev_priv)
{
WARN_ON(!dev_priv-gen_pmu.buffer.addr);
- /* TODO: routine for forwarding snapshots
On Wed, Jul 15, 2015 at 11:31:32AM +0100, Chris Wilson wrote:
On Wed, Jul 15, 2015 at 10:54:28AM +0100, Chris Wilson wrote:
On Wed, Jul 15, 2015 at 02:16:56PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
Currently the context ids are specific to a drm
On Wed, Jul 15, 2015 at 10:54:28AM +0100, Chris Wilson wrote:
On Wed, Jul 15, 2015 at 02:16:56PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
Currently the context ids are specific to a drm file instance, as opposed
to being globally unique. There are
On 07/14/15 12:16, Daniel Vetter wrote:
cut away old quotes
I would guess that a LUT supporting 16 bit color components would need a
precision
of 0.20 or so (assuming the resulting values are used in further
calculations).
High dynamic range video will be an important driving force
On Wed, Jul 15, 2015 at 02:21:46PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
This patch adds support for retrieving MMIO register values alongwith
timestamps and forwarding them to userspace through perf.
The userspace can request upto 8 MMIO register
On Tue, Jul 14, 2015 at 06:19:22PM +0300, Mika Kuoppala wrote:
Arun Siluvery arun.siluv...@linux.intel.com writes:
In Indirect context w/a batch buffer,
+WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
v2: SKL revision id was used for BXT, copy paste error found during
internal
Op 13-07-15 om 19:16 schreef Daniel Stone:
Hi,
On 13 July 2015 at 15:30, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
@@ -13649,9 +13647,7 @@ static void intel_begin_crtc_commit(struct drm_crtc
*crtc)
/* Perform vblank evasion around commit operation */
if
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, July 15, 2015 4:47 PM
To: Daniel, Thomas
Cc: Goel, Akash; intel-gfx@lists.freedesktop.org; Belgaumkar, Vinay;
Winiarski,
Michal; Zou, Nanhai
Subject: Re: [PATCH v4] drm/i915: Add soft-pinning
On Wed, Jul 15, 2015 at 03:58:33PM +, Daniel, Thomas wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, July 15, 2015 4:47 PM
To: Daniel, Thomas
Cc: Goel, Akash; intel-gfx@lists.freedesktop.org; Belgaumkar, Vinay;
Winiarski,
kernel: 3.19.8
xserver-xorg-video-intel 2:2.99.917-1 on debian
X.Org X Server 1.17.1
[254670.214607] pool[30720]: segfault at 20 ip 7f0e68d3f534 sp
7f0dd57f9500 error 4 in libgio-2.0.so.0.4200.1[7f0e68cfa000+171000]
[254670.781126] [ cut here ]
[254670.781140]
This patch adds set_property handler for deGamma color correction and
enhancement capability at Pipe level on CHV/BSW platform. The set
function just attaches the deGamma blob to CRTC state, that later gets
committed using atomic path.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
CHV/BSW platform supports various Gamma correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Adds the core function to program Gamma correction values for CHV/BSW
platform
2. Adds Gamma correction macros/defines
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
CHV/BSW platform
2. Adds CSC correction macros/defines
This patch adds set_property handler for CSC color correction
and enhancement capability at Pipe level on CHV/BSW platform. The set
function just attaches the CSC blob to CRTC state, that later
gets committed using atomic path.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Color Manager framework defines a color correction property for color
space transformation and Gamut mapping. This property is called CTM (Color
Transformation Matrix).
This patch adds a new structure in DRM layer for CTM color correction.
This structure will be used by all user space agents to
This patch adds set_property handler for Gamma color correction and
enhancement capability at Pipe level on CHV/BSW platform. The set
function just attaches the Gamma blob to CRTC state, that later gets
committed using atomic path.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
This only grabs the mutex when really needed, but still has a
might-acquire lockdep check to make sure that's always possible.
With this patch tegra is officially struct_mutex free, yay!
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
Since David Herrmann's mmap vma manager rework we don't need to grab
dev-struct_mutex any more to prevent races when looking up the mmap
offset. Drop it and instead don't forget to use the unref_unlocked
variant (since the drm core still cares).
While at it also fix a leak when this ioctl is
drm_property_replace_global_blob() is getting used by many wrapper
functions to replace an existing blob with new values. Because this
function was static, modules are forced to create wrapper functions in
same file. Exporting this function will remove need for such wrapper
functions.
This patch
Color Management is an extension to Kernel display framework. It allows
abstraction of hardware color correction and enhancement capabilities by
virtue of DRM properties.
This patch initializes color management framework by :
1. Introducing new pointers in DRM mode_config structure to
carry
This patch does the following:
1. Adds new files intel_color_manager(.c/.h)
2. Attaches color properties to CRTC while initialization
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi kausal.mall...@intel.com
---
drivers/gpu/drm/i915/Makefile |
This patch adds blob properties to CRTC state to hold the respective
blobs for color properties. These will be required by set_property calls
to attach blobs for atomic commit later.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi kausal.mall...@intel.com
As per Color Manager design, each driver is responsible to load its
palette color correction and enhancement capabilities in the form of
a DRM blob property, so that user space can query and read.
This patch loads all CHV platform specific gamma color capabilities
for CRTC into a blob that can be
This patch adds atomic set property interface for Intel CRTC. This
interface will be used to set color correction DRM properties.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi kausal.mall...@intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 11
From: Matt Roper matthew.d.ro...@intel.com
The intel_atomic_check() function had some simple testing to make
sure that an atomic update isn't updating more than one CRTC at a time.
The logic assumed that a plane was always being updated, so it figured
out the nuclear pipe from the first plane it
This patch adds new structures in DRM layer for Palette color
correction.
These structures will be used by user space agents to configure
appropriate number of samples and Palette LUT for a platform.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi
The DRM color management framework is targeting various hardware
platforms and drivers. Different platforms can have different color
correction and enhancement capabilities.
A commom user space application can query these capabilities using the
DRM property interface. Each driver can fill this
On Wed, Jul 15, 2015 at 06:39:26PM +0530, Kausal Malladi wrote:
[...]
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 57ca8cc..408d39a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1178,6 +1178,12 @@ struct drm_mode_config {
struct drm_property
On 07/15/15 14:35, Hans Verkuil wrote:
On 07/14/15 12:16, Daniel Vetter wrote:
cut away old quotes
I would guess that a LUT supporting 16 bit color components would need a
precision
of 0.20 or so (assuming the resulting values are used in further
calculations).
High dynamic range
This patch set adds Color Manager implementation in DRM layer. Color Manager is
an extension in DRM framework to support color correction/enhancement. Various
Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a
CHV/BSW supports DeGamma color correction feature, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
CHV/BSW platform
2. Adds DeGamma correction
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register when read using a single instruction, split the
read into two instructions. Since the read here is of automatically
incrementing timestamp counters, we also have to be very careful in
order to make sure
Hey,
Op 15-07-15 om 14:15 schreef Daniel Vetter:
Currently we both set mode-private_flags to some value and also use
the pipe_config quirk. But since the pipe_config quirk isn't tied to
the lifetime of the mode object we need to check both.
Simplify this by only using mode.private_flags and
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, July 15, 2015 4:06 PM
To: Goel, Akash
Cc: Daniel, Thomas; intel-gfx@lists.freedesktop.org; Belgaumkar, Vinay;
Winiarski, Michal; Zou, Nanhai
Subject: Re: [PATCH v4] drm/i915: Add soft-pinning
Avoids legacy userspace/code getting confused when dpms doesn't
reflect reality of what's going on.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_atomic_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
On Wed, Jul 15, 2015 at 03:41:49PM +, Daniel, Thomas wrote:
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, July 15, 2015 4:06 PM
To: Goel, Akash
Cc: Daniel, Thomas; intel-gfx@lists.freedesktop.org; Belgaumkar, Vinay;
Winiarski,
On 15 July 2015 at 16:44, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Avoids legacy userspace/code getting confused when dpms doesn't
reflect reality of what's going on.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
Reviewed-by: Daniel Stone dani...@collabora.com
On Wed, Jul 15, 2015 at 08:25:23PM +0530, Goel, Akash wrote:
+int
+i915_gem_evict_for_vma(struct i915_vma *target)
+{
+ struct drm_mm_node *node, *next;
+
+ list_for_each_entry_safe(node, next,
+ target-vm-mm.head_node.node_list,
+ node_list) {
+
On Wed, Jul 15, 2015 at 03:20:34PM +0200, Maarten Lankhorst wrote:
Hey,
Op 15-07-15 om 14:15 schreef Daniel Vetter:
Currently we both set mode-private_flags to some value and also use
the pipe_config quirk. But since the pipe_config quirk isn't tied to
the lifetime of the mode object we
Thanks for the comments, Thierry.
We can surely do this.
Regards
Shashank
-Original Message-
From: Thierry Reding [mailto:thierry.red...@gmail.com]
Sent: Wednesday, July 15, 2015 6:55 PM
To: Malladi, Kausal
Cc: Roper, Matthew D; Barnes, Jesse; Lespiau, Damien; Jindal, Sonika; R,
On 6/30/2015 7:50 PM, Daniel, Thomas wrote:
Many apologies to Michal for incorrectly spelling his name in the CC list.
Thomas.
-Original Message-
From: Daniel, Thomas
Sent: Tuesday, June 30, 2015 3:13 PM
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson; Goel, Akash; Belgaumkar,
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