From: Shashank Sharma shashank.sha...@intel.com
This patch modifies dsi_prepare() function to support the same
modeset prepare sequence for BXT also. Main changes are:
1. BXT port control register is different than VLV.
2. BXT modeset sequence needs vdisplay and hdisplay programmed
for
From: Shashank Sharma shashank.sha...@intel.com
SKL and BXT qualifies the HAS_DDI() check, and hence haswell
modeset functions are re-used for modeset sequence. But DDI
interface doesn't include support for DSI.
This patch adds:
1. cases for DSI encoder, in those modeset functions and allows
a
From: Shashank Sharma shashank.sha...@intel.com
This patch adds new functions for BXT clock and PLL programming.
They are:
1. configure_dsi_pll for BXT.
This function does the basic math and generates the divider ratio
based on requested pixclock, and program clock registers.
2.
From: Shashank Sharma shashank.sha...@intel.com
This patch contains changes to support DSI disble sequence in BXT.
The changes are:
1. BXT specific changes in clear_device_ready function.
2. BXT specific changes in DSI disable and post-disable functions.
3. Add a new function to reset BXT Dphy
From: Shashank Sharma shashank.sha...@intel.com
BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
(Output value must be 39.5Mhz)
2. Select divide by 2
From: Shashank Sharma shashank.sha...@intel.com
This patch contains following changes:
1. MIPI device ready changes to support dsi_pre_enable. Changes
are specific to BXT device ready sequence. Added check for
ULPS mode(No effects on VLV).
2. Changes in dsi_enable to pick BXT port control
From: Shashank Sharma shashank.sha...@intel.com
This patch adds two new functions:
- disable_dsi_pll.
BXT DSI disable sequence and registers are
different from previous platforms.
- intel_disable_dsi_pll
wrapper function to re-use the same code for
multiple platforms. It checks platform
From: Shashank Sharma shashank.sha...@intel.com
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar
Op 24-07-15 om 15:26 schreef Ander Conselvan De Oliveira:
On Tue, 2015-07-21 at 16:09 +0200, Maarten Lankhorst wrote:
-EDEADLK has special meaning in atomic, but get_fence may call
i915_find_fence_reg which can return -EDEADLK.
This has special meaning in the atomic world, so convert the
This patch series adds support for MIPI DSI for BXT platform.
Support for VBT v3 sequence parsing and programming is needed
for panel, backlight enable and control. The same will be added
as part of a different patch series.
Below is the link for earlier patch series in mailing list:
Hey,
I wasn't able to apply that patch to any kernel version. I tried it with
3.19.7, 4.1.3, and 4.2-rc3 and always got the following message:
patching file drivers/gpu/drm/drm_crtc.c
Hunk #1 FAILED at 5273.
1 out of 1 hunk FAILED -- saving rejects to file
drivers/gpu/drm/drm_crtc.c.rej
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
From: Sunil Kamath sunil.kam...@intel.com
Latest VBT mentions which set of registers will be used for BLC,
as controller number field. Making use of this field in BXT
BLC implementation. Also, the registers are used in case control
pin indicates display DDI. Adding a check for this.
According to
DSI backlight support for bxt is added.
TODO: There is no support for backlight control in drm panel
framework. This will be added as part of VBT version patches
fixing the backlight sequence.
v2: Fixed Jani's review comments from previous patch. Added the
BXT DSI backlight code
From: Shashank Sharma shashank.sha...@intel.com
BXT's DSI PLL is different from that of VLV. So this patch
adds a new function to get the current DSI pixel clock based
on the PLL divider ratio and lane count.
This function is required for intel_dsi_get_config() function.
v2: Fixed Jani's review
From: Shashank Sharma shashank.sha...@intel.com
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Uma Shankar
Any comments for this change ?
On 7/22/2015 6:31 PM, Sivakumar Thulasimani wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes the current code
to do the same.
On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote:
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Rodrigo Vivi rodrigo.v...@intel.com
Cc: Sunil Kamath sunil.kam...@intel.com
Signed-off-by: Animesh Manna animesh.ma...@intel.com
---
Please update the commit message header relevant details.
On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote:
Modified HAS_CSR macro defination which earlier only supported
for skl, now added support for BXT.
Cc: Vetter, Daniel daniel.vet...@intel.com
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Sunil Kamath
On 7/6/2015 4:35 PM, Vandana Kannan wrote:
From: Deepak M m.dee...@intel.com
LFP brighness control from the VBT block 43 indicates which
controller is used for brightness.
LFP1 brightness control method:
Bit 7-4 = This field controller number of the brightnes controller.
0 = Controller 0
1 =
On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote:
Display microcontroller(DMC) used to save and restore display engine status
while entering into low power display states for gen9 platform.
Though skylake and broxton both are gen9 platform but dmc act diferently.
Skylake is solely dependednt
On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote:
Added stepping info in intel_csr.c which is required to extract
specific firmware from packaged dmc firmware.
Cc: Vetter, Daniel daniel.vet...@intel.com
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Sunil
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
Behalf Of David Henningsson
Sent: Thursday, July 23, 2015 11:26 PM
To: Koul, Vinod; jani.nik...@linux.intel.com; Vetter, Daniel;
ti...@suse.de; intel-gfx@lists.freedesktop.org; alsa-devel@alsa-
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and removing the edp HPD logic because port A HPD is not
present(Imre)
v3: Rebased on top of Imre's patchset for enabling
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