From: Libin Yang
When modeset occurs and the TMDS frequency is set to some
speical value, the N/CTS need to be set manually if audio
is playing.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/i915_reg.h| 6 ++
drivers/gpu/drm/i915/intel_audio.c | 42 +++
From: Libin Yang
Display audio may not work at some frequencies
with the HW provided N/CTS.
This patch sets the proper N value for the
given audio sample rate at the impacted frequencies.
At other frequencies, it will use the N/CTS value
which HW provides.
Signed-off-by: Libin Yang
---
driver
From: Libin Yang
Add the set_ncts callback.
With the callback, audio driver can trigger
i915 driver to set the proper N/CTS
based on different sample rates.
Signed-off-by: Libin Yang
---
include/drm/i915_component.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/i915_compon
From: Libin Yang
On some Intel platforms, display audio need set N/CTS
manually at some TMDS frequencies.
Signed-off-by: Libin Yang
---
sound/pci/hda/patch_hdmi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index a97db5f..4
Op 06-08-15 om 07:34 schreef Sivakumar Thulasimani:
>
>
> On 7/27/2015 6:05 PM, Maarten Lankhorst wrote:
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 7 --
>> drivers/gpu/drm/i915/intel_dp_mst.c | 45
>> +++-
>> 2 f
From: Rodrigo Vivi
DDI-E and DDI-4 share 4 DDI-A lanes.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index aaa34b8..ea10fa8 100644
--- a/driv
From: Rodrigo Vivi
There are OEMs using DDI-E out there,
so let's enable it.
Unfortunately there is no detection bit for DDI-E
So we need to rely on VBT for that.
I also need to give credits to Xiong since before seing
his approach to check info->support_* I was creating an ugly
vbt->ddie_sfuse
Signed-off-by: Xiong Zhang
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 49 +---
drivers/gpu/drm/i915/i915_reg.h | 12 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 3
From: Rodrigo Vivi
On Skylake we have eDP-to-VGA using DDI-E and another aux.
So let's identify it properly.
Also let's remove duplicated definitions to avoid later
confusion.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_bios.h | 5 -
drivers/gpu/drm/i915/intel_dp.c | 9 ++
From: Rodrigo Vivi
There is no correspondent Aux channel for DDI-E.
So we need to rely on VBT to let us know witch one
is being used instead.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/intel_bios.c | 23 +++
drivers
DDI-E doesn't have the correspondent GMBUS pin.
We rely on VBT to tell us which one it being used instead.
The DVI/HDMI on shared port couldn't exist.
This patch isn't tested without hardware wchich has HDMI
on DDI-E.
Signed-off-by: Xiong Zhang
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
I will submit another patch.
//Derek
-Original Message-
From: Ceraolo Spurio, Daniele
Sent: Wednesday, August 5, 2015 5:00 PM
To: Morton, Derek J; intel-gfx@lists.freedesktop.org
Cc: Wood, Thomas
Subject: Re: [Intel-gfx] [PATCH i-g-t] benchmarks/Android.mk, tools/Android.mk:
Fix android
Recently added tools / benckmarks have the same module name as
existing tests. Android does not allow duplicate modules. This
patch appends _benchmark and _tool to the module names used when
building benckmarks and tools to prevent complie errors due to
clashes with tests of the same name.
v2: Don
On 8/5/2015 2:44 PM, Daniel Vetter wrote:
On Mon, Aug 03, 2015 at 09:55:35PM +0530, Animesh Manna wrote:
Another interesting criteria to work dmc as expected is pw1 to be
enabled by driver and dmc will shut it off in its execution
sequence. If already disabled by driver dmc will get confuse an
On 8/5/2015 2:42 PM, Daniel Vetter wrote:
On Mon, Aug 03, 2015 at 09:55:34PM +0530, Animesh Manna wrote:
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked.
On Wed, Aug 05, 2015 at 07:13:11PM -0300, Tiago Vignatti wrote:
> Userspace is the one in charge of flush CPU by wrapping mmap with
> begin{,end}_cpu_access.
>
> v2: Remove LLC check cause we have dma-buf sync providers now. Also, fix
> return
> before transferring ownership when mmap fails.
i91
On Thu, Aug 06, 2015 at 10:09:37AM +0100, Chris Wilson wrote:
> On Wed, Aug 05, 2015 at 07:13:11PM -0300, Tiago Vignatti wrote:
> > Userspace is the one in charge of flush CPU by wrapping mmap with
> > begin{,end}_cpu_access.
> >
> > v2: Remove LLC check cause we have dma-buf sync providers now. A
On 8/5/2015 2:35 PM, Daniel Vetter wrote:
On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote:
Mmio register access after dc6/dc5 entry is not allowed when
DC6 power states are enabled according to bspec (bspec-id 0527),
so enabling dc6 as the last call in suspend flow.
v1: Initial
On 8/5/2015 2:31 PM, Daniel Vetter wrote:
On Tue, Aug 04, 2015 at 11:25:40AM +0530, Animesh Manna wrote:
On 8/4/2015 9:16 AM, Nagaraju, Vathsala wrote:
"This patch contains the changes to remove the byte swapping logic introduced with
old dmc firmware."
Which version of DMC need reversal l
On Thu, 06 Aug 2015 08:52:55 +0200,
libin.y...@intel.com wrote:
>
> From: Libin Yang
>
> Display audio may not work at some frequencies
> with the HW provided N/CTS.
>
> This patch sets the proper N value for the
> given audio sample rate at the impacted frequencies.
> At other frequencies, it
On 8/6/2015 1:04 AM, Benjamin Tissoires wrote:
On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote:
On 7/29/2015 8:52 PM, Benjamin Tissoires wrote:
On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote:
why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you can
Hi,
On 30 July 2015 at 08:03, Maarten Lankhorst
wrote:
> This will cause drm_atomic_helper_page_flip and drm_mode_atomic_ioctl to
> fail with -EINVAL if a event is requested on a inactive crtc.
>
> Signed-off-by: Maarten Lankhorst
> ---
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/d
On 8/4/2015 5:03 PM, Animesh Manna wrote:
On 8/4/2015 4:50 PM, Sunil Kamath wrote:
On Monday 03 August 2015 09:55 PM, Animesh Manna wrote:
As csr firmware is taking care of loading the firmware,
so no need for driver to load again.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc:
On Thu, 06 Aug 2015 08:52:56 +0200,
libin.y...@intel.com wrote:
>
> From: Libin Yang
>
> On some Intel platforms, display audio need set N/CTS
> manually at some TMDS frequencies.
>
> Signed-off-by: Libin Yang
> ---
> sound/pci/hda/patch_hdmi.c | 7 +++
> 1 file changed, 7 insertions(+)
>
Mmio register access after dc6/dc5 entry is not allowed when
DC6 power states are enabled according to bspec (bspec-id 0527),
so enabling dc6 as the last call in suspend flow.
Before triggering dc6 a condition check added to check firmware
loading status. Removed the set call for firmware loading
Hey,
Op 06-08-15 om 11:47 schreef Daniel Stone:
> Hi,
>
> On 30 July 2015 at 08:03, Maarten Lankhorst
> wrote:
>> This will cause drm_atomic_helper_page_flip and drm_mode_atomic_ioctl to
>> fail with -EINVAL if a event is requested on a inactive crtc.
>>
>> Signed-off-by: Maarten Lankhorst
>> --
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work properly.
v1: Initial version.
v2: Based on review comment from
On Sun, May 04, 2014 at 04:48:24PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> This patch could help to reduce the time, 'struct_mutex' is kept
> locked during either the exec-buffer path or Page fault
> handling path as now the backing pages are requested from shmem layer
> without
Physically disconnecting a DP connector with an active MST stream
can lead to a kernel panic in intel_mst_disable_dp when calling
drm_dp_update_payload_part1. Examining the code it seems that the
port is freed while work to remove the connector is scheduled.
This probably means it's fine to skip c
This function always returned false because intel_connector->encoder
is always NULL. Instead use the attached encoder from atomic.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_dp_mst.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
Fully remove the MST connector from the atomic state, and remove the
early returns in check_*_state for MST connectors.
With atomic the state can be made consistent all the time.
Thanks to Sivakumar Thulasimani for the idea of using
drm_atomic_helper_set_config.
Changes since v1:
- Remove the MS
Right now dpms callbacks can still fiddle with the connector state,
but it can only turn connectors off.
This is remediated by only checking crtc->state->active when the
connector is active, and ignore crtc->state->active when the
connector is off.
connectors_active is no longer checked, and will
On Sun, May 04, 2014 at 04:48:25PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Moved the cache flush of the preallocated shmem pages outside
> the span of 'struct_mutex' lock. This shall not lead to any
> redundancy as the cache flush of the newly allocated pages
> will be done anyw
On Wed, Aug 05, 2015 at 06:32:01PM +0300, David Weinehall wrote:
> On Wed, Aug 05, 2015 at 10:59:00AM +0200, Daniel Vetter wrote:
> > On Tue, Aug 04, 2015 at 04:55:52PM +0300, David Weinehall wrote:
> > > VBT version 196 increased the size of common_child_dev_config. The parser
> > > code assumed t
On Wed, Aug 05, 2015 at 08:30:01PM +, Vivi, Rodrigo wrote:
> On Wed, 2015-08-05 at 10:07 +0200, Daniel Vetter wrote:
> > On Thu, Jul 30, 2015 at 04:26:39PM -0700, Rodrigo Vivi wrote:
> > > This is just a preparation patch to make clear what operation we
> > > are performing. There is no functio
On Wed, Aug 05, 2015 at 04:49:17PM +0100, Michel Thierry wrote:
> On 8/5/2015 4:31 PM, Daniel Vetter wrote:
> >On Wed, Jul 29, 2015 at 05:23:46PM +0100, Michel Thierry wrote:
> >>This transitional patch doesn't do much for the existing code. However,
> >>it should make upcoming patches to use the f
thanks for the change :)
Reviewed-by: Sivakumar Thulasimani
On 8/6/2015 5:17 PM, Maarten Lankhorst wrote:
Fully remove the MST connector from the atomic state, and remove the
early returns in check_*_state for MST connectors.
With atomic the state can be made consistent all the time.
Thank
On Wed, Aug 05, 2015 at 05:14:03PM +0100, Michel Thierry wrote:
> On 8/5/2015 5:01 PM, Daniel Vetter wrote:
> >On Wed, Jul 29, 2015 at 05:23:59PM +0100, Michel Thierry wrote:
> >>Otherwise it can overflow in 48-bit mode, and cause an incorrect
> >>exec_start.
> >>
> >>Before commit 5f19e2bffa63a91c
Hey,
Op 05-08-15 om 08:18 schreef Tomi Valkeinen:
> Hi,
>
> On 21/07/15 14:28, Maarten Lankhorst wrote:
>> In intel it's useful to keep track of some state changes with old
>> crtc state vs new state, for example to disable initial planes or
>> when a modeset's prevented during fastboot.
>>
>> Cc:
On Wed, Aug 05, 2015 at 05:14:33PM +0100, Michel Thierry wrote:
> On 8/5/2015 4:58 PM, Daniel Vetter wrote:
> >On Wed, Jul 29, 2015 at 05:24:01PM +0100, Michel Thierry wrote:
> >>There are some allocations that must be only referenced by 32-bit
> >>offsets. To limit the chances of having the first
On Thu, Aug 06, 2015 at 01:19:35PM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 06-08-15 om 11:47 schreef Daniel Stone:
> > Hi,
> >
> > On 30 July 2015 at 08:03, Maarten Lankhorst
> > wrote:
> >> This will cause drm_atomic_helper_page_flip and drm_mode_atomic_ioctl to
> >> fail with -EINVAL if a
On Wed, Aug 05, 2015 at 03:28:54PM -0300, Paulo Zanoni wrote:
> 2015-08-05 5:30 GMT-03:00 Daniel Vetter :
> > On Thu, Jul 30, 2015 at 06:20:28PM -0300, Paulo Zanoni wrote:
> >> From: Damien Lespiau
> >>
> >> Before this patch, we used the intel_display_power_{get,put} functions
> >> to make sure t
On Thu, Aug 06, 2015 at 01:47:35PM +0200, Maarten Lankhorst wrote:
> This function always returned false because intel_connector->encoder
> is always NULL. Instead use the attached encoder from atomic.
Note that you've broken this since you removed the updating of
intel_connector->encoder somewher
On Thu, Aug 06, 2015 at 01:47:37PM +0200, Maarten Lankhorst wrote:
> Physically disconnecting a DP connector with an active MST stream
> can lead to a kernel panic in intel_mst_disable_dp when calling
> drm_dp_update_payload_part1. Examining the code it seems that the
> port is freed while work to
We want to make sure that no one tries to acquire more locks and
states, and ww mutexes provide debug facilities for that. So use them.
v2: Only call acquire_done when ->atomic_check was successful to avoid
falling over an -EDEADLK (spotted by Maarten).
Cc: Rob Clark
Cc: Maarten Lankhorst
Signe
On Thu, Aug 06, 2015 at 06:17:28AM +0200, Maarten Lankhorst wrote:
> Op 06-08-15 om 00:25 schreef Daniel Vetter:
> > On Wed, Aug 5, 2015 at 8:13 PM, Maarten Lankhorst
> > wrote:
> >> Op 05-08-15 om 17:03 schreef Daniel Vetter:
> >>> On Wed, Aug 5, 2015 at 4:57 PM, Maarten Lankhorst
> >>> wrote:
>
On Wed, Aug 05, 2015 at 12:37:10PM +0200, Maarten Lankhorst wrote:
> The rest will be a noop anyway, since without modeset there will be
> no updated dplls and no modeset state to update.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 30 +++--
On Wed, Aug 05, 2015 at 12:36:58PM +0200, Maarten Lankhorst wrote:
> Mixed bag of fixes for -next now that the first merge happened.
> Patch series deals with getting rid of intel DPMS handling and
> making the state checker atomic.
>
> The state checker is now atomic and only checks the affected
On Wed, Aug 05, 2015 at 05:10:17PM -0300, Tiago Vignatti wrote:
> On 08/05/2015 04:08 AM, Daniel Vetter wrote:
> >On Tue, Aug 04, 2015 at 06:30:25PM -0300, Tiago Vignatti wrote:
> >Nah they don't have to be equal since the problem isn't that nothing goes
> >out to memory where the display can see i
On Thu, Aug 06, 2015 at 02:47:22PM +0530, Animesh Manna wrote:
>
>
> On 8/5/2015 2:35 PM, Daniel Vetter wrote:
> >On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote:
> >>Mmio register access after dc6/dc5 entry is not allowed when
> >>DC6 power states are enabled according to bspec (bs
On Thu, Aug 06, 2015 at 03:51:36PM +0800, Xiong Zhang wrote:
> From: Rodrigo Vivi
>
> There are OEMs using DDI-E out there,
> so let's enable it.
>
> Unfortunately there is no detection bit for DDI-E
> So we need to rely on VBT for that.
>
> I also need to give credits to Xiong since before sei
Op 06-08-15 om 14:59 schreef Daniel Vetter:
> On Thu, Aug 06, 2015 at 01:47:35PM +0200, Maarten Lankhorst wrote:
>> This function always returned false because intel_connector->encoder
>> is always NULL. Instead use the attached encoder from atomic.
> Note that you've broken this since you removed
If we encounter frequent problems with dp aux channel
communications, we end up spamming the dmesg with the
exact similar trace and status.
Inject a new backtrace only if we have new information
to share as otherwise we flush out all other important
stuff.
Signed-off-by: Mika Kuoppala
---
drive
Add WaDisableSbeCacheDispatchPortSharing:skl
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1c14233..1a
Hey,
Op 06-08-15 om 15:01 schreef Daniel Vetter:
> On Thu, Aug 06, 2015 at 01:47:37PM +0200, Maarten Lankhorst wrote:
>> Physically disconnecting a DP connector with an active MST stream
>> can lead to a kernel panic in intel_mst_disable_dp when calling
>> drm_dp_update_payload_part1. Examining th
On 8/5/2015 9:59 AM, Daniel Vetter wrote:
On Tue, Aug 04, 2015 at 04:55:52PM +0300, David Weinehall wrote:
VBT version 196 increased the size of common_child_dev_config. The parser
code assumed that the size of this structure would not change.
The modified code now copies the amount needed base
This register needs to be updated with masked writes.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 99bba8e..29347e7 100644
--- a/driv
Op 06-08-15 om 15:12 schreef Daniel Vetter:
> On Wed, Aug 05, 2015 at 12:37:10PM +0200, Maarten Lankhorst wrote:
>> The rest will be a noop anyway, since without modeset there will be
>> no updated dplls and no modeset state to update.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/
On Thu, Aug 06, 2015 at 02:59:10PM +0100, Michel Thierry wrote:
> On 8/5/2015 9:59 AM, Daniel Vetter wrote:
> >On Tue, Aug 04, 2015 at 04:55:52PM +0300, David Weinehall wrote:
> >>VBT version 196 increased the size of common_child_dev_config. The parser
> >>code assumed that the size of this struct
If idle to active bit is set, the rest of the fields
in CSQ are not valid.
Bail out early if this is the case in order to prevent
rest of the loop inspecting stale values.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dr
On Fri, Jul 10, 2015 at 02:10:55PM +0300, Antti Koskipaa wrote:
> An OEM may request increased I_boost beyond the recommended values
> by specifying an I_boost value to be applied to all swing entries for
> a port. These override values are specified in VBT.
>
> v2: rebase and remove unused iboost
On Thu, Aug 06, 2015 at 02:18:35PM +0200, Daniel Vetter wrote:
> On Wed, Aug 05, 2015 at 06:32:01PM +0300, David Weinehall wrote:
> > On Wed, Aug 05, 2015 at 10:59:00AM +0200, Daniel Vetter wrote:
> > > On Tue, Aug 04, 2015 at 04:55:52PM +0300, David Weinehall wrote:
> > > > VBT version 196 increas
On 8/6/2015 3:00 PM, Mika Kuoppala wrote:
This register needs to be updated with masked writes.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_
On 06/08/2015 14:51, Mika Kuoppala wrote:
Add WaDisableSbeCacheDispatchPortSharing:skl
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu
On 8/6/2015 6:48 PM, Daniel Vetter wrote:
On Thu, Aug 06, 2015 at 02:47:22PM +0530, Animesh Manna wrote:
On 8/5/2015 2:35 PM, Daniel Vetter wrote:
On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote:
Mmio register access after dc6/dc5 entry is not allowed when
DC6 power states are
"Siluvery, Arun" writes:
> On 06/08/2015 14:51, Mika Kuoppala wrote:
>> Add WaDisableSbeCacheDispatchPortSharing:skl
>>
>> Cc: Arun Siluvery
>> Signed-off-by: Mika Kuoppala
>> ---
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/dr
On 06/08/2015 15:45, Mika Kuoppala wrote:
"Siluvery, Arun" writes:
On 06/08/2015 14:51, Mika Kuoppala wrote:
Add WaDisableSbeCacheDispatchPortSharing:skl
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertion
On Thu, Aug 06, 2015 at 03:51:36PM +0800, Xiong Zhang wrote:
> From: Rodrigo Vivi
>
> There are OEMs using DDI-E out there,
> so let's enable it.
>
> Unfortunately there is no detection bit for DDI-E
> So we need to rely on VBT for that.
>
> I also need to give credits to Xiong since before sei
On Thu, Aug 06, 2015 at 05:08:55PM +0300, David Weinehall wrote:
> On Thu, Aug 06, 2015 at 02:59:10PM +0100, Michel Thierry wrote:
> > On 8/5/2015 9:59 AM, Daniel Vetter wrote:
> > >On Tue, Aug 04, 2015 at 04:55:52PM +0300, David Weinehall wrote:
> > >>VBT version 196 increased the size of common_c
On Thu, Aug 06, 2015 at 05:11:03PM +0300, David Weinehall wrote:
> On Fri, Jul 10, 2015 at 02:10:55PM +0300, Antti Koskipaa wrote:
> > An OEM may request increased I_boost beyond the recommended values
> > by specifying an I_boost value to be applied to all swing entries for
> > a port. These overr
On Thu, 2015-08-06 at 15:30 +0200, Daniel Vetter wrote:
> On Thu, Aug 06, 2015 at 03:51:36PM +0800, Xiong Zhang wrote:
> > From: Rodrigo Vivi
> >
> > There are OEMs using DDI-E out there,
> > so let's enable it.
> >
> > Unfortunately there is no detection bit for DDI-E
> > So we need to rely on
On Thu, Aug 06, 2015 at 08:08:58PM +0530, Animesh Manna wrote:
>
>
> On 8/6/2015 6:48 PM, Daniel Vetter wrote:
> >On Thu, Aug 06, 2015 at 02:47:22PM +0530, Animesh Manna wrote:
> >>
> >>On 8/5/2015 2:35 PM, Daniel Vetter wrote:
> >>>On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote:
>
On Thu, Aug 06, 2015 at 03:51:31PM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 06-08-15 om 15:01 schreef Daniel Vetter:
> > On Thu, Aug 06, 2015 at 01:47:37PM +0200, Maarten Lankhorst wrote:
> >> Physically disconnecting a DP connector with an active MST stream
> >> can lead to a kernel panic in
On Thu, 2015-08-06 at 17:14 +0200, Daniel Vetter wrote:
> On Thu, Aug 06, 2015 at 03:51:36PM +0800, Xiong Zhang wrote:
> > From: Rodrigo Vivi
> >
> > There are OEMs using DDI-E out there,
> > so let's enable it.
> >
> > Unfortunately there is no detection bit for DDI-E
> > So we need to rely on
On Thu, Aug 06, 2015 at 03:37:08PM +0200, Maarten Lankhorst wrote:
> Op 06-08-15 om 14:59 schreef Daniel Vetter:
> > On Thu, Aug 06, 2015 at 01:47:35PM +0200, Maarten Lankhorst wrote:
> >> This function always returned false because intel_connector->encoder
> >> is always NULL. Instead use the atta
On Thu, Aug 06, 2015 at 04:06:58PM +0200, Maarten Lankhorst wrote:
> Op 06-08-15 om 15:12 schreef Daniel Vetter:
> > On Wed, Aug 05, 2015 at 12:37:10PM +0200, Maarten Lankhorst wrote:
> >> The rest will be a noop anyway, since without modeset there will be
> >> no updated dplls and no modeset state
On Thu, Aug 06, 2015 at 03:25:55PM +0100, Michel Thierry wrote:
> On 8/6/2015 3:00 PM, Mika Kuoppala wrote:
> >This register needs to be updated with masked writes.
> >
> >Signed-off-by: Mika Kuoppala
> >---
> > drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deleti
On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> If idle to active bit is set, the rest of the fields
> in CSQ are not valid.
>
> Bail out early if this is the case in order to prevent
> rest of the loop inspecting stale values.
>
> Signed-off-by: Mika Kuoppala
Same questions he
On 8/6/2015 5:03 PM, Daniel Vetter wrote:
On Thu, Aug 06, 2015 at 03:25:55PM +0100, Michel Thierry wrote:
On 8/6/2015 3:00 PM, Mika Kuoppala wrote:
This register needs to be updated with masked writes.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed
On 8/6/2015 1:47 PM, Daniel Vetter wrote:
On Wed, Aug 05, 2015 at 05:14:33PM +0100, Michel Thierry wrote:
On 8/5/2015 4:58 PM, Daniel Vetter wrote:
On Wed, Jul 29, 2015 at 05:24:01PM +0100, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limi
From: Kausal Malladi
This patch adds atomic get property interface for Intel CRTC. This
interface will be used for get operation on any non-core DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_atomic.c | 8
drivers/gpu/drm/
From: Kausal Malladi
Color Management is an extension to Kernel display framework. It allows
abstraction of hardware color correction and enhancement capabilities by
virtue of DRM properties.
This patch initializes color management framework by :
1. Introducing new pointers in DRM mode_config st
This patch set adds Color Manager implementation in DRM layer. Color Manager is
an extension in DRM framework to support color correction/enhancement. Various
Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a
From: Kausal Malladi
This patch adds atomic set property interface for Intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_atomic.c | 9 +
drivers/gpu/drm/i915/int
From: Kausal Malladi
I915 driver registers gamma correction as palette correction
property with DRM layer. This patch adds set_property() and get_property()
handlers for pipe level gamma correction.
The set function attaches the Gamma correction blob to CRTC state, these
values will be committed
From: Kausal Malladi
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
include/
From: Kausal Malladi
The DRM color management framework is targeting various hardware
platforms and drivers. Different platforms can have different color
correction and enhancement capabilities.
A commom user space application can query these capabilities using the
DRM property interface. Each d
From: Kausal Malladi
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
From: Kausal Malladi
As per Color Manager design, each driver is responsible to load its
palette color correction and enhancement capabilities in the form of
a DRM blob property, so that user space can query and read.
This patch does the following:
1. Create new files intel_color_manager(.c/.h)
From: Kausal Malladi
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Add
From: Kausal Malladi
This patch adds set_property and get_property handlers for deGamma
color correction capability at Pipe level.
Set function just attaches the deGamma correction blob to CRTC state, which
will be later commited in the atomic commit path.
Signed-off-by: Shashank Sharma
Signed
From: Kausal Malladi
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC corre
From: Kausal Malladi
This patch initializes gamma color correction proeprty
for Gen8 and higher platforms.
It does the following :
1. Load pipe Gamma color correction capabilities for BDW/SKL/BXT
2. Attach the color properties to CRTC
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Mallad
From: Kausal Malladi
This patch adds set and get property handlers for CSC color correction
and enhancement capability at Pipe level on CHV/BSW platform. The set
function just attaches the CSC blob to CRTC state, that later
gets committed using atomic path.
Signed-off-by: Shashank Sharma
Signed
From: Kausal Malladi
BDW/SKL/BXT supports DeGamma color correction feature, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platfor
From: Kausal Malladi
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/
From: Kausal Malladi
CHV/BSW supports DeGamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
From: Kausal Malladi
BDW/SKL/BXT platforms support various Gamma correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. 10-bit Split Gamma mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values for BDW/SKL/BXT
platform
2. A
From: Kausal Malladi
Color Manager framework defines a color correction property for color
space transformation and Gamut mapping. This property is called CTM (Color
Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents
We have for a long time been ultra-paranoid about the situation whereby
we hand back pages to the system that have been written to by the GPU
and potentially simultaneously by the user through a CPU mmapping. We
can relax this restriction when we know that the cache domain tracking
is true and ther
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