On 8/7/2015 1:37 PM, Daniel Vetter wrote:
On Thu, Aug 06, 2015 at 05:43:39PM +0100, Chris Wilson wrote:
We have for a long time been ultra-paranoid about the situation whereby
we hand back pages to the system that have been written to by the GPU
and potentially simultaneously by the user
On 8/9/2015 4:25 PM, Chris Wilson wrote:
On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote:
On 8/7/2015 1:37 PM, Daniel Vetter wrote:
I presume though you only want to avoid clflush when actually purging an
object, so maybe we can keep this by purging the shmem backing node first
On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote:
On 8/7/2015 1:37 PM, Daniel Vetter wrote:
I presume though you only want to avoid clflush when actually purging an
object, so maybe we can keep this by purging the shmem backing node first
and checking here for __I915_MADV_PURGED
We follow the VBT as to whether a DDI port is used for eDP and if so, do
not attach a HDMI encoder to it. However there are machines for which
the VBT eDP flag is a lie (shocking!) and we fail to detect a eDP link.
Furthermore, on those machines the HDMI is connected to that DDI port
but we ignore
Hi,
On Sun, Aug 09, 2015 at 01:12:53PM +0100, Chris Wilson wrote:
We follow the VBT as to whether a DDI port is used for eDP and if so, do
not attach a HDMI encoder to it. However there are machines for which
the VBT eDP flag is a lie (shocking!) and we fail to detect a eDP link.
Furthermore,
On Sun, Aug 09, 2015 at 05:11:52PM +0530, Goel, Akash wrote:
On 8/9/2015 4:25 PM, Chris Wilson wrote:
On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote:
On 8/7/2015 1:37 PM, Daniel Vetter wrote:
I presume though you only want to avoid clflush when actually purging an
object, so
On 8/9/2015 6:19 PM, Chris Wilson wrote:
On Sun, Aug 09, 2015 at 05:11:52PM +0530, Goel, Akash wrote:
On 8/9/2015 4:25 PM, Chris Wilson wrote:
On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote:
On 8/7/2015 1:37 PM, Daniel Vetter wrote:
I presume though you only want to avoid
2015-8-10 上午11:15於 Yang, Libin libin.y...@intel.com寫道：
Hi Raymond,
}
+ if (is_haswell_plus(codec)) {
+ if (acomp acomp-ops acomp-ops-set_ncts)
+ acomp-ops-set_ncts(acomp-dev, per_pin-
pin_nid - 4,
Please describe more how
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Lukas Wunner
Hi,
On Sun, Aug 09, 2015 at 01:12:53PM +0100, Chris Wilson wrote:
We follow the VBT as to whether a DDI port is used for eDP and if so,
do not attach a HDMI encoder to
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
With HPD support added for all ports including PORT_A, setting hpd_pin will
result in enabling of hpd to edp as well. There is no need to enable HPD on
PORT_A hence this patch removes
Hi Raymond,
}
+ if (is_haswell_plus(codec)) {
+ if (acomp acomp-ops acomp-ops-set_ncts)
+ acomp-ops-set_ncts(acomp-dev, per_pin-
pin_nid - 4,
Please describe more how pin_nid - 4 is supposed to work. Also...
OK, I see.
+
Hi Daniel,
That patch was already merged:
http://lists.freedesktop.org/archives/intel-gfx/2015-July/071142.html
For SKL, the above patch helped in getting the correct ISR bits set.
One option is to enable the HDMI optimization from VLV onwards.
I don't have an ivb machine to try out the issue.
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
Also remove redundant comments.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 10 +++---
1 file changed, 3 insertions(+), 7
On 7/14/2015 5:21 PM, Sonika Jindal wrote:
Adding this for SKL onwards.
v2: Adding checks for VLV/CHV as well. Reusing old ibx and g4x functions
to check digital port status. Adding a separate function to get bxt live
status (Daniel)
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
Also remove redundant comments.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 02b9e73..9b9533a
This series adds BXT HPD pin swap WA for A0/A1 by setting right hpd_pin
and irq_port for PORT_B.
Sonika Jindal (3):
drm/i915: Dont enable hpd for eDP
drm/i915/bxt: Add HPD support for DDIA
drm/i915/bxt: WA for swapped HPD pins in A stepping
drivers/gpu/drm/i915/i915_irq.c | 10
With HPD support added for all ports including PORT_A, setting hpd_pin will
result in enabling of hpd to edp as well. There is no need to enable HPD on
PORT_A hence this patch removes hpd_pin update for PORT_A, where edp will
be connected. it can be added back when required
Signed-off-by: Sonika
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and removing the edp HPD logic because port A HPD is not
present(Imre)
v3: Rebased on top of Imre's patchset for enabling
Hello,
We launched Intel GPU Tools on 6 platforms: Skylake-Y, Braswell-M,
Broadwell-U, Baytrail M and T, Haswell-U to validate tag
drm-intel-testing-2015-07-31 (kernel 4.2-rc4).
Here are the results:
New bugs reported:
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