On Fri, Aug 14, 2015 at 12:35:23PM +0200, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The gtt.stolen_size field is of type size_t, and so should be printed
using %zu to avoid build warnings on either 32-bit and 64-bit builds.
Or better would be to convert stolen.size to u32
On Wed, 12 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Aug 12, 2015 at 04:02:17PM +0300, Ville Syrjälä wrote:
On Wed, Aug 12, 2015 at 05:31:55PM +0530, Sivakumar Thulasimani wrote:
On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 11:32:52AM +0530,
On 8/14/2015 12:29 PM, Jani Nikula wrote:
On Wed, 12 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Aug 12, 2015 at 04:02:17PM +0300, Ville Syrjälä wrote:
On Wed, Aug 12, 2015 at 05:31:55PM +0530, Sivakumar Thulasimani wrote:
On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
On Fri, Jul
There is currently conflicting documentation on which steppings the
workaround is needed, up to C vs. forever. However there is post-C
stepping hardware that doesn't report port presence on DDI A, leading to
black screen on eDP. Assume the strap isn't connected, and try to enable
DDI A on these
On Thu, 13 Aug 2015, Xiong Zhang xiong.y.zh...@intel.com wrote:
Signed-off-by: Xiong Zhang xiong.y.zh...@intel.com
Even for a small patch like this, your commit message is inadequate.
First, it's obvious from the code that you're adding a break for one
case. Instead, you should explain what bug
On Fri, Aug 14, 2015 at 12:13:04PM +1000, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
This is validating from the wrong index.
testing with KASAN found it.
Reported-by: Dave Jones da...@codemonkey.org.uk
Signed-off-by: Dave Airlie airl...@redhat.com
---
On Fri, 2015-08-14 at 16:09 +0300, Ville Syrjälä wrote:
On Fri, Aug 14, 2015 at 01:03:24PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported
On pe, 2015-08-14 at 14:11 +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 03:38:57PM +0300, Imre Deak wrote:
Due to a coherency issue on BXT A steppings we can't guarantee a
coherent view of cached GPU mappings, so fall back to uncached mappings.
Note that this still won't fix cases
On pe, 2015-08-14 at 13:49 +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 03:38:55PM +0300, Imre Deak wrote:
This is a v2 of [1]. Since v1 the HW team confirmed that there is an
HW issue in A steppings with the GPU/CPU snoop logic, which explains why
we need this workaround.
I've
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7141
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On pe, 2015-08-14 at 14:12 +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 03:38:56PM +0300, Imre Deak wrote:
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion time is not
seen by the CPU. This results in
On Fri, Aug 14, 2015 at 04:26:29PM +0300, Imre Deak wrote:
On pe, 2015-08-14 at 13:49 +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 03:38:55PM +0300, Imre Deak wrote:
This is a v2 of [1]. Since v1 the HW team confirmed that there is an
HW issue in A steppings with the GPU/CPU snoop
On Fri, Aug 14, 2015 at 08:40:47AM +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 12:13:04PM +1000, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
This is validating from the wrong index.
testing with KASAN found it.
Reported-by: Dave Jones da...@codemonkey.org.uk
On Wed, Aug 12, 2015 at 09:34:54PM +0300, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 03:13:52PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
On Thursday, August 13, 2015 10:39:08 PM Sedat Dilek wrote:
--f46d04447e7fc2306e051d3753a5
Content-Type: text/plain; charset=UTF-8
On Thu, Aug 13, 2015 at 6:53 PM, Hans de Goede hdego...@redhat.com wrote:
Before this commit, the following would happen:
a)
On Wed, Aug 12, 2015 at 06:44:17PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
As with ILK/SNB wire up the port A HPD on IVB/HSW.
This might be more important on HSW with PSR. BSpec tells us that if the
automagic link training performed by
On Wed, Aug 12, 2015 at 06:33:55PM -0300, Paulo Zanoni wrote:
We need to test those pixel formats on the FBC code, so let's make
sure the drawing library works on them first.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
gtkdoc update seems to be missing for the igt_draw_rect change.
On 08/13/2015 01:29 AM, Tiago Vignatti wrote:
Hi,
The idea is to create a GEM bo in one process and pass the prime handle of the
it to another process, which in turn uses the handle only to map and write.
This could be useful for Chrome OS architecture, where the Web content
(unpriviledged
On Fri, Aug 14, 2015 at 10:53:17AM +0300, Jani Nikula wrote:
There is currently conflicting documentation on which steppings the
workaround is needed, up to C vs. forever. However there is post-C
stepping hardware that doesn't report port presence on DDI A, leading to
black screen on eDP.
On Thu, Aug 13, 2015 at 04:51:37PM -0700, Bob Paauwe wrote:
When reducing a xy reflection to a 180 degree rotation, make sure
only one rotation bit is set. Also by rotating the bit left, we
can support cases where xy reflection happens with 90/270 degree
rotation.
Signed-off-by: Bob Paauwe
On Wed, Aug 12, 2015 at 07:04:22PM +0300, Ville Syrjälä wrote:
On Mon, Jul 06, 2015 at 03:09:59PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
While working on CHV DPIO powergating I relized DP .compute_config() was
clobbering lane_count
Looks good to me.
Reviewed-by: Sonika Jindal sonika.jin...@intel.com
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Sivakumar Thulasimani
Sent: Friday, August 7, 2015 3:15 PM
To: dan...@ffwll.ch; intel-gfx@lists.freedesktop.org
Subject:
On Wed, Aug 12, 2015 at 09:24:01PM +0300, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 03:13:57PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
On Wed, Aug 12, 2015 at 09:49:12PM +0300, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 03:13:58PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
On Thu, 13 Aug 2015, David Weinehall david.weineh...@linux.intel.com wrote:
On Wed, Aug 12, 2015 at 05:19:35PM +0300, Jani Nikula wrote:
On Wed, 12 Aug 2015, David Weinehall david.weineh...@linux.intel.com wrote:
Some more fixup is needed; the bits from Antti's patch
that actually expanded
On Wed, Aug 12, 2015 at 07:35:10PM -0700, O'Rourke, Tom wrote:
On Wed, Aug 12, 2015 at 07:57:37AM -0700, Gordon, David S wrote:
On 12/08/15 15:43, Dave Gordon wrote:
This patch series enables command submission via the GuC. In this mode,
instead of the host CPU driving the execlist port
On 13.08.2015 16:14, David Weinehall wrote:
On Wed, Aug 12, 2015 at 05:19:35PM +0300, Jani Nikula wrote:
On Wed, 12 Aug 2015, David Weinehall david.weineh...@linux.intel.com wrote:
Some more fixup is needed; the bits from Antti's patch
that actually expanded the struct to fully fit the newer
On Thu, Aug 13, 2015 at 01:31:41PM -0700, Jesse Barnes wrote:
git clean fixes this all, at least over here git status is clean.
-Daniel
---
.gitignore | 3 +++
tests/.gitignore | 13 +
tools/.gitignore | 8
3 files changed, 24 insertions(+)
diff --git
Hi,
On 13-08-15 16:33, Hans de Goede wrote:
Hi,
On 12-08-15 21:26, Ville Syrjälä wrote:
On Mon, Aug 10, 2015 at 08:29:00PM +0200, Sedat Dilek wrote:
On Sat, Aug 1, 2015 at 2:23 PM, Sedat Dilek sedat.di...@gmail.com wrote:
On Mon, Jul 27, 2015 at 12:33 AM, Sedat Dilek sedat.di...@gmail.com
On Thu, Aug 13, 2015 at 02:57:38AM +, Zhang, Xiong Y wrote:
On Wed, Aug 12, 2015 at 06:39:34PM +0800, Xiong Zhang wrote:
DDI-E doesn't have the correspondent GMBUS pin.
We rely on VBT to tell us which one it being used instead.
The DVI/HDMI on shared port couldn't exist.
On Wed, Aug 12, 2015 at 04:40:03PM +0100, Dave Gordon wrote:
On 11/08/15 15:44, Arun Siluvery wrote:
From: Mika Kuoppala mika.kuopp...@intel.com
Prevent leaking the if scoping by containing the WA_REG
macro inside its own scope.
Reported-by: Arun Siluvery arun.siluv...@linux.intel.com
On Wed, Aug 12, 2015 at 04:41:13PM +0100, Dave Gordon wrote:
On 11/08/15 15:44, Arun Siluvery wrote:
From Gen9, Push constant instruction parsing behaviour varies according to
whether set shader is enabled or not. If we want legacy behaviour then it
can be achieved by disabling set shader.
On Thu, Aug 13, 2015 at 03:49:35PM -0700, Ben Widawsky wrote:
On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas Lahtinen wrote:
Hi,
On ke, 2015-08-12 at 18:35 -0700, Ben Widawsky wrote:
On Wed, Aug 12, 2015 at 03:10:18PM +0300, Joonas Lahtinen wrote:
On ke, 2015-08-12 at 12:26 +0100,
On Wed, Aug 12, 2015 at 03:43:36PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
This fetches the required firmware image from the filesystem,
then loads it into the GuC's memory via a dedicated DMA engine.
This patch is derived from GuC loading work originally done by
Vinit
On Fri, Aug 14, 2015 at 08:27:45AM +, Jindal, Sonika wrote:
Looks good to me.
Reviewed-by: Sonika Jindal sonika.jin...@intel.com
Queued for -next, thanks for the patch.
-Daniel
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
On Thu, Aug 13, 2015 at 01:37:49PM +0300, Timo Aaltonen wrote:
On 13.08.2015 13:36, Timo Aaltonen wrote:
On 13.08.2015 13:00, Xiong Zhang wrote:
Signed-off-by: Xiong Zhang xiong.y.zh...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff
On 08/14/2015 05:32 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:30PM -0700, Jesse Barnes wrote:
Need some LRC tests in the 'basic' subset, and this is a good simple
one.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
This is just a testcase for a very specific lrc corner
On 08/14/2015 05:33 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:31PM -0700, Jesse Barnes wrote:
We should be able to create small and moderate sized objects quickly and
without errors.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
They're all super-fast basic testcases
On 08/14/2015 05:29 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:29PM -0700, Jesse Barnes wrote:
debugfs may not be mounted, but sysfs should always be restored after
suspend or hibernate.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
We already have a suspend/resume
On 08/14/2015 05:41 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:34PM -0700, Jesse Barnes wrote:
These simple tests should always pass.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Imo shouldn't be part of the basic set, they thrash the machine quite
badly. Especially
The ENODEV return value was introduced to the GEM_SET_CACHING ioctl to
mean that the given platform doesn't support the requested caching level
(currently only due to a HW issues on BXT A steppings). Handle this as
the other cases where we want to skip the related subtests.
Signed-off-by: Imre
git clean updates the .gitignore file? Not having to run git clean is the
whole point of this patch...
On 08/14/2015 01:09 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:41PM -0700, Jesse Barnes wrote:
git clean fixes this all, at least over here git status is clean.
-Daniel
---
---
tests/core_getversion.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/core_getversion.c b/tests/core_getversion.c
index f994315..2f481c9 100644
--- a/tests/core_getversion.c
+++ b/tests/core_getversion.c
@@ -37,7 +37,7 @@ igt_simple_main
int fd;
---
tests/core_get_client_auth.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/core_get_client_auth.c b/tests/core_get_client_auth.c
index 92313f9..3518bb7 100644
--- a/tests/core_get_client_auth.c
+++ b/tests/core_get_client_auth.c
@@ -84,7 +84,7 @@ igt_main
{
On 08/14/2015 05:19 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:24PM -0700, Jesse Barnes wrote:
There was a lot of duplication going on... Mark as basic while we're at
it as these should never fail.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
tests/Makefile.sources
On 08/14/2015 05:27 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:28PM -0700, Jesse Barnes wrote:
Fundamental and simple functionality.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Mark entire testcase as basic instead to catch future extensions?
getparams should always
The drm_open_driver*() functions replace the drm_open_any*() functions and
provide the same utility, but in a way that is platform agnostic, not
intel-specific. This opens the path for adopting intel-gpu-tools to non-intel
platforms.
This commit renames the calls and adds the chipset parameter
Changes since last version of patch:
Now using the core_* tests as demonstrations rather than drm_read.
Micah Fedke (7):
lib: adding drm_open_driver() interface
convert drm_open_any*() calls to drm_open_driver*(DRIVER_INTEL) calls
with cocci
lib: remove support for deprecated
---
tests/core_getstats.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/core_getstats.c b/tests/core_getstats.c
index cdab0e5..6f6a4ee 100644
--- a/tests/core_getstats.c
+++ b/tests/core_getstats.c
@@ -48,7 +48,7 @@ igt_simple_main
int fd, ret;
On 08/14/2015 05:22 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:26PM -0700, Jesse Barnes wrote:
Reduces runtime a lot...
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
tests/drv_module_reload_basic | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Apply the new API to all call sites within the test suite using the following
semantic patch:
// Semantic patch for replacing drm_open_any* with arch-specific
drm_open_driver* calls
@@
identifier i =~ \bdrm_open_any\b;
@@
- i()
+ drm_open_driver(DRIVER_INTEL)
@@
identifier i =~
---
tests/core_getclient.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/core_getclient.c b/tests/core_getclient.c
index d82e349..5293741 100644
--- a/tests/core_getclient.c
+++ b/tests/core_getclient.c
@@ -39,7 +39,7 @@ igt_simple_main
int fd, ret;
Signed-off-by: Micah Fedke micah.fe...@collabora.co.uk
---
lib/drmtest.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/lib/drmtest.h b/lib/drmtest.h
index dcb0c34..41ddbe7 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -41,12 +41,6 @@
#define OPEN_ANY_GPU 0x1
#define DRIVER_INTEL
On 08/14/2015 05:26 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:27PM -0700, Jesse Barnes wrote:
They're testing basic functionality and don't involve stress or race
induction.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
These are more stress-tests in nature I think. For
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion time is not
seen by the CPU. This results in __i915_wait_request seeing the stale
seqno and not completing the request (not considering the lost
interrupt/GPU reset
Due to a coherency issue on BXT A steppings we can't guarantee a
coherent view of cached (CPU snooped) GPU mappings, so fail such
requests. User space is supposed to fall back to uncached mappings in
this case.
v2:
- limit the WA to A steppings, on later stepping this HW issue is fixed
v3:
-
On 08/14/2015 05:44 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:36PM -0700, Jesse Barnes wrote:
Need some simple vblank coverage in the BAT list.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
This testcase relies upon fbcon to have enabled pipe 0, which means it
On 08/14/2015 05:50 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:38PM -0700, Jesse Barnes wrote:
These always need to pass for basic PM functionality.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
tests/pm_rpm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Hi Mika,
On Fri, Aug 14, 2015 at 01:03:24PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we
The PIPE.STAT register contains some interrupt status bits per pipe, and
if assert cause the corresponding bit in the IIR to be asserted (thus
raising an interrupt). When handling an interrupt, we should clear the
PIPE.STAT generator first before clearing the IIR so that we do not miss
events or
On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
Only internal eDP, LVDS, DVI screen could set scalling mode, some
customers need to set scalling mode for external DP, HDMI, VGA screen.
Let's fulfill this.
On 08/14/2015 09:01 AM, Daniel Vetter wrote:
On Fri, Aug 14, 2015 at 08:29:40AM -0700, Jesse Barnes wrote:
On 08/14/2015 05:29 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:29PM -0700, Jesse Barnes wrote:
debugfs may not be mounted, but sysfs should always be restored after
suspend
On 08/13/2015 08:20 PM, Jonathan Corbet wrote:
On Thu, 13 Aug 2015 20:09:35 -0300
Danilo Cesar Lemes de Paula danilo.ce...@collabora.co.uk wrote:
Did you find time to take a look on this?
No. Just when I thought things couldn't get crazier, my laptop died.
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7142
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -2
Hi Dave,
drm-intel-next-2015-07-31:
- kerneldoc for tiling/swizzling/fencing code
- bxt hpd port A w/a
- various other fixes all over
... not much, everyone's on vacation.
Cheers, Daniel
The following changes since commit e0548f1979bfee900fb0671a5dd3a2f217dce5df:
drm/i915: Update
On Fri, Aug 14, 2015 at 06:43:30PM +0300, Imre Deak wrote:
Due to a coherency issue on BXT A steppings we can't guarantee a
coherent view of cached (CPU snooped) GPU mappings, so fail such
requests. User space is supposed to fall back to uncached mappings in
this case.
v2:
- limit the WA
On 08/14/2015 05:56 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:39PM -0700, Jesse Barnes wrote:
Simple variants that don't do multiple output or interruptible testing.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
tests/kms_flip.c | 11 ++-
1 file changed, 10
On Fri, Aug 14, 2015 at 06:35:27PM +0300, Imre Deak wrote:
By running igt/store_dword_loop_render on BXT we can hit a coherency
problem where the seqno written at GPU command completion time is not
seen by the CPU. This results in __i915_wait_request seeing the stale
seqno and not completing
On 08/14/2015 09:07 AM, Daniel Vetter wrote:
On Fri, Aug 14, 2015 at 08:20:22AM -0700, Jesse Barnes wrote:
git clean updates the .gitignore file? Not having to run git clean is the
whole point of this patch...
I looked at this patch first, but later noticed that you have a few
renames
On Mon, Jun 16, 2014 at 04:11:00PM +0100, oscar.ma...@intel.com wrote:
From: Oscar Mateo oscar.ma...@intel.com
Otherwise, we might receive a new interrupt before we have time to
ack the first one, eventually missing it.
Without an atomic XCHG operation with mmio space, this patch merely
This commit is essentially a rewrite of drm/i915: Check pixel format
for fbc from Ville Syrjälä. The idea is the same, but the code is
different due to all the changes that happened since his original
patch. So any bugs are due to my bad rewrite.
Testcases:
I only tested this on BDW, but since the register description is the
same ever since gen4, let's assume that all gens take the same
register format. If that's not true, then hopefully someone will
bisect a bug to this patch and we'll fix it.
Notice that the wrong fence offset register just means
The spec says the register should have that value for the entire time
that FBC is enabled, so apply the WA before we enable FBC.
Notice that we also have this WA for ILK/SNB, but it is implemented at
init_clock_gating(). I could move the IVB/HSW/BDW WA code to
init_clock_gating() too, but since
BSpec says we shouldn't enable FBC on BDW when the pipe pixel rate
exceeds 95% of the core display clock.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_fbc.c | 8
2 files changed, 9 insertions(+)
diff --git
And also print the threshold. I was surprised to see a log message
claiming the CFB size was 32mb when there was less than 24mb available
for it.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Always update the currrent crtc, fb and vertical offset after calling
enable_fbc. We were forgetting to do so along the failure paths when
enabling fbc synchronously. Fix this with a new helper to enable_fbc()
and update the state simultaneously.
v2: Improve commit message (Chris).
Hello
This series contains tons of bug fixes for FBC. Some of the patches on this
series have seen the mailing list a few times already. With this series applied,
my BDW machine passes all the FBC tests that are on IGT.
This means we could even try to enable FBC on BDW by default, but I won't
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7150
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires
benjamin.tissoi...@redhat.com wrote:
On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote:
On 7/29/2015 8:52 PM, Benjamin Tissoires wrote:
On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote:
why not detect reverse in
This reverts commit 0ffb0ff283cca16f72caf29c44496d83b0c291fb.
Technology has evolved and now we have eDP panels with 3200x1800
resolution. In the meantime, the BIOS guys didn't change the default
32mb for stolen memory. And we can't assume our users will be able to
increase the default stolen
If we want to try to enable FBC by default on any platform we need to
be on the safe side and disable it in case we get an underrun while
FBC is enabled on the corresponding pipe. We currently already have
other reasons for FIFO underruns on our driver, but the ones I saw
with FBC lead to black
This WA is only for HSW/BDW.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index b76c19f..5dfe460 100644
---
Keep searching in case the candidate has a NULL primary fb. This is
only relevant for the platforms that don't have the pipe_a_only
restriction.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
We were considering the whole framebuffer height, but the spec clearly
says that we should only consider the active display height size.
On my current testing machine, this moves us from 124 successes and
502 skips to 209 successes and 417 skips on kms_frontbuffer_tracking
--fbc-only. The high
We used to have this bug in the past, but now that we properly track
the size of the CFB, we don't have it anymore. Still, add the WARN
just to make sure we don't go back to the bad state.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_fbc.c | 2 ++
1 file
I could only find the restrictions for HSW+, but I think it's safe to
assume that the older platforms also can't support the configurations
HSW can't support. The older platforms probably have additional
restrictions, so we need to figure out those and implement them later.
Let's not block HSW+
The FBC hardware for these platforms doesn't have access to the
bios_reserved range, so it always assumes the maximum (8mb) is used.
So avoid this range while allocating.
This solves a bunch of FIFO underruns that happen if you end up
putting the CFB in that memory range. On my machine, with 32mb
Sorry, but I don't get how this enables power_well_2 as well. I just see it
enabling ddi A/E as the other.
Maybe Paulo or Imre are the best one to review this.
On Thu, Aug 13, 2015 at 2:54 AM Xiong Zhang xiong.y.zh...@intel.com wrote:
From B spec, DDI_E port belong to PowerWell 2, but
DDI_E
Hi Daniel,
On 08/13/2015 04:04 AM, Daniel Vetter wrote:
On Wed, Aug 12, 2015 at 08:29:14PM -0300, Tiago Vignatti wrote:
+ /* Map too big */
+ handle = gem_create(fd, BO_SIZE);
+ fill_bo(handle, BO_SIZE);
+ dma_buf_fd = prime_handle_to_fd(fd, handle);
+
On 11 August 2015 at 17:54, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
The port is removed synchronously, but the connector delayed.
This causes a use after free which can cause a kernel BUG with
slug_debug=FPZU. This is fixed by freeing the port after the
connector.
Where is
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7152
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7155
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
On Fri, Aug 14, 2015 at 08:29:40AM -0700, Jesse Barnes wrote:
On 08/14/2015 05:29 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:29PM -0700, Jesse Barnes wrote:
debugfs may not be mounted, but sysfs should always be restored after
suspend or hibernate.
Signed-off-by: Jesse
On Fri, Aug 14, 2015 at 08:31:01AM -0700, Jesse Barnes wrote:
On 08/14/2015 05:32 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:30PM -0700, Jesse Barnes wrote:
Need some LRC tests in the 'basic' subset, and this is a good simple
one.
Signed-off-by: Jesse Barnes
On Fri, Aug 14, 2015 at 08:48:42AM -0700, Jesse Barnes wrote:
On 08/14/2015 05:50 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:38PM -0700, Jesse Barnes wrote:
These always need to pass for basic PM functionality.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
On Fri, Aug 14, 2015 at 08:31:53AM -0700, Jesse Barnes wrote:
On 08/14/2015 05:33 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:31PM -0700, Jesse Barnes wrote:
We should be able to create small and moderate sized objects quickly and
without errors.
Signed-off-by: Jesse Barnes
On Fri, Aug 14, 2015 at 08:20:22AM -0700, Jesse Barnes wrote:
git clean updates the .gitignore file? Not having to run git clean is the
whole point of this patch...
I looked at this patch first, but later noticed that you have a few
renames where you don't update the .gitignore.
On
On Fri, Aug 14, 2015 at 08:21:12AM -0700, Jesse Barnes wrote:
On 08/14/2015 05:19 AM, Daniel Vetter wrote:
On Thu, Aug 13, 2015 at 01:31:24PM -0700, Jesse Barnes wrote:
There was a lot of duplication going on... Mark as basic while we're at
it as these should never fail.
Signed-off-by:
From: Thierry Reding tred...@nvidia.com
The gtt.stolen_size field is of type size_t, and so should be printed
using %zu to avoid build warnings on either 32-bit and 64-bit builds.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
1 file changed,
On Thu, Aug 13, 2015 at 02:57:38AM +, Zhang, Xiong Y wrote:
On Wed, Aug 12, 2015 at 06:39:34PM +0800, Xiong Zhang wrote:
DDI-E doesn't have the correspondent GMBUS pin.
We rely on VBT to tell us which one it being used instead.
The DVI/HDMI on shared port couldn't
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