On Wed, 19 Aug 2015, Jani Nikula wrote:
> On Wed, 19 Aug 2015, Daniel Vetter wrote:
>> On Tue, Aug 18, 2015 at 10:00 AM, Ville Syrjälä
>> wrote:
>>> On Tue, Aug 18, 2015 at 09:58:57AM -0700, Daniel Vetter wrote:
On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
> This reverts
>
On Tue, 18 Aug 2015, Ville Syrjälä wrote:
> On Tue, Aug 18, 2015 at 02:28:55PM +0300, Jani Nikula wrote:
>> commit 75067ddecf21271631bc018d2fb23ddd09b66aae
>> Author: Antti Koskipaa
>> Date: Fri Jul 10 14:10:55 2015 +0300
>>
>> drm/i915: Per-DDI I_boost override
>>
>> increased size of un
On Wed, 19 Aug 2015, Daniel Vetter wrote:
> On Tue, Aug 18, 2015 at 10:00 AM, Ville Syrjälä
> wrote:
>> On Tue, Aug 18, 2015 at 09:58:57AM -0700, Daniel Vetter wrote:
>>> On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
>>> > This reverts
>>> >
>>> > commit 047fe6e6db9161e69271f56daaafdaf2add
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
With DPIO powergating active the DPLL can't be accessed unless
something else is keeping the common lane in the channel on.
That means the PPS kick procedure could fail to enable the PLL.
Power up some data lane
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the D
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Powergate the PHY lanes when they're not needed. For HDMI all four lanes
are needed always, but for DP we can enable only the needed lanes. To
power down the unused lanes we use some power down override bits in t
On Tue, Aug 18, 2015 at 05:25:55PM +0300, Joonas Lahtinen wrote:
> Hi,
>
> On pe, 2015-08-14 at 10:58 +0200, Daniel Vetter wrote:
> > On Thu, Aug 13, 2015 at 03:49:35PM -0700, Ben Widawsky wrote:
> > > On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas Lahtinen wrote:
> > > > Hi,
> > > >
> > > > On
Em Sáb, 2015-08-15 às 09:24 +0100, Chris Wilson escreveu:
> On Fri, Aug 14, 2015 at 06:34:20PM -0300, Paulo Zanoni wrote:
> > This reverts commit 0ffb0ff283cca16f72caf29c44496d83b0c291fb.
> >
> > Technology has evolved and now we have eDP panels with 3200x1800
> > resolution. In the meantime, the
Em Sáb, 2015-08-15 às 09:29 +0100, Chris Wilson escreveu:
> On Fri, Aug 14, 2015 at 06:34:13PM -0300, Paulo Zanoni wrote:
> > The FBC hardware for these platforms doesn't have access to the
> > bios_reserved range, so it always assumes the maximum (8mb) is
> > used.
> > So avoid this range while a
From: Alex Dai
If rc6 is enabled, notify GuC so it can do proper forcewake before
command submission.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_submission.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/driver
From: Alex Dai
The firmware layout changes that now it only has css header +
uCode + RSA signature. Plus, other trivial changes to support
GuC V4.3.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 11 ---
drivers/gpu/drm/i915/intel_guc_loader.c | 17 ++
On Tue, Aug 18, 2015 at 10:00 AM, Ville Syrjälä
wrote:
> On Tue, Aug 18, 2015 at 09:58:57AM -0700, Daniel Vetter wrote:
>> On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
>> > This reverts
>> >
>> > commit 047fe6e6db9161e69271f56daaafdaf2add023b1
>> > Author: David Weinehall
>> > Date: Tue
On Tue, Aug 18, 2015 at 09:58:57AM -0700, Daniel Vetter wrote:
> On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
> > This reverts
> >
> > commit 047fe6e6db9161e69271f56daaafdaf2add023b1
> > Author: David Weinehall
> > Date: Tue Aug 4 16:55:52 2015 +0300
> >
> > drm/i915: Allow parsing o
On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
> This reverts
>
> commit 047fe6e6db9161e69271f56daaafdaf2add023b1
> Author: David Weinehall
> Date: Tue Aug 4 16:55:52 2015 +0300
>
> drm/i915: Allow parsing of variable size child device entries from VBT
>
> That commit is not valid for
On 8/18/2015 10:56 PM, Mika Kuoppala wrote:
commit e1f123257a1f7d3af36a31a0fb2d4c6f40039fed
Author: Michel Thierry
Date: Wed Jul 29 17:23:56 2015 +0100
drm/i915: Expand error state's address width to 64b
changed the batch buffer address to be 64b. Fix the parsing
of gtt offset according
On Tue, Aug 18, 2015 at 03:55:07PM +0100, Nick Hoath wrote:
> >This is the wrong location. Just kill set_seqno, the experiment has run
> >its course and we now have a n igt to exercise seqno wraparound.
> It has to be here as the seqno has to be initialised before it is
> used to create requests fo
commit e1f123257a1f7d3af36a31a0fb2d4c6f40039fed
Author: Michel Thierry
Date: Wed Jul 29 17:23:56 2015 +0100
drm/i915: Expand error state's address width to 64b
changed the batch buffer address to be 64b. Fix the parsing
of gtt offset accordingly.
Bugzilla: https://bugs.freedesktop.org/sho
On 18/08/2015 15:31, Chris Wilson wrote:
On Tue, Aug 18, 2015 at 03:23:32PM +0100, Nick Hoath wrote:
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- M
Hi,
On pe, 2015-08-14 at 10:58 +0200, Daniel Vetter wrote:
> On Thu, Aug 13, 2015 at 03:49:35PM -0700, Ben Widawsky wrote:
> > On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas Lahtinen wrote:
> > > Hi,
> > >
> > > On ke, 2015-08-12 at 18:35 -0700, Ben Widawsky wrote:
> > > > On Wed, Aug 12, 2015
On Tue, Aug 18, 2015 at 03:23:32PM +0100, Nick Hoath wrote:
> Extend init/init_hw split to context init.
>- Move context initialisation in to i915_gem_init_hw
>- Move one off initialisation for render ring to
> i915_gem_validate_context
>- Move default context initialisation to
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr
On Tue, Aug 18, 2015 at 02:28:55PM +0300, Jani Nikula wrote:
> commit 75067ddecf21271631bc018d2fb23ddd09b66aae
> Author: Antti Koskipaa
> Date: Fri Jul 10 14:10:55 2015 +0300
>
> drm/i915: Per-DDI I_boost override
>
> increased size of union child_device_config without taking into account
On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
> > > On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
> > > > Only internal eDP, LVDS, DVI screen could set scalling mode, some
> > > > customers need to set
On 8/18/2015 12:42 PM, Jani Nikula wrote:
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/18/2015 12:14 PM, Jani Nikula wrote:
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2
Hey,
Op 17-08-15 om 17:05 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> With MST there won't be a crtc assigned to the main link encoder, so
> trying to dig up the pipe_config from there is a recipe for an oops.
>
> Instead store the parameters (lane_count and link_rate) in the
From EDID we can read and request higher pixel clock than
our HW can support. This set of patches add checks if
requested pixel clock is lower than the one supported by the HW.
The requested mode is discarded if we cannot support the requested
pixel clock. For example for Cherryview
'cvt 2560 1600
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.
This patch applies to DVO.
V2:
-
Store max dotclock into dev_priv structure so we are able
to filter out the modes that are not supported by our
platforms.
V2:
- limit the max dot clock frequency to max CD clock frequency
for the gen9 and above
- limit the max dot clock frequency to 90% of the max CD clock
frequency for the o
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.
This patch applies to LVDS.
V2:
-
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.
This patch applies to DSI.
V2:
-
commit 75067ddecf21271631bc018d2fb23ddd09b66aae
Author: Antti Koskipaa
Date: Fri Jul 10 14:10:55 2015 +0300
drm/i915: Per-DDI I_boost override
increased size of union child_device_config without taking into account
the size check in parse_sdvo_device_mapping(). Switch the function over
to
On Tue, Aug 18, 2015 at 12:33:36PM +0300, Jani Nikula wrote:
> This reverts
>
> commit 047fe6e6db9161e69271f56daaafdaf2add023b1
> Author: David Weinehall
> Date: Tue Aug 4 16:55:52 2015 +0300
>
> drm/i915: Allow parsing of variable size child device entries from VBT
>
> That commit is not
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
v2: rename the function to indicate it checks source rates (Jani)
v3: update comment to indicate TP3 dependancy on HBR2 supported
hardware (Jani)
Reviewed-by: Ville Syrjä
This reverts
commit 047fe6e6db9161e69271f56daaafdaf2add023b1
Author: David Weinehall
Date: Tue Aug 4 16:55:52 2015 +0300
drm/i915: Allow parsing of variable size child device entries from VBT
That commit is not valid for v4.2, however it will be valid for v4.3. It
was simply queued too ea
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
> On 8/18/2015 12:14 PM, Jani Nikula wrote:
>> On Tue, 18 Aug 2015, Sivakumar Thulasimani
>> wrote:
>>> From: "Thulasimani,Sivakumar"
>>>
>>> This patch removes TP3 support on CHV since there is no support
>>> for HBR2 on this platform.
>>>
>>>
From: Libin Yang
For display audio, call the sync_audio_rate callback function
to do the synchronization between gfx driver and audio driver.
Signed-off-by: Libin Yang
Reviewed-by: Takashi Iwai
---
sound/pci/hda/patch_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --g
From: Libin Yang
When modeset occurs and the TMDS frequency is set to some
speical values, the N/CTS need to be set manually if audio
is playing.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/i915_reg.h| 8
drivers/gpu/drm/i915/intel_audio.c | 40
From: Libin Yang
HDMI audio may not work at some frequencies
with the HW provided N/CTS.
This patch sets the proper N value for the
given audio sample rate at the impacted frequencies.
At other frequencies, it will use the N/CTS value
which HW provides.
Signed-off-by: Libin Yang
---
drivers/g
From: Libin Yang
Add the sync_audio_rate callback.
With the callback, audio driver can trigger
i915 driver to set the proper N/CTS or N/M
based on different sample rates.
Signed-off-by: Libin Yang
---
include/drm/i915_component.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm
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