>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 2:48 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 01/11] drm/i915: Adding
>the parsing logic for the i2
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 5:41 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 03/11] drm/i915: Parsing
>VBT if size of VBT exceeds
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 5:48 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using
>the approprite vbt size if vb
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 8:09 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 05/11] drm/i915: Added
>support the v3 mipi sequence
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 7:01 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using
>the approprite vbt size if vb
Starting with commit
commit 28cc504e8d52248962f5b485bdc65f539e3fe21d
Author: Rob Clark
Date: Tue Aug 25 15:36:00 2015 -0400
drm/i915: enable atomic fb-helper
I've been seeing some panics on i915 when the DRM master shuts down that appear
to be caused by usi
This commit is essentially a rewrite of "drm/i915: Check pixel format
for fbc" from Ville Syrjälä. The idea is the same, but the code is
different due to all the changes that happened since his original
patch. So any bugs are due to my bad rewrite.
v2:
- Drop the alpha formats (Ville).
v3:
- D
Hello,
This change looks good but incomplete.
When changing RC6 from EI mode to TO mode,
should the time value in GEN6_RC6_THRESHOLD
be changed to hold the timeout value instead
of the evaluation interval period?
Should the workaround name be included in a comment?
While this workaround is unname
On 17 September 2015 at 00:45, Daniel Vetter wrote:
> On Mon, Sep 14, 2015 at 8:22 AM, Daniel Vetter wrote:
>> Hi Dave,
>>
>> -rc1 is out the door and here's my first pull request for drm-next. It's
>> all over:
>> - better atomic helpers for runtime pm drivers
>> - atomic fbdev
>
> David Herrman
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/int
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Cc: Alex Dai
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertio
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
It will be usefull to specify w/a that affects only SKL GT3 and GT4.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/driver
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD
exit.
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d
On Fri, Sep 11, 2015 at 05:44:32AM -0700, Kamble, Sagar A wrote:
> Due to flip interrupts routed to GuC, GuC stays awake always and GT does not
> enter RC6.
> GuC firmware should re-direct to GuC those interrupts that it can handle.
>
> v2: Commit message change and routing all interrupts to host
This one can be discarded and I will amend a fix to my other patch series.
Thanks,
Alex
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gatin
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Enable TO mode for RC6 for SKL till D0 and BXT till A0.
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 13 ++---
1 file changed, 10 ins
On Mon, Sep 07, 2015 at 02:45:59PM -0400, Dave Jones wrote:
> On Fri, Sep 04, 2015 at 11:40:53PM +0100, Dave Airlie wrote:
> >
> > Hi Linus,
> >
> > This is the main pull request for the drm for 4.3. Nouveau is probably
> the biggest
> > amount of changes in here, since it missed 4.2
In case of Y-Tiling, "plane_blocks_per_line" calculation is different
than X/None-Tiling case.
This patch corrects this calculation according to Bspec.
plane blocks per line = Plane memory format is Y tile ?
ceiling[4 * plane bytes per line / 512]/4 :
ceiling
If ddb allocation for planes in current CRTC is changed, that doesn't
lead to ddb allocation change for other CRTCs, because our DDB allocation
is not dynamic according to plane parameters, ddb is allocated according
to number of CRTC enabled, & divided equally among CTRC's.
In current condition c
Reviewed-by: Sivakumar Thulasimani
On 9/18/2015 2:11 PM, Sonika Jindal wrote:
Adding voltage swing table for edp to support low vswings.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff
Reviewed-by: Sivakumar Thulasimani
On 9/18/2015 2:11 PM, Sonika Jindal wrote:
Bspec update tells that we have to enable oscaledcompmethod instead of
ouniqetrangenmethod for enabling scale value during swing programming.
Also, scale value is 'don't care' for other levels except the last entry
tr
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and till SKL E0.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_p
On Mon, Sep 21, 2015 at 09:26:11AM -0700, Jesse Barnes wrote:
> On 09/18/2015 12:26 PM, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
> > Yeah I guess that was a crappy example. Trying to think of a better one,
> > I figure execlist status could be read from
Looks fine to me.
Reviewed by: Alex Dai .
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD
exit.
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel
Looks fine to me.
Reviewed by: Alex Dai .
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
On BXT, We Observe timeout for forcewake request completion with 2ms polling
period as given here:
[drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
Polling for 50ms is recom
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
Signed-off-by: Alex Da
On 09/21/2015 09:53 AM, Ville Syrjälä wrote:
> On Mon, Sep 21, 2015 at 09:26:11AM -0700, Jesse Barnes wrote:
>> On 09/18/2015 12:26 PM, Ville Syrjälä wrote:
>>> On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
>>> Yeah I guess that was a crappy example. Trying to think of a better one,
On Wed, Sep 16, 2015 at 11:07:01PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> This patch adds new structures in DRM layer for Palette color
> correction.These structures will be used by user space agents
> to configure appropriate number of samples and Palette LUT for
> a platform.
On 09/18/2015 12:26 PM, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
> Yeah I guess that was a crappy example. Trying to think of a better one,
> I figure execlist status could be read from memory, but apparently
> that's just mmio. I guess the context update
> > > > + if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED
> > &&
> > > > + ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) %
> > 4)) {
> > > > + DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line
> > aligned\n",
> > > > +
From: Tvrtko Ursulin
Prevent leaking VMAs and PPGTT VMs when objects are imported
via flink.
Scenario is that any VMAs created by the importer will be left
dangling after the importer exits, or destroys the PPGTT context
with which they are associated.
This is caused by object destruction not r
From: Ville Syrjälä
v2: Hide the 945 vs. rest of gen2/3 difference in the macro
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_fence.c | 41 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 21 +++---
drivers/gpu/drm/i915/i915_reg.h
On Mon, Sep 14, 2015 at 03:20:03PM -0300, Paulo Zanoni wrote:
> I only tested this on BDW and SKL, but since the register description
> is the same ever since gen4, let's assume that all gens take the same
> register format. If that's not true, then hopefully someone will
> bisect a bug to this pat
On Mon, Sep 14, 2015 at 03:20:02PM -0300, Paulo Zanoni wrote:
> This commit is essentially a rewrite of "drm/i915: Check pixel format
> for fbc" from Ville Syrjälä. The idea is the same, but the code is
> different due to all the changes that happened since his original
> patch. So any bugs are due
On Mon, 21 Sep 2015, Andrzej Hajda wrote:
> The function can return negative value.
>
> The problem has been detected using proposed semantic patch
> scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
>
> [1]: http://permalink.gmane.org/gmane.linux.kernel/2038576
>
> Signed-off-by: Andr
On Mon, Sep 14, 2015 at 03:19:59PM -0300, Paulo Zanoni wrote:
> BSpec says we shouldn't enable FBC on HSW/BDW when the pipe pixel rate
> exceeds 95% of the core display clock.
>
> v2:
> - HSW also needs the WA (Ville).
> - Add the WA name (Ville).
> - Use the current cdclk (Ville).
>
> Sign
On Mon, Sep 14, 2015 at 03:19:57PM -0300, Paulo Zanoni wrote:
> The FBC hardware for these platforms doesn't have access to the
> bios_reserved range, so it always assumes the maximum (8mb) is used.
> So avoid this range while allocating.
>
> This solves a bunch of FIFO underruns that happen if yo
On Tue, Jul 21, 2015 at 10:42:53AM -0700, Bob Paauwe wrote:
> Clearing the watermarks for all pipes/planes when updating the
> watermarks for a single CRTC change seems like the wrong thing to
> do here. As is, this code will ony update any pipe/plane watermarks
> that need updating and leave the r
On Mon, Sep 14, 2015 at 03:19:56PM -0300, Paulo Zanoni wrote:
> Don't allow FBC for cases where the spec says we can't FBC.
>
> v2:
> - Just WARN_ON() the strides that should have been caught earlier
> (Daniel)
> - Make it a new function since I expect this to grow more.
> v3:
> - Docume
The function can return negative value.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/intel_lrc.c | 7 +++
Hi,
This is set of independent patches. The only connection between
them is that they try to address problems spotted by proposed
coccinelle semantic patch unsigned_lesser_than_zero.cocci[1].
Semantic patch finds comparisons of types:
unsigned < 0
unsigned >= 0
The former is always false,
On 09/21/2015 02:02 PM, Nick Hoath wrote:
Remove extraneous request cancel in request allocation failure path
in intel_lr_context_deferred_alloc (Tvrtko Ursulin)
Signed-off-by: Nick Hoath
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 1 -
1 file changed, 1 deletion(-)
diff --
On Mon, Sep 21, 2015 at 03:33:00PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 21, 2015 at 10:45:46AM +0300, Jani Nikula wrote:
> > On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/i915
This is fix for a regression introduced by 27321ae88c70104df
"drm/i915: Use the disable callback for disabling planes."
Disabling invisible planes may cause recalculation of
watermarks, which is a problem because the software state
is not yet in sync with the hardware state.
This may result in a b
Remove extraneous request cancel in request allocation failure path
in intel_lr_context_deferred_alloc (Tvrtko Ursulin)
Signed-off-by: Nick Hoath
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/driver
On Mon, Sep 21, 2015 at 02:48:03PM +0200, Sedat Dilek wrote:
> On Mon, Sep 21, 2015 at 11:42 AM, Chris Wilson
> wrote:
> > On Sun, Sep 20, 2015 at 08:20:21PM +0200, Sedat Dilek wrote:
> >> Hi,
> >>
> >> I am here on Ubuntu/precise AMD64 with libdrm v2.4.65 and mesa v10.6.8.
> >>
> >> I cannot see
On Mon, Sep 21, 2015 at 11:42 AM, Chris Wilson wrote:
> On Sun, Sep 20, 2015 at 08:20:21PM +0200, Sedat Dilek wrote:
>> Hi,
>>
>> I am here on Ubuntu/precise AMD64 with libdrm v2.4.65 and mesa v10.6.8.
>>
>> I cannot see my LightDM login-manager, my system hangs in VT-1.
>>
>> When I revert...
>>
On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote:
> From: Akash Goel
>
> Signed-off-by: Ankitprasad Sharma
> Signed-off-by: Akash Goel
> Signed-off-by: Sagar Arun Kamble
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --gi
On Mon, Sep 21, 2015 at 10:45:46AM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_gem_fence.c | 42
> > +--
> > drivers/gpu/d
Hey,
Op 14-09-15 om 16:23 schreef Ville Syrjälä:
> On Mon, Sep 14, 2015 at 01:57:45PM +0200, Maarten Lankhorst wrote:
>> Op 10-09-15 om 17:59 schreef ville.syrj...@linux.intel.com:
>>> From: Ville Syrjälä
>>>
>>> intel_modeset_readout_hw_state() seems like the more appropriate place
>>> for popul
On pe, 2015-09-18 at 17:52 +0100, Arun Siluvery wrote:
> Cc: Nick Hoath
> Cc: Imre Deak
> Signed-off-by: Arun Siluvery
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/dr
On Mon, Sep 21, 2015 at 10:45:31AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> GTT page remapping logic for 90/270 rotation needs some
> extensions to support NV12 90/270 rotation work which is
> currently underway.
>
> Main thing is really to support building of the rotated
> page m
Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD
exit.
v3: Explicitly clear the Turbo control register (Akash)
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 20
On ma, 2015-09-21 at 10:45 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> v2: Rebase.
>
> Signed-off-by: Tvrtko Ursulin
>
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
> drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
> drivers/gpu/drm/i915/intel_
On ma, 2015-09-21 at 10:45 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Just adding the rotated UV plane at the end of the rotated Y plane.
>
> v2: Rebase.
>
>
> Signed-off-by: Tvrtko Ursulin
>
One comment below, otherwise.
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm
On Mon, Sep 21, 2015 at 12:43:36PM +0200, Patrik Jakobsson wrote:
> On Thu, Sep 17, 2015 at 02:14:37PM +0300, Ville Syrjälä wrote:
> > On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> > > On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> > > > We need to be able to
Hi,
On ma, 2015-09-21 at 10:45 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> By providing a start offset into the source array of pages, and
> returning the
> end position in the scatter-gather table, we will be able to append
> the UV
> plane to the rotated mapping in later patches.
>
On ma, 2015-09-21 at 10:45 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This will be needed for NV12 support.
>
> v2: Rebase.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +-
> drivers/gpu/drm/i915/intel
On Thu, Sep 17, 2015 at 02:14:37PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> > > We need to be able to control if DC6 is allowed or not. Much like
> > > requesting power to a s
>-Original Message-
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:48 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in
>CRTC modeset
>
>-Original Message-
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:21 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Kamath, Sunil; Kannan, Vandana; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC
>accordin
Hi,
On 09/11/2015 12:53 PM, Nick Hoath wrote:
> Extend init/init_hw split to context init.
> - Move context initialisation in to i915_gem_init_hw
> - Move one off initialisation for render ring to
> i915_gem_validate_context
> - Move default context initialisation to logical_
>-Original Message-
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:08 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight
>support
>
>On Tue, 01 Sep 2015, Uma
>-Original Message-
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 7:03 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM
>frequency
>
>On Tue, 01 Sep 2015,
>-Original Message-
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 6:58 PM
>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy
>clocks
>
>On T
On Mon, 21 Sep 2015, Mika Kuoppala wrote:
> Jani Nikula writes:
>
>> SKL port E handling was added in
>>
>> commit 26951caf55d73ceb1967b0bf12f6d0b96853508e
>> Author: Xiong Zhang
>> Date: Mon Aug 17 15:55:50 2015 +0800
>>
>> drm/i915/skl: enable DDI-E hotplug
>>
>> but the whole function w
From: Tvrtko Ursulin
Just adding the rotated UV plane at the end of the rotated Y plane.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 37 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +++
drivers/gpu/drm/i915/intel_disp
From: Tvrtko Ursulin
By providing a start offset into the source array of pages, and returning the
end position in the scatter-gather table, we will be able to append the UV
plane to the rotated mapping in later patches.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_
From: Tvrtko Ursulin
This will be needed for NV12 support.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 10 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
3 files changed, 7 insertions(+), 7 deleti
From: Tvrtko Ursulin
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 26 +-
drivers/gpu/drm/i915/intel_drv.h | 4 +++-
drivers/gpu/drm/i9
From: Tvrtko Ursulin
GTT page remapping logic for 90/270 rotation needs some
extensions to support NV12 90/270 rotation work which is
currently underway.
Main thing is really to support building of the rotated
page mapping from two planes instead of one, and adding
appropriate calculations for t
On Sun, Sep 20, 2015 at 08:20:21PM +0200, Sedat Dilek wrote:
> Hi,
>
> I am here on Ubuntu/precise AMD64 with libdrm v2.4.65 and mesa v10.6.8.
>
> I cannot see my LightDM login-manager, my system hangs in VT-1.
>
> When I revert...
>
> commit 650da13c7257019728cfca361dfcbe34a6c526ef
> "sna: Col
On 9/18/2015 6:47 PM, Jani Nikula wrote:
On Tue, 01 Sep 2015, Uma Shankar wrote:
From: Shashank Sharma
This patch contains following changes:
1. MIPI device ready changes to support dsi_pre_enable. Changes
are specific to BXT device ready sequence. Added check for
ULPS mode(No effec
Jani Nikula writes:
> SKL port E handling was added in
>
> commit 26951caf55d73ceb1967b0bf12f6d0b96853508e
> Author: Xiong Zhang
> Date: Mon Aug 17 15:55:50 2015 +0800
>
> drm/i915/skl: enable DDI-E hotplug
>
> but the whole function was moved in a another branch in
>
> commit b93433ccf648
On Mon, Sep 21, 2015 at 11:26:06AM +0300, Jani Nikula wrote:
> On Mon, 21 Sep 2015, Patrik Jakobsson
> wrote:
> > On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> >> On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> >> > We need to be able to control if DC6 is al
Jani Nikula writes:
> On Fri, 18 Sep 2015, Mika Kuoppala wrote:
>> If csr/dmc firmware is known to be outdated, notify
>> user.
>
> What would break if we requested a firmware version that works? Or we've
> made it so that we only request the major version because there's not
> supposed to be ch
On Mon, 21 Sep 2015, Patrik Jakobsson wrote:
> On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
>> On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
>> > We need to be able to control if DC6 is allowed or not. Much like
>> > requesting power to a specific piece of the
On Wed, Sep 16, 2015 at 11:10:07PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 11, 2015 at 01:55:22PM +0200, Patrik Jakobsson wrote:
> > We need to be able to control if DC6 is allowed or not. Much like
> > requesting power to a specific piece of the hardware we need to be able
> > to request that we
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> FIXME: Should there be a WARN(i != 9) or something, or what does the
> entry 9 comment mean?
Either the code, the comment, or both are bust. Needs to be checked.
However, this patch does not change that part for
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12
> drivers/gpu/drm/i915/intel_tv.c | 8
> 2 files changed, 8 insertions(+), 12 deletio
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/d
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +-
> drivers/gpu/drm/i915/intel_pm.c | 14 +++---
> 2 files changed, 12 insertions(+), 12 de
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_gem_fence.c | 42
> +--
> drivers/gpu/drm/i915/i915_gpu_error.c | 21 --
> drivers/gpu/drm/i915/i915
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 8
> drivers/gpu/drm/i915/intel_lrc.c| 8 +++-
> drivers/gpu/drm/i915/intel_lrc.h| 6 ++
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> d
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> intel_sdvo_select_ddc_bus() and intel_sdvo_select_i2c_bus() have no used
> for the passed in 'reg', so just drop it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/inte
On Fri, 18 Sep 2015, Mika Kuoppala wrote:
> If csr/dmc firmware is known to be outdated, notify
> user.
What would break if we requested a firmware version that works? Or we've
made it so that we only request the major version because there's not
supposed to be changes like this between minor ver
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