Re: [Intel-gfx] v4.3-rc4: i915: ThinkPad Yoga 12: *ERROR* The master control interrupt lied (SDE)! [regression]

Created bug in fdo bugzilla to keep track of this regression: https://bugs.freedesktop.org/show_bug.cgi?id=92454 Regards -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Monday, October 12, 2015 2:06 AM To: Darren Hart Cc: Linux

[Intel-gfx] [PATCH] MAINTAINERS: add link to the Intel Graphics for Linux web site

There's plenty of drm/i915 related hardware and software documentation, and firmware downloads for the latest platforms. Cc: Daniel Vetter Signed-off-by: Jani Nikula --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS

Re: [Intel-gfx] [PATCH 09/20] i915: switch from acpi_os_ioremap to memremap

On Mon, Oct 12, 2015 at 09:12:57PM +, Williams, Dan J wrote: > On Mon, 2015-10-12 at 09:01 +0200, Daniel Vetter wrote: > > On Fri, Oct 09, 2015 at 06:16:25PM -0400, Dan Williams wrote: > > > i915 expects the OpRegion to be cached (i.e. not __iomem), so explicitly > > > map it with memremap

Re: [Intel-gfx] 4.2-rc4 kernel warnings on HSW laptop [regression]

On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote: > On Mon, 12 Oct 2015 09:04:20 +0200, > Daniel Vetter wrote: > > > > Another pile of regressions for Jairo to track ... > > > > On Sat, Oct 10, 2015 at 11:46:29AM +0200, Takashi Iwai wrote: > > > Hi, > > > > > > I noticed that a HSW

Re: [Intel-gfx] [PATCH] drm/i915: Hold dev->event_lock whilst inspecting intel_crtc->unpin_work

On Sat, Oct 10, 2015 at 10:44:32AM +0100, Chris Wilson wrote: > We should serialise access to the intel_crtc->unpin_work through the > dev->event_lock spinlock. It should not be possible for it to disappear > without severe error as the mmio_flip worker has not tagged the > unpin_work pending

Re: [Intel-gfx] [PATCH v2] drm/i915: Improve kernel-doc for i915_audio_component struct

On Mon, 12 Oct 2015 10:17:51 +0200, David Henningsson wrote: > > > > On 2015-10-12 10:07, David Henningsson wrote: > > To make kernel-doc happy, the i915_audio_component_audio_ops struct > > cannot be nested. > > > > Signed-off-by: David Henningsson > > --- >

[Intel-gfx] [PATCH] drm/i915: Log correct start and length in pte map trace

The PTE_map trace added in commit 4c06ec8d13d2 ("drm/i915/gen8: Add dynamic page trace events") was using the full start and length values, instead of the page directory ones. Since this is just a trace, I don't think it requires cc'ing stable. Cc: Akash Goel

Re: [Intel-gfx] [PATCH 19/22] drm/i915: BDW: Pipe level Gamma correction

Regards Shashank On 10/12/2015 11:39 PM, Rob Bradford wrote: On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote: BDW/SKL/BXT platforms support various Gamma correction modes which are: 1. Legacy 8-bit mode 2. 10-bit Split Gamma mode 3. 12-bit mode This patch does the following: 1. Adds

Re: [Intel-gfx] [PATCH 20/22] drm/i915: BDW: Load degamma correction values

Regards Shashank On 10/12/2015 11:43 PM, Rob Bradford wrote: On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote: I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property. This patch adds the no of coefficients(65) for degamma correction as

Re: [Intel-gfx] [PATCH] drm/i915: Hold dev->event_lock whilst inspecting intel_crtc->unpin_work

On Tue, Oct 13, 2015 at 12:23:38PM +0300, Ville Syrjälä wrote: > On Sat, Oct 10, 2015 at 10:44:32AM +0100, Chris Wilson wrote: > > We should serialise access to the intel_crtc->unpin_work through the > > dev->event_lock spinlock. It should not be possible for it to disappear > > without severe

Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe timing for BXT DSI

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Monday, October 12, 2015 10:54 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit >Subject: Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe >timing for BXT

Re: [Intel-gfx] [PATCH 21/22] drm/i915: BDW: Pipe level degamma correction

Thanks for the review Rob. Regards Shashank On 10/12/2015 11:38 PM, Rob Bradford wrote: On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote: BDW/SKL/BXT supports Degamma color correction feature, which linearizes the non-linearity due to gamma encoded color values. This will be applied

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote: > Op 23-09-15 om 17:34 schreef Gabriel Feceoru: > > Using 2 connectors (DVI and VGA) will cause wrpll to be set for > > INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VGA > > > > Supresses errors like these: > >

Re: [Intel-gfx] [PATCH 21/22] drm/i915: BDW: Pipe level degamma correction

On 10 October 2015 at 06:31, Sharma, Shashank wrote: > On 10/10/2015 5:19 AM, Emil Velikov wrote: >> >> Hi Shashank, >> >> On 9 October 2015 at 20:29, Shashank Sharma >> wrote: >>> >>> BDW/SKL/BXT supports Degamma color correction feature,

Re: [Intel-gfx] [PATCH 16/22] drm/i915: Commit color correction to CRTC

Regards Shashank On 10/13/2015 6:47 PM, Emil Velikov wrote: On 10 October 2015 at 06:20, Sharma, Shashank wrote: On 10/10/2015 4:54 AM, Emil Velikov wrote: Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: The color

Re: [Intel-gfx] [PATCH 22/22] drm/i915: BDW: Pipe level CSC correction

On 10 October 2015 at 06:34, Sharma, Shashank wrote: > On 10/10/2015 5:24 AM, Emil Velikov wrote: >> >> Hi Shashank, >> >> On 9 October 2015 at 20:29, Shashank Sharma >> wrote: >>> >>> BDW/SKL/BXT support Color Space Conversion (CSC) using a

Re: [Intel-gfx] [PATCH] drm/i915: Fix kerneldoc for i915_gem_shrink_all

On Tue, 06 Oct 2015, Daniel Vetter wrote: > I've botched this, so let's fix it. > > Signed-off-by: Daniel Vetter Pushed to drm-intel-fixes, thanks for the patch. BR, Jani. > --- > drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 +- > 1 file

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

On Tue, Oct 13, 2015 at 03:43:28PM +0200, Maarten Lankhorst wrote: > Op 13-10-15 om 15:35 schreef Daniel Vetter: > > On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote: > >> Op 23-09-15 om 17:34 schreef Gabriel Feceoru: > >>> Using 2 connectors (DVI and VGA) will cause wrpll to be

Re: [Intel-gfx] [PATCH 10/22] drm/i915: Register color correction capabilities

> Do you have a link handy ? I suspect that something else was mentioned in > that comment as splitting function declaration and definition is extremely > uncommon Yep, maybe I misunderstood. I will add the definition here. Regards Shashank -Original Message- From: Emil Velikov

Re: [Intel-gfx] [PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

On 13 October 2015 at 14:40, Sharma, Shashank wrote: > I am not sure if I915 follows a general rule of using for(...) over while(), > coz I see many instances of using a while in i915_gem, i915_drv, i915_irq > etc, so it should be good. I would see if someone else can

[Intel-gfx] 4.3-rc5 triggering warning in i915 driver

Hi, I got this warning, which 4.2 didn't show on boot: [6.882835] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in has_drrs (expected 1, found 0) [6.882836] [ cut here ] [6.882854] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:12691

Re: [Intel-gfx] [PATCH] RFC drm/i915: Stop the machine whilst capturing the GPU crash dump

On Tue, Oct 13, 2015 at 02:52:46PM +0100, Chris Wilson wrote: > On Tue, Oct 13, 2015 at 03:52:08PM +0200, Daniel Vetter wrote: > > Yeah, hence using _rcu list macros. They have the relevant barriers > > already and should work. The only difference is that instead of > > synchronize_rcu on the

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4

On Tue, 13 Oct 2015, Daniel Vetter wrote: > On Tue, Oct 13, 2015 at 04:10:19PM +0300, Jani Nikula wrote: >> On Thu, 08 Oct 2015, Ville Syrjälä wrote: >> > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: >> >> On Wed, Oct 07, 2015 at

Re: [Intel-gfx] [PATCH] drm/i915: Deny wrapping an userptr into a framebuffer

On 13/10/15 15:00, Tvrtko Ursulin wrote: On 13/10/15 14:22, Chris Wilson wrote: Pinning a userptr onto the hardware raises interesting questions about the lifetime of such a surface as the framebuffer extends that life beyond the client's address space. That is the hardware will need to keep

Re: [Intel-gfx] [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it

On Tue, Oct 13, 2015 at 04:16:47PM +0300, Jani Nikula wrote: > On Wed, 07 Oct 2015, Jani Nikula wrote: > > On Tue, 06 Oct 2015, Ville Syrjälä wrote: > >> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote: > >>> On Tue, 06 Oct 2015,

[Intel-gfx] [PATCH] drm/i915: track relative-constants-mode per-context not per-device

'relative_constants_mode' has always been tracked per-device, but this is wrong in execlists (or GuC) mode, as INSTPM is saved and restored with the logical context, and the per-context value could therefore get out of sync with the tracked value. This patch moves the tracking element from the

Re: [Intel-gfx] [PATCH 19/22] drm/i915: BDW: Pipe level Gamma correction

On 10 October 2015 at 06:21, Sharma, Shashank wrote: > On 10/10/2015 5:09 AM, Emil Velikov wrote: >> >> Hi Shashank, >> >> On 9 October 2015 at 20:29, Shashank Sharma [snip] >>> + switch (num_samples) { >>> + case

Re: [Intel-gfx] [PATCH 15/22] drm/i915: CHV: Pipe level CSC correction

On 10 October 2015 at 06:26, Sharma, Shashank wrote: > On 10/10/2015 5:13 AM, Emil Velikov wrote: >> >> On 9 October 2015 at 20:29, Shashank Sharma >> wrote: >>> >>> CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix >>> that

Re: [Intel-gfx] [PATCH 10/22] drm/i915: Register color correction capabilities

Regards Shashank On 10/13/2015 6:33 PM, Emil Velikov wrote: On 10 October 2015 at 06:01, Sharma, Shashank wrote: On 10/10/2015 3:51 AM, Emil Velikov wrote: Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: From DRM

Re: [Intel-gfx] [PATCH] drm/i915: Convert WARNs during userptr revoke to SIGBUS

On Tue, Oct 13, 2015 at 02:09:48PM +0100, Chris Wilson wrote: > On Tue, Oct 13, 2015 at 02:23:57PM +0200, Daniel Vetter wrote: > > On Tue, Oct 13, 2015 at 12:44:05PM +0100, Chris Wilson wrote: > > > On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote: > > > > On Mon, Oct 12, 2015 at

Re: [Intel-gfx] [PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

Regards Shashank On 10/13/2015 6:38 PM, Emil Velikov wrote: On 10 October 2015 at 06:09, Sharma, Shashank wrote: On 10/10/2015 4:37 AM, Emil Velikov wrote: Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: CHV/BSW

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

On Tue, Oct 13, 2015 at 03:35:01PM +0200, Daniel Vetter wrote: > On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote: > > Op 23-09-15 om 17:34 schreef Gabriel Feceoru: > > > Using 2 connectors (DVI and VGA) will cause wrpll to be set for > > > INTEL_OUTPUT_HDMI but never reset if

Re: [Intel-gfx] [PATCH 09/22] drm/i915: Create color management files

Thanks for the review Emil. Please find my comments inline Regards Shashank On 10/13/2015 6:29 PM, Emil Velikov wrote: On 10 October 2015 at 05:55, Sharma, Shashank wrote: On 10/10/2015 4:17 AM, Emil Velikov wrote: Hi Shashank, On 9 October 2015 at 20:28,

Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote: > On Wed, 26 Aug 2015, Chris Wilson wrote: > > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote: > >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote: > >> > In order to flush the

Re: [Intel-gfx] [PATCH 19/22] drm/i915: BDW: Pipe level Gamma correction

Regards Shashank On 10/13/2015 6:53 PM, Emil Velikov wrote: On 10 October 2015 at 06:21, Sharma, Shashank wrote: On 10/10/2015 5:09 AM, Emil Velikov wrote: Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma [snip] +

Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

On Tue, 13 Oct 2015, Daniel Vetter wrote: > On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote: >> On Wed, 26 Aug 2015, Chris Wilson wrote: >> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote: >> >> On Fri, Aug 21, 2015 at

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4

On Tue, Oct 13, 2015 at 04:10:19PM +0300, Jani Nikula wrote: > On Thu, 08 Oct 2015, Ville Syrjälä wrote: > > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: > >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrj...@linux.intel.com > >> wrote: > >>

Re: [Intel-gfx] [PATCH 22/22] drm/i915: BDW: Pipe level CSC correction

Regards Shashank On 10/13/2015 7:15 PM, Emil Velikov wrote: On 10 October 2015 at 06:34, Sharma, Shashank wrote: On 10/10/2015 5:24 AM, Emil Velikov wrote: Hi Shashank, On 9 October 2015 at 20:29, Shashank Sharma wrote: BDW/SKL/BXT

[Intel-gfx] Video freezing after activating XScreensaver

This is an issue that has been ongoing for over 1 1/2 years now. I have tried kernel after kernel and whether it's a Ubuntu kernel such as the one in my sig or a kernel from here - http://kernel.ubuntu.com/~kernel-ppa/mainline/drm-intel-next/ the video will intermittently freeze. Running

Re: [Intel-gfx] [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it

On Wed, 07 Oct 2015, Jani Nikula wrote: > On Tue, 06 Oct 2015, Ville Syrjälä wrote: >> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote: >>> On Tue, 06 Oct 2015, Ville Syrjälä wrote: >>> > On Tue,

Re: [Intel-gfx] [PATCH 16/22] drm/i915: Commit color correction to CRTC

On 10 October 2015 at 06:20, Sharma, Shashank wrote: > On 10/10/2015 4:54 AM, Emil Velikov wrote: >> >> Hi Shashank, >> >> On 9 October 2015 at 20:29, Shashank Sharma >> wrote: >>> >>> The color correction blob values are loaded during

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

Op 23-09-15 om 17:34 schreef Gabriel Feceoru: > Using 2 connectors (DVI and VGA) will cause wrpll to be set for > INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VGA > > Supresses errors like these: > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.wrpll >

[Intel-gfx] [PATCH] drm/i915: Deny wrapping an userptr into a framebuffer

Pinning a userptr onto the hardware raises interesting questions about the lifetime of such a surface as the framebuffer extends that life beyond the client's address space. That is the hardware will need to keep scanning out from the backing storage even after the client wants to remap its

Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe timing for BXT DSI

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, October 13, 2015 4:54 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit >Subject: Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe >timing for BXT

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

Op 13-10-15 om 15:35 schreef Daniel Vetter: > On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote: >> Op 23-09-15 om 17:34 schreef Gabriel Feceoru: >>> Using 2 connectors (DVI and VGA) will cause wrpll to be set for >>> INTEL_OUTPUT_HDMI but never reset if switching to

Re: [Intel-gfx] [PATCH] RFC drm/i915: Stop the machine whilst capturing the GPU crash dump

On Tue, Oct 13, 2015 at 01:24:53PM +0100, Chris Wilson wrote: > On Tue, Oct 13, 2015 at 02:09:59PM +0200, Daniel Vetter wrote: > > On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote: > > > On Fri, Oct 09, 2015 at 07:33:23PM +0200, Daniel Vetter wrote: > > > > On Fri, Oct 09, 2015 at

Re: [Intel-gfx] [PATCH 15/22] drm/i915: CHV: Pipe level CSC correction

Regards Shashank On 10/13/2015 7:03 PM, Emil Velikov wrote: On 10 October 2015 at 06:26, Sharma, Shashank wrote: On 10/10/2015 5:13 AM, Emil Velikov wrote: On 9 October 2015 at 20:29, Shashank Sharma wrote: CHV/BSW supports Color

Re: [Intel-gfx] [PATCH v2] drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level

On Fri, Oct 09, 2015 at 02:43:21PM +0100, Tvrtko Ursulin wrote: > > On 09/10/15 14:11, Chris Wilson wrote: > >Since the remove of the pin-ioctl, we only care about not changing the > >cache level on buffers pinned to the hardware as indicated by > >obj->pin_display. By knowing that only objects

Re: [Intel-gfx] [PATCH 10/22] drm/i915: Register color correction capabilities

On 13 October 2015 at 14:36, Sharma, Shashank wrote: > On 10/13/2015 6:33 PM, Emil Velikov wrote: >> >> On 10 October 2015 at 06:01, Sharma, Shashank >> wrote: >>> >>> On 10/10/2015 3:51 AM, Emil Velikov wrote: Hi Shashank,

Re: [Intel-gfx] [PATCH] RFC drm/i915: Stop the machine whilst capturing the GPU crash dump

On Tue, Oct 13, 2015 at 03:52:08PM +0200, Daniel Vetter wrote: > On Tue, Oct 13, 2015 at 01:24:53PM +0100, Chris Wilson wrote: > > On Tue, Oct 13, 2015 at 02:09:59PM +0200, Daniel Vetter wrote: > > > On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote: > > > > On Fri, Oct 09, 2015 at

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

Op 13-10-15 om 15:58 schreef Daniel Vetter: > On Tue, Oct 13, 2015 at 03:43:28PM +0200, Maarten Lankhorst wrote: >> Op 13-10-15 om 15:35 schreef Daniel Vetter: >>> On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote: Op 23-09-15 om 17:34 schreef Gabriel Feceoru: > Using 2

Re: [Intel-gfx] [PATCH] drm/i915: Deny wrapping an userptr into a framebuffer

On 13/10/15 14:22, Chris Wilson wrote: Pinning a userptr onto the hardware raises interesting questions about the lifetime of such a surface as the framebuffer extends that life beyond the client's address space. That is the hardware will need to keep scanning out from the backing storage even

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Grab execlist spinlock to avoid post-reset concurrency issues.

On Tue, Oct 13, 2015 at 03:46:00PM +0200, Daniel Vetter wrote: > On Tue, Oct 13, 2015 at 12:45:58PM +0100, Chris Wilson wrote: > > On Tue, Oct 13, 2015 at 01:46:38PM +0200, Daniel Vetter wrote: > > > On Fri, Oct 09, 2015 at 09:45:16AM +0100, Chris Wilson wrote: > > > > On Fri, Oct 09, 2015 at

Re: [Intel-gfx] v4.3-rc4: i915: ThinkPad Yoga 12: *ERROR* The master control interrupt lied (SDE)! [regression]

Le 12. 10. 15 09:06, Daniel Vetter a écrit : Another regression for Jairo to track. -Daniel I get the exact same dmesg too with the 4.3.0-rc5 on a i5-5250U NUC using HDMI. The rest is a standard Debian Jessie. On Sat, Oct 10, 2015 at 12:08:43PM -0700, Darren Hart wrote: The Debian 3.16.0

Re: [Intel-gfx] [PATCH] drm/i915: Deny wrapping an userptr into a framebuffer

On Tue, 13 Oct 2015, Tvrtko Ursulin wrote: > On 13/10/15 14:22, Chris Wilson wrote: >> Pinning a userptr onto the hardware raises interesting questions about >> the lifetime of such a surface as the framebuffer extends that life >> beyond the client's address

Re: [Intel-gfx] [PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

Regards Shashank On 10/13/2015 7:29 PM, Emil Velikov wrote: On 13 October 2015 at 14:40, Sharma, Shashank wrote: I am not sure if I915 follows a general rule of using for(...) over while(), coz I see many instances of using a while in i915_gem, i915_drv, i915_irq

Re: [Intel-gfx] [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

On Tue, Oct 13, 2015 at 04:00:37PM +0200, Maarten Lankhorst wrote: > Op 13-10-15 om 15:58 schreef Daniel Vetter: > > On Tue, Oct 13, 2015 at 03:43:28PM +0200, Maarten Lankhorst wrote: > >> Op 13-10-15 om 15:35 schreef Daniel Vetter: > >>> On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst

Re: [Intel-gfx] [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE

On Mon, Oct 12, 2015 at 09:12:09AM -0700, Jesse Barnes wrote: > On 09/18/2015 10:03 AM, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Signed-off-by: Ville Syrjälä > > --- > >

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Cope with request list state change during error state capture

On Fri, Oct 09, 2015 at 12:45:07PM +0100, Tomas Elf wrote: > On 09/10/2015 09:28, Daniel Vetter wrote: > >On Thu, Oct 08, 2015 at 07:31:35PM +0100, Tomas Elf wrote: > >>Since we're not synchronizing the ring request list during error state > >>capture > >>the request list state might change

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Unify execlist and legacy request life-cycles

On Tue, Oct 13, 2015 at 01:29:56PM +0200, Daniel Vetter wrote: > On Fri, Oct 09, 2015 at 06:23:50PM +0100, Chris Wilson wrote: > > On Fri, Oct 09, 2015 at 07:18:21PM +0200, Daniel Vetter wrote: > > > On Fri, Oct 09, 2015 at 10:45:35AM +0100, Chris Wilson wrote: > > > > On Fri, Oct 09, 2015 at

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Grab execlist spinlock to avoid post-reset concurrency issues.

On Fri, Oct 09, 2015 at 09:45:16AM +0100, Chris Wilson wrote: > On Fri, Oct 09, 2015 at 10:38:18AM +0200, Daniel Vetter wrote: > > On Thu, Oct 08, 2015 at 07:31:39PM +0100, Tomas Elf wrote: > > > Grab execlist lock when cleaning up execlist queues after GPU reset to > > > avoid > > > concurrency

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Migrate to safe iterators in error state capture

On Tue, Oct 13, 2015 at 01:37:32PM +0200, Daniel Vetter wrote: > On Fri, Oct 09, 2015 at 12:40:51PM +0100, Tomas Elf wrote: > > On 09/10/2015 09:27, Daniel Vetter wrote: > > >On Thu, Oct 08, 2015 at 07:31:34PM +0100, Tomas Elf wrote: > > >>Using safe list iterators alleviates the problem of

Re: [Intel-gfx] [PATCH] RFC drm/i915: Stop the machine whilst capturing the GPU crash dump

On Tue, Oct 13, 2015 at 02:09:59PM +0200, Daniel Vetter wrote: > On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote: > > On Fri, Oct 09, 2015 at 07:33:23PM +0200, Daniel Vetter wrote: > > > On Fri, Oct 09, 2015 at 01:21:45PM +0100, Chris Wilson wrote: > > > > The error state is

[Intel-gfx] [PATCH v5 03/22] drm: Add color correction blobs in CRTC state

This patch adds new variables in CRTC state, to hold respective color correction blobs. These blobs will be required during the atomic commit for writing the color correction values in correction registers. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi

[Intel-gfx] [PATCH v5 02/22] drm: Create Color Management query properties

DRM color management is written to extract the color correction capabilities of various platforms, and every platform can showcase its capabilities using the query properties. Different hardwares can have different no of coefficients for palette correction. Also the correction can be applied

[Intel-gfx] [PATCH v5 04/22] drm: Add set property support for color manager

As per DRM color manager design, if a userspace wants to set a correction blob, it prepares it and sends the blob_id to kernel via set_property call. DRM framework takes this blob_id, gets the blob, and saves it in the CRTC state, so that, during the atomic_commit, the color correction values from

[Intel-gfx] [PATCH v5 09/22] drm/i915: Create color management files

This patch create new files intel_color_manager.c which will contain the core color correction code for I915 driver and its header intel_color_manager.h The per color property patches coming up in this patch series will fill the appropriate functions in this file. Signed-off-by: Shashank Sharma

[Intel-gfx] [PATCH v5 11/22] drm/i915: CHV: Load gamma color correction values

DRM color manager allows the driver to showcase its best color correction capabilities using the specific query property cm_coeff_after_ctm_property. The driver must loads the no. of coefficients for color correction as per the platform capability during the init time. This patch adds no of

[Intel-gfx] [PATCH v5 08/22] drm/i915: Add set property interface for CRTC

This patch adds set property interface for intel CRTC. This interface will be used for set operation on any DRM properties. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file

[Intel-gfx] [PATCH v5 10/22] drm/i915: Register color correction capabilities

From DRM color management: DRM color manager supports these color properties: 1. "ctm": Color transformation matrix property, where a color transformation matrix of 9 correction values gets applied as correction. 2. "palette_before_ctm": for corrections which get

Re: [Intel-gfx] [PATCH] drm/i915: Postpone plane readout until after encoder readout, v3.

On Thu, 27 Aug 2015, Maarten Lankhorst wrote: > When reading out hw state for planes we disable inactive planes which in > turn triggers an update of the watermarks. The update depends on the > crtc_clock being set which is done when reading out encoders. Thus

Re: [Intel-gfx] [PATCH 10/22] drm/i915: Register color correction capabilities

On 10 October 2015 at 06:01, Sharma, Shashank wrote: > On 10/10/2015 3:51 AM, Emil Velikov wrote: >> >> Hi Shashank, >> >> On 9 October 2015 at 20:29, Shashank Sharma >> wrote: >>> >>> From DRM color management: >>>

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Cope with request list state change during error state capture

On Fri, Oct 09, 2015 at 12:25:26PM +0100, Tomas Elf wrote: > On 09/10/2015 08:48, Chris Wilson wrote: > >On Thu, Oct 08, 2015 at 07:31:35PM +0100, Tomas Elf wrote: > >>Since we're not synchronizing the ring request list during error state > >>capture > >>the request list state might change

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Grab execlist spinlock to avoid post-reset concurrency issues.

On Tue, Oct 13, 2015 at 01:46:38PM +0200, Daniel Vetter wrote: > On Fri, Oct 09, 2015 at 09:45:16AM +0100, Chris Wilson wrote: > > On Fri, Oct 09, 2015 at 10:38:18AM +0200, Daniel Vetter wrote: > > > On Thu, Oct 08, 2015 at 07:31:39PM +0100, Tomas Elf wrote: > > > > Grab execlist lock when

Re: [Intel-gfx] [PATCH] drm/i915: Convert WARNs during userptr revoke to SIGBUS

On Tue, Oct 13, 2015 at 12:44:05PM +0100, Chris Wilson wrote: > On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote: > > On Mon, Oct 12, 2015 at 10:31:35AM +0100, Chris Wilson wrote: > > > On Mon, Oct 12, 2015 at 10:06:23AM +0100, Tvrtko Ursulin wrote: > > > > > > > > On 09/10/15 18:26,

Re: [Intel-gfx] 4.2-rc4 kernel warnings on HSW laptop [regression]

On Tue, 13 Oct 2015, Ville Syrjälä wrote: > On Tue, Oct 13, 2015 at 10:24:58AM +0200, Daniel Vetter wrote: >> On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote: >> > On Mon, 12 Oct 2015 09:04:20 +0200, >> > Daniel Vetter wrote: >> > > >> > > Another pile

Re: [Intel-gfx] [PATCH] drm/i915: Clear PIPE.STAT before IIR on VLV/CHV

On Tue, 01 Sep 2015, Imre Deak wrote: > On pe, 2015-08-14 at 18:24 +0100, Chris Wilson wrote: >> The PIPE.STAT register contains some interrupt status bits per pipe, and >> if assert cause the corresponding bit in the IIR to be asserted (thus >> raising an interrupt). When

Re: [Intel-gfx] [PATCH] drm/i915/guc: Add GuC css header parser

On 28/09/15 22:30, yu@intel.com wrote: From: Alex Dai The size / offset information of all firmware ingredients are now caculated from header. Driver will validate the header and rsa key size. If any component is out of boundary, driver will reject the loading too. v4:

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Migrate to safe iterators in error state capture

On Fri, Oct 09, 2015 at 12:40:51PM +0100, Tomas Elf wrote: > On 09/10/2015 09:27, Daniel Vetter wrote: > >On Thu, Oct 08, 2015 at 07:31:34PM +0100, Tomas Elf wrote: > >>Using safe list iterators alleviates the problem of unsynchronized driver > >>list > >>manipulations while error state capture

Re: [Intel-gfx] [PATCH 5/8] drm/i915: vma NULL pointer check

On Fri, Oct 09, 2015 at 12:59:44PM +0100, Chris Wilson wrote: > On Fri, Oct 09, 2015 at 12:30:29PM +0100, Tomas Elf wrote: > > On 09/10/2015 08:48, Chris Wilson wrote: > > >On Thu, Oct 08, 2015 at 07:31:37PM +0100, Tomas Elf wrote: > > >>Sometimes the iterated vma objects are NULL apparently. Be

Re: [Intel-gfx] [PATCH] drm/i915: Convert WARNs during userptr revoke to SIGBUS

On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote: > On Mon, Oct 12, 2015 at 10:31:35AM +0100, Chris Wilson wrote: > > On Mon, Oct 12, 2015 at 10:06:23AM +0100, Tvrtko Ursulin wrote: > > > > > > On 09/10/15 18:26, Chris Wilson wrote: > > > >On Fri, Oct 09, 2015 at 07:14:02PM +0200,

Re: [Intel-gfx] [PATCH 0/7] Enable SVM for Intel VT-d

On Sat, Oct 10, 2015 at 02:17:55PM +0100, David Woodhouse wrote: > On Fri, 2015-10-09 at 00:50 +0100, David Woodhouse wrote: > > This patch set enables PASID support for the Intel IOMMU, along with > > page request support. > > > > Like its AMD counterpart, it exposes an IOMMU-specific API. I

Re: [Intel-gfx] [DMC_REDESIGN_V2 01/14] drm/i915/gen9: csr_init after runtime pm enable

On ke, 2015-08-26 at 16:58 +0530, Animesh Manna wrote: > Skl is fully dependent on dmc for going to low power state (dc5/dc6). > This requires a trigger from rpm. To ensure the dmc firmware > is available for runtime pm support rpm-reference-count is used > by not releasing the rpm reference if

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix primary_get_hw_state for gen9+.

On Wed, 23 Sep 2015, Maarten Lankhorst wrote: > On skylake and broxton the old registers are no longer in use. > Instead it uses universal planes, fix primary_get_hw to use the > correct registers. > > Signed-off-by: Maarten Lankhorst

Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

On Wed, 26 Aug 2015, Chris Wilson wrote: > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote: >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote: >> > In order to flush the results from in-batch pipecontrol writes (used for >> > example in

Re: [Intel-gfx] [PATCH] drm/i915: Postpone plane readout until after encoder readout, v3.

Op 13-10-15 om 14:40 schreef Jani Nikula: > On Thu, 27 Aug 2015, Maarten Lankhorst > wrote: >> When reading out hw state for planes we disable inactive planes which in >> turn triggers an update of the watermarks. The update depends on the >> crtc_clock being

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4

On Thu, 08 Oct 2015, Ville Syrjälä wrote: > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrj...@linux.intel.com >> wrote: >> > From: Ville Syrjälä >> > >> > We

Re: [Intel-gfx] [PATCH 13/22] drm/i915: CHV: Pipe level Gamma correction

On 10 October 2015 at 06:09, Sharma, Shashank wrote: > On 10/10/2015 4:37 AM, Emil Velikov wrote: >> >> Hi Shashank, >> >> On 9 October 2015 at 20:29, Shashank Sharma >> wrote: >>> >>> CHV/BSW platform supports two different pipe level gamma

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Unify execlist and legacy request life-cycles

On Fri, Oct 09, 2015 at 06:23:50PM +0100, Chris Wilson wrote: > On Fri, Oct 09, 2015 at 07:18:21PM +0200, Daniel Vetter wrote: > > On Fri, Oct 09, 2015 at 10:45:35AM +0100, Chris Wilson wrote: > > > On Fri, Oct 09, 2015 at 11:15:08AM +0200, Daniel Vetter wrote: > > > > My idea was to create a new

Re: [Intel-gfx] [PATCH] RFC drm/i915: Stop the machine whilst capturing the GPU crash dump

On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote: > On Fri, Oct 09, 2015 at 07:33:23PM +0200, Daniel Vetter wrote: > > On Fri, Oct 09, 2015 at 01:21:45PM +0100, Chris Wilson wrote: > > > The error state is purposefully racy as we expect it to be called at any > > > time and so have

Re: [Intel-gfx] [PATCH] vlv eDP BIOS Compatiblity to EMGD generated BIOS

On Tue, 23 Jun 2015, Andreas Lampersperger wrote: > When the i915.ko identify an eDP output on a valleyview > board, it should be more slackly. The reason for that is, > that BIOS DATA TABLES generated with intel BMP (Binary > Modification Program) do not set

[Intel-gfx] [PATCH v5 20/22] drm/i915: BDW: Load degamma correction values

I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property. This patch adds the no of coefficients(512) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms. Signed-off-by: Shashank Sharma

[Intel-gfx] [PATCH v5 22/22] drm/i915: BDW: Pipe level CSC correction

BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into respective CSC registers. This patch does the following: 1. Adds the core function to program CSC correction values for BDW/SKL/BXT platform 2. Adds CSC correction macros/defines

Re: [Intel-gfx] [PATCH] drm/i915: Do not update pipe state when crtc is inactive.

On Tue, 22 Sep 2015, Maarten Lankhorst wrote: > Nothing good can come from detaching scalers or updating pipe config > when the crtc is already disabled. Touching registers while the crtc > and power wells are disabled causes unclaimed register access warnings.

[Intel-gfx] [PATCH v5 19/22] drm/i915: BDW: Pipe level Gamma correction

BDW/SKL/BXT platforms support various Gamma correction modes which are: 1. Legacy 8-bit mode 2. 10-bit mode 3. Split mode 4. 12-bit mode This patch does the following: 1. Adds the core function to program Gamma correction values for BDW/SKL/BXT platforms 2. Adds Gamma correction macros/defines

[Intel-gfx] [PATCH v5 16/22] drm/i915: Commit color correction to CRTC

The color correction blob values are loaded during set_property calls. This patch adds a function to find the blob and apply the correction values to the display registers, during the atomic commit call. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi

[Intel-gfx] [PATCH v5 15/22] drm/i915: CHV: Pipe level CSC correction

CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers. This patch does the following: 1. Attaches CSC property to CRTC 2. Adds the core function to program CSC correction values 3. Adds CSC correction macros

[Intel-gfx] [PATCH v5 14/22] drm/i915: CHV: Pipe level degamma correction

CHV/BSW supports Degamma color correction, which linearizes all the non-linear color values. This will be applied before Color Transformation. This patch does the following: 1. Attach deGamma property to CRTC 2. Add the core function to program DeGamma correction values for CHV/BSW platform 2.

[Intel-gfx] [PATCH v5 18/22] drm/i915: BDW: Load gamma correction values

I915 color manager registers pipe gamma correction as palette correction after CTM property. For BDW and higher platforms, split gamma correction is the best gamma correction. This patch adds the no of coefficients(512) for split gamma correction as "num_samples_after_ctm" parameter in device

[Intel-gfx] [PATCH v5 17/22] drm/i915: Attach color properties to CRTC

Function intel_attach_color_properties_to_crtc attaches a color property to its CRTC object. This patch calls this function from crtc initialization sequence. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi ---

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