Re: [Intel-gfx] [PATCH 7/8] drm/i915: Move max voltage and pre emphasis to intel_dp_link_training.c

On 10/19/2015 11:29 AM, Ander Conselvan De Oliveira wrote: On Mon, 2015-10-19 at 10:44 +0530, Thulasimani, Sivakumar wrote: As an FYI, both of these functions need to be rewritten when we want the code to be compliant to DP spec. We should read the pre-emphasis given by the panel and if vwing

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Move max voltage and pre emphasis to intel_dp_link_training.c

On Mon, 2015-10-19 at 10:44 +0530, Thulasimani, Sivakumar wrote: > As an FYI, both of these functions need to be rewritten when we want the > code to be > compliant to DP spec. > We should read the pre-emphasis given by the panel and if vwing exeeds > max value > we should use the max vswing supp

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Move max voltage and pre emphasis to intel_dp_link_training.c

As an FYI, both of these functions need to be rewritten when we want the code to be compliant to DP spec. We should read the pre-emphasis given by the panel and if vwing exeeds max value we should use the max vswing supported for that pre-emphasis but current code is opposite of that. you can

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Don't pass *DP around to link training functions

On 10/5/2015 12:31 PM, Ander Conselvan de Oliveira wrote: It just makes the code more confusing, so just reference intel_dp_>DP directly. The old behavior of not updating the value in intel_dp if link training fail is preserved by saving the previous value of DP in the stack and restoring the o

Re: [Intel-gfx] [PATCH v5 1/2] drm/i915: Fix failure paths around initial fbdev allocation

Hi Ville, On Thu, Oct 15, 2015 at 08:34:23PM +0300, Ville Syrjälä wrote: > On Thu, Oct 15, 2015 at 07:14:35PM +0200, Lukas Wunner wrote: > > Hi Ville, > > > > On Tue, Oct 13, 2015 at 06:04:40PM +0300, Ville Syrjälä wrote: > > > On Tue, Jun 30, 2015 at 10:06:27AM +0100, Lukas Wunner wrote: > > > >

Re: [Intel-gfx] [PATCH] drm: Explicitly compute the last cacheline for clflush on range

On Sun, Oct 18, 2015 at 02:07:13PM +0100, Chris Wilson wrote: > > I couldn't spot the difference either. I am beginning to suspect it is > > gcc as > > > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c > > index 6743ff7..c9097b5 100644 > > --- a/drivers/gpu/drm/drm_cache.c

Re: [Intel-gfx] [PATCH] drm: Explicitly compute the last cacheline for clflush on range

On Sun, Oct 18, 2015 at 01:28:11PM +0100, Chris Wilson wrote: > On Sat, Oct 17, 2015 at 11:03:19PM +0300, Imre Deak wrote: > > On Fri, 2015-10-16 at 20:55 +0100, Chris Wilson wrote: > > > Fixes regression from > > > > > > commit afcd950cafea6e27b739fe7772cbbeed37d05b8b > > > Author: Chris Wilson

Re: [Intel-gfx] [PATCH] drm: Explicitly compute the last cacheline for clflush on range

On Sat, Oct 17, 2015 at 11:03:19PM +0300, Imre Deak wrote: > On Fri, 2015-10-16 at 20:55 +0100, Chris Wilson wrote: > > Fixes regression from > > > > commit afcd950cafea6e27b739fe7772cbbeed37d05b8b > > Author: Chris Wilson > > Date: Wed Jun 10 15:58:01 2015 +0100 > > > > drm: Avoid the dou