[Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views (v4)

While pinning a fb object to the display plane, only install a fence if the object is using a normal view. This corresponds with the behavior found in i915_gem_object_do_pin() where the fencability criteria is determined only for objects with normal views. v2: Look at the object's map_and_fenceabl

[Intel-gfx] [PATCH] igt/kms_rotation_crc: Add a subtest to validate Y-tiled obj + Y fb modifier (v5)

The main goal of this subtest is to trigger the following warning in the function i915_gem_object_get_fence(): if (WARN_ON(!obj->map_and_fenceable)) To trigger this warning, the subtest first creates a Y-tiled object and an associated framebuffer with the Y-fb modifier. Furthermore, to pre

[Intel-gfx] [PATCH v6 0/2] Add drm_dp_aux chardev support.

This series implement support to a drm_dp_aux chardev that allows reading and writing an arbitrary amount of bytes to arbitrary dpcd register addresses using regular read, write and lseek operations. v2: - lseek is used to select the register to read/write - read/write are used instead of ioctl

[Intel-gfx] [PATCH v6 1/2] drm/dp: Add a drm_aux-dev module for reading/writing dpcd registers.

This module is heavily based on i2c-dev. Once loaded, it provides one dev node per DP AUX channel, named drm_dp_auxN, where N is an integer. It's possible to know which connector owns this aux channel by looking at the respective sysfs /sys/class/drm_aux_dev/drm_dp_auxN/connector, if the connector

[Intel-gfx] [PATCH v6 2/2] drm/dp: Set aux.dev to the drm_connector device, instead of drm_device.

So far, the i915 driver and some other drivers set it to the drm_device, which doesn't allow one to know which DP a given aux channel is related to. Changing this to be the drm_connector provides proper nesting, still allowing one to get the drm_device from it. Some drivers already set it to the dr

Re: [Intel-gfx] 4.0.8->4.1.3 : after resume from s2ram both internal and external display of a docked ThinkPad ate black

On Sun 2015-10-04 18:30:14, Toralf Förster wrote: > On 08/04/2015 02:29 PM, Toralf Förster wrote: > > On 08/02/2015 09:43 AM, Pavel Machek wrote: > >> Any chance to bisect it? > > Did it. > > > > FWIW: the mentioned commit was introduced between 3.18 and 3.19. > > But my system (hardened 64 bit Ge

Re: [Intel-gfx] [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled

On Thu, Oct 29, 2015 at 12:36:34PM -0700, Jesse Barnes wrote: > On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for > > all the relevant underrun bits, so in order to keep the error inte

Re: [Intel-gfx] [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK

On Thu, Oct 29, 2015 at 12:39:53PM -0700, Jesse Barnes wrote: > On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > We get underruns on the other pipe when enabling the CPU eDP PLL and > > port on ILK. > > > > Bspec knows about the PLL issue, and recommen

Re: [Intel-gfx] [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB

On Thu, Oct 29, 2015 at 05:57:57PM -0200, Paulo Zanoni wrote: > 2015-10-29 17:25 GMT-02:00 : > > From: Ville Syrjälä > > > > We get spurious PCH FIFO underruns if we enable the reporting too soon > > after enabling the crtc. Move it to be the last step, after the encoder > > enable. Additionally

Re: [Intel-gfx] [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake.

Hi Rodrigo, [auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-drm-i915-Avoid-GuC-loading-for-now-on-Kabylake/20151030-012505 conf

Re: [Intel-gfx] [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB

2015-10-29 17:25 GMT-02:00 : > From: Ville Syrjälä > > We get spurious PCH FIFO underruns if we enable the reporting too soon > after enabling the crtc. Move it to be the last step, after the encoder > enable. Additionally we need an extra vblank wait, otherwise we still > get the underruns. Pres

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes

On 10/29/2015 12:26 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We don't care about ILK-A and the old w/a notes may just confuse > people, so get rid of them. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_dp.c | 4 > 1 file changed, 4 deletions

Re: [Intel-gfx] [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We get underruns on the other pipe when enabling the CPU eDP PLL and > port on ILK. > > Bspec knows about the PLL issue, and recommends doing a vblank wait just > prior to enabling the PLL. That does seem to h

Re: [Intel-gfx] [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Doing the IBX transcoder B workaround causes underruns on > pipe/transcoder A. Just hide them by disabling underrun reporting for > pipe A around the workaround. > > It might be possible to avoid the underruns

Re: [Intel-gfx] [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > ironlake_enaable_pch_transcoder() checks for CPT to see if it should > enable the timing override chicken bit, but > ironlake_disable_pch_transcoder() checks for !IBX to see if it should > clear the same bit. C

Re: [Intel-gfx] [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for > all the relevant underrun bits, so in order to keep the error interrupt > enabled, we need to have underrun reporting enabled on all PCH >

Re: [Intel-gfx] [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > No point in doing the crtc->pipe->crtc->config->cpu_transcoder dance > when we can just do crtc->config->cpu_transcoder. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_display.c | 7 ++--

Re: [Intel-gfx] [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen > after the encoder enable on HSW+. And again, for symmetry, move the > the disable to happen before encoder disable. > > I've left out th

Re: [Intel-gfx] [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We get spurious PCH FIFO underruns if we enable the reporting too soon > after enabling the crtc. Move it to be the last step, after the encoder > enable. Additionally we need an extra vblank wait, otherwise we

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL

On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rather than looking at crtc->mode (which is the user mode) dig up the > sync polarity settings from the adjusted_mode when programming > TRANS_DP_CTL on CPT/PPT. > > Signed-off-by: Ville Syrjälä > --- > driv

[Intel-gfx] [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK

From: Ville Syrjälä We get underruns on the other pipe when enabling the CPU eDP PLL and port on ILK. Bspec knows about the PLL issue, and recommends doing a vblank wait just prior to enabling the PLL. That does seem to help, but unfortunately we get another underrun when actually enabling the C

[Intel-gfx] [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes

From: Ville Syrjälä We don't care about ILK-A and the old w/a notes may just confuse people, so get rid of them. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_

[Intel-gfx] [PATCH 10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/

From: Ville Syrjälä The DP link frequency is 162MHz, not 160MHz. Rename the ILK eDP PLL defines to match. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_dp.c | 10 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/dr

[Intel-gfx] [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+

From: Ville Syrjälä As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen after the encoder enable on HSW+. And again, for symmetry, move the the disable to happen before encoder disable. I've left out the vblank wait before the enable here because I don't know if it's needed or

[Intel-gfx] [PATCH 14/14] drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()

From: Ville Syrjälä ironlake_set_pll_cpu_edp() only gets called just before ironlake_edp_pll_on(), so just pull the code into ironlake_edp_pll_on(). Also toss in a debug print into ironlake_edp_pll_off() to match the one we have in ironlake_edp_pll_on(). Signed-off-by: Ville Syrjälä --- drive

[Intel-gfx] [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()

From: Ville Syrjälä ironlake_enaable_pch_transcoder() checks for CPT to see if it should enable the timing override chicken bit, but ironlake_disable_pch_transcoder() checks for !IBX to see if it should clear the same bit. Change ironlake_disable_pch_transcoder() to check for CPT as well to keep

[Intel-gfx] [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts

From: Ville Syrjälä Rewrite the eDP PLL state asserts to conform to our usual state assert style. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 54 + 1 file changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 13/14] drm/i915: Use intel_dp->DP in eDP PLL setup

From: Ville Syrjälä Use intel_dp->DP in the eDP PLL setup, instead of doing RMWs. To do this we need to move DP_AUDIO_OUTPUT_ENABLE setup to happen later, so that we don't enable audio accidentally while configuring the PLL. Also intel_dp_link_down() must be made to update intel_dp->DP so that

[Intel-gfx] [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround

From: Ville Syrjälä Doing the IBX transcoder B workaround causes underruns on pipe/transcoder A. Just hide them by disabling underrun reporting for pipe A around the workaround. It might be possible to avoid the underruns by moving the workaround to be applied only when enabling pipe A. But I wa

[Intel-gfx] [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled

From: Ville Syrjälä Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for all the relevant underrun bits, so in order to keep the error interrupt enabled, we need to have underrun reporting enabled on all PCH transocders. Currently we leave the underrun reporting disabled when the

[Intel-gfx] [PATCH 06/14] drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT

From: Ville Syrjälä Due to the shared error interrupt on IVB/HSW and CPT/PPT we may not always get an interrupt on a FIFO underrun. But we can always do an explicit check (like we do on GMCH platforms that have no underrun interrupt). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL

From: Ville Syrjälä Rather than looking at crtc->mode (which is the user mode) dig up the sync polarity settings from the adjusted_mode when programming TRANS_DP_CTL on CPT/PPT. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 6 -- 1 file changed, 4 insertions(+), 2

[Intel-gfx] [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB

From: Ville Syrjälä We get spurious PCH FIFO underruns if we enable the reporting too soon after enabling the crtc. Move it to be the last step, after the encoder enable. Additionally we need an extra vblank wait, otherwise we still get the underruns. Presumably the pipe/fdi isn't yet fully up an

[Intel-gfx] [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms

From: Ville Syrjälä This series eliminates all spurious PCH FIFO underrun reports on my machines during a BAT run ('-t basic -x reload -x suspend' actually). It also eliminates the non-spurious but expected underrun reports on ILK. I also embarked on a small scale cleanup of the CPU eDP PLL code

[Intel-gfx] [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around

From: Ville Syrjälä No point in doing the crtc->pipe->crtc->config->cpu_transcoder dance when we can just do crtc->config->cpu_transcoder. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gp

Re: [Intel-gfx] [PATCH 02/26] drm/i915: don't stop+start FBC at every flip

On Thu, Oct 29, 2015 at 05:52:26PM +, Zanoni, Paulo R wrote: > Em Qui, 2015-10-29 às 19:30 +0200, Ville Syrjälä escreveu: > > On Wed, Oct 28, 2015 at 07:20:12PM +0200, Ville Syrjälä wrote: > > > On Wed, Oct 28, 2015 at 04:56:39PM +, Zanoni, Paulo R wrote: > > > > Em Ter, 2015-10-27 às 20:32

Re: [Intel-gfx] [PATCH] drm/i915/kbl: Fix DMC load on Kabylake.

Hi Rodrigo, [auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-Fix-DMC-load-on-Kabylake/20151030-012303 config: x86_64-randconfig-

Re: [Intel-gfx] [PATCH] drm/i915/kbl: Fix DMC load on Kabylake.

Hi Rodrigo, [auto build test WARNING on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-Fix-DMC-load-on-Kabylake/20151030-012303 config: x86_64-randconfi

Re: [Intel-gfx] [PATCH 19/26] drm/i915: move adjusted_mode checks from fbc_update to fbc_enable

Em Qui, 2015-10-29 às 13:59 +0100, Maarten Lankhorst escreveu: > Op 27-10-15 om 17:50 schreef Paulo Zanoni: > > These things can't change without a full modeset. > False! Fastset can update parameters too. Although I don't think it > currently prevents DBLSCAN updates, > so maybe make sure cfb enab

Re: [Intel-gfx] [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake

Hi Deepak, [auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-drm-i915-Avoid-GuC-loading-for-now-on-Kabylake/20151030-012505 confi

Re: [Intel-gfx] [PATCH 02/26] drm/i915: don't stop+start FBC at every flip

Em Qui, 2015-10-29 às 19:30 +0200, Ville Syrjälä escreveu: > On Wed, Oct 28, 2015 at 07:20:12PM +0200, Ville Syrjälä wrote: > > On Wed, Oct 28, 2015 at 04:56:39PM +, Zanoni, Paulo R wrote: > > > Em Ter, 2015-10-27 às 20:32 +0200, Ville Syrjälä escreveu: > > > > On Tue, Oct 27, 2015 at 02:50:04P

Re: [Intel-gfx] [PATCH 02/26] drm/i915: don't stop+start FBC at every flip

On Wed, Oct 28, 2015 at 07:20:12PM +0200, Ville Syrjälä wrote: > On Wed, Oct 28, 2015 at 04:56:39PM +, Zanoni, Paulo R wrote: > > Em Ter, 2015-10-27 às 20:32 +0200, Ville Syrjälä escreveu: > > > On Tue, Oct 27, 2015 at 02:50:04PM -0200, Paulo Zanoni wrote: > > > > The hardware already takes car

[Intel-gfx] [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake.

GuC has no version for KBL published yet and it is not recommended to load the Skylake one, so let's avoid loading this for now while we don't have the proper GuC firmware for Kabylake. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 d

[Intel-gfx] [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake

From: Deepak S Reviewed-by: Damien Lespiau Signed-off-by: Deepak S Signed-off-by: Damien Lespiau Signed-off-by: Rodrigo Vivi --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 9f9cc68..5

[Intel-gfx] [PATCH] drm/i915/kbl: Fix DMC load on Kabylake.

Kabylake A0 is based on Skylake H0. v2: Don't assume revid+7 and only load the one we are sure about. v3: Add missing IS_KABYLAKE. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_csr.c | 38 +++--- 1 file changed, 31 insertions(+), 7 deletions(-) dif

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Add csr programming registers to dmc debugfs entry

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote: > We check these to determine firmware loading status. Include > them to help to debug causes of firmware loading fails. > > v2: Move all CSR specific registers to i915_reg.h (Ville) > v3: Rebase > > Signed-off-by: Mika Kuoppala Reviewed-by

Re: [Intel-gfx] [PATCH 5/7] drm/i915/bxt: Expose DC5 entry count

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote: > For bxt CSR firmware exposes a count of dc5 entries. Expose > it through debugs > > Signed-off-by: Mika Kuoppala Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_debugfs.c | 3 +++ > drivers/gpu/drm/i915/i915_reg.h | 1 + >

Re: [Intel-gfx] [PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote: > From: Damien Lespiau > > The CSR firmware expose two counters, handy to check if we are indeed > entering DC5/DC6. > > v2: Rebase > > Signed-off-by: Damien Lespiau > Reviewed-by: Rodrigo Vivi (v1) > Signed-off-by: Mika Kuoppala > --- >

Re: [Intel-gfx] [PATCH 05/26] drm/i915: extract fbc_on_pipe_a_only()

Em Qui, 2015-10-29 às 13:05 +0100, Maarten Lankhorst escreveu: > Op 27-10-15 om 17:50 schreef Paulo Zanoni: > > Make the code easier to read. > > > > Suggested-by: Chris Wilson > > Signed-off-by: Paulo Zanoni > > --- > >  drivers/gpu/drm/i915/intel_fbc.c | 13 +++-- > >  1 file changed, 7

Re: [Intel-gfx] [PATCH 3/7] drm/i915/skl: Print the DMC firmware status in debugfs

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote: > From: Damien Lespiau > > Create a new debufs file for it, we'll have a few more things to add > there. > > v2: Fix checkpatch warning about static const array > v3: use named initializers (Ville) > v4: strip out csr_state as it will be rem

[Intel-gfx] FW: [PATCH v7 08/25] drm: Add color correction state flag

HI Jani, I am getting this warning, from kbuild, for the new flags being added in the patch series in CRTC state. >> include/drm/drm_crtc.h:314: warning: No description found for parameter >> 'color_correction_changed' Can you please help me out by giving some details about how can I resolve the

Re: [Intel-gfx] [PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote: > There is known issue on GT interrupt delivery with DC6 and > firmwares <1.21. There is a suspicion that this causes > spurious gpu hangs on driver init and with some workloads, > as upgrading the firmware to 1.21 makes these problems > disapp

Re: [Intel-gfx] [PATCH 1/7] drm/i915/skl: Store and print the DMC firmware version we load

On ti, 2015-10-27 at 14:46 +0200, Mika Kuoppala wrote: > From: Damien Lespiau > > That can be handy later on to tell which DMC firmware version the user > has, by just looking at the dmesg. > > v2: use DRM_DEBUG_DRIVER (Chris) > v3: use DRM_INFO (Marc Herbert) > > Cc: Marc Herbert > Signed-off

Re: [Intel-gfx] HDMI 4k modes VIC

Thanks for the suggestion. I will check with Thierrey also. Regards Shashank -Original Message- From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] Sent: Thursday, October 29, 2015 6:48 PM To: Sharma, Shashank Cc: Lespiau, Damien; Jani Nikula; intel-gfx@lists.freedesktop.org; dri

Re: [Intel-gfx] [PATCH v3 01/13] drm/i915/gen9: csr_init after runtime pm enable

On to, 2015-10-29 at 15:48 +0530, Sunil Kamath wrote: > On Thursday 29 October 2015 03:28 AM, Imre Deak wrote: > > From: Animesh Manna > > > > Skl is fully dependent on dmc for going to low power state (dc5/dc6). > > This requires a trigger from rpm. To ensure the dmc firmware > > is available for

[Intel-gfx] [maintainer-tools PATCH] dim: append commit message tags in git, not in files

Email is hard. Let that sink in. The message piped to dim may have, among other things, base64 encoding, and using sed to modify the commit message directly on the input falls apart. This is also true for messages sent using git-send-email. Let 'git am' handle the hard part, and modify the commit

Re: [Intel-gfx] [PATCH] drm/i915: make A0 wa's applied to A1

On Thu, 29 Oct 2015, Arun Siluvery wrote: > On 26/10/2015 10:48, tim.g...@intel.com wrote: >> From: Tim Gore >> >> Since A1 chips use the same GPU as A0, they need all the >> same wa's in the i915 driver. Update some conditionals >> to do this. >> >> Signed-off-by: Tim Gore >> --- >> drivers/g

Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views (v3)

On 29/10/15 13:20, Ville Syrjälä wrote: On Wed, Oct 28, 2015 at 06:24:19PM -0700, Vivek Kasireddy wrote: While pinning a fb object to the display plane, only install a fence if the object is using a normal view. This corresponds with the behavior found in i915_gem_object_do_pin() where the fenc

Re: [Intel-gfx] [PATCH v3 00/13] drm/i915: Redesign dmc firmware loading.

On to, 2015-10-29 at 10:08 +0200, Jani Nikula wrote: > On Wed, 28 Oct 2015, Imre Deak wrote: > > This is a rebased version of [1], addressing the review comments. It > > depends on Mika's FW version blacklisting/capture patchset [2]. > > > > I have added my Reviewed-by to those patches that I only

[Intel-gfx] [PATCH 7/7] drm/i915: Add dmc firmware load state and version to error state

We have had one case where buggy csr/dmc firmware version influenced gt side and caused a hang. Add dmc firmware loading state and version to error state. v2: - Rebased on top of Damien's patches - included fw load state v3: include dmc info only if platform supports it (Chris) v4: move *csr t

Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views (v3)

On Wed, Oct 28, 2015 at 06:24:19PM -0700, Vivek Kasireddy wrote: > While pinning a fb object to the display plane, only install a fence > if the object is using a normal view. This corresponds with the > behavior found in i915_gem_object_do_pin() where the fencability > criteria is determined only

Re: [Intel-gfx] HDMI 4k modes VIC

On Thu, Oct 29, 2015 at 08:03:29AM +, Sharma, Shashank wrote: > Actually we should update the cea_modedb in drm layer with 4k modes and > appropriate VIC, coz the AVI infoframe functions are > not getting proper VICs for cea modes. Or while processing alternative cea > modes, we should check

Re: [Intel-gfx] [PATCH 19/26] drm/i915: move adjusted_mode checks from fbc_update to fbc_enable

Op 27-10-15 om 17:50 schreef Paulo Zanoni: > These things can't change without a full modeset. False! Fastset can update parameters too. Although I don't think it currently prevents DBLSCAN updates, so maybe make sure cfb enable/disable is called when updating pipe too? > Signed-off-by: Paulo Zano

[Intel-gfx] [PATCH igt v7.1 1/4] lib/tests: Add igt_assert_*() self-tests

Make sure our igt_assert variants are doing something that looks vaguely like the right thing. v7.1: Rename to igt_assert, add to .gitignore. Signed-off-by: Daniel Stone --- lib/tests/.gitignore | 1 + lib/tests/Makefile.sources | 1 + lib/tests/igt_assert.c | 173

Re: [Intel-gfx] [PATCH] drm/i915: make A0 wa's applied to A1

On 26/10/2015 10:48, tim.g...@intel.com wrote: From: Tim Gore Since A1 chips use the same GPU as A0, they need all the same wa's in the i915 driver. Update some conditionals to do this. Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/intel_guc_loader.c | 2 +- drivers/gpu/drm/i915/intel_l

Re: [Intel-gfx] [PATCH] drm/dp: add eDP DPCD backlight control bit definitions

On Thu, 2015-10-29 at 11:03 +0200, Jani Nikula wrote: > Cc: Yetunde Adebisi > Signed-off-by: Jani Nikula > --- > include/drm/drm_dp_helper.h | 36 > 1 file changed, 36 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >

Re: [Intel-gfx] [PATCH 05/26] drm/i915: extract fbc_on_pipe_a_only()

Op 27-10-15 om 17:50 schreef Paulo Zanoni: > Make the code easier to read. > > Suggested-by: Chris Wilson > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_fbc.c | 13 +++-- > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c

Re: [Intel-gfx] [PATCH 02/26] drm/i915: don't stop+start FBC at every flip

Op 28-10-15 om 18:20 schreef Ville Syrjälä: > On Wed, Oct 28, 2015 at 04:56:39PM +, Zanoni, Paulo R wrote: >> Em Ter, 2015-10-27 às 20:32 +0200, Ville Syrjälä escreveu: >>> On Tue, Oct 27, 2015 at 02:50:04PM -0200, Paulo Zanoni wrote: The hardware already takes care of disabling and recomp

Re: [Intel-gfx] PROBLEM: i915.preliminary_hw_support crash

On Mon, 26 Oct 2015, John Doe wrote: > i'm getting this crash booting kernel 4.2.1 with > i915.preliminary_hw_support=1. > I'm running an intel skylake i7-6700k cpu on z170 chipset, using xen > (qubes-os). Having to use i915.preliminary_hw_support=1 is a hint that the support isn't quite there ye

Re: [Intel-gfx] [PATCH] lib/igt_kms: Introduce get_first_connected_output to retrieve a valid output

On 29 October 2015 at 02:09, Vivek Kasireddy wrote: > In some cases, we just need one valid output to perform a test. > This macro can help in these situations by avoiding iterating > over all the outputs. > > Suggested-by: Matt Roper > CC: Tvrtko Ursulin > CC: Matt Roper > Signed-off-by: Vivek

[Intel-gfx] [PATCH igt v7 4/4] kms_atomic: Add basic atomic modesetting tests

Add tests for KMS atomic modesetting, to exercise the basic interface and test failure/corner cases. Should ensure coherency between the legacy and atomic interfaces. v2: New patch. v3: Disable connector checking for now, as it was causing GPU hangs on newer kernels. v4: Rebase. v5: Use do_ioc

[Intel-gfx] intel i915 driver crashes: drivers/gpu/drm/i915/intel_display.c:11293 intel_check_page_flip+0xf4/0x100

[1.] intel i915 driver crashes: drivers/gpu/drm/i915/intel_display.c:11293 intel_check_page_flip+0xf4/0x100 [2.] It always happens in several seconds (5-60) after loading a Don't Starve Together game (latest version through Steam, 148470, AFAIK it uses OpenGL) and often after several hours of KDE

[Intel-gfx] PROBLEM: i915.preliminary_hw_support crash

Greetings, i'm getting this crash booting kernel 4.2.1 with i915.preliminary_hw_support=1. I'm running an intel skylake i7-6700k cpu on z170 chipset, using xen (qubes-os). Full boot log is attached. [3.580272] BUG: unable to handle kernel NULL pointer dereference at 0060 [3.580

[Intel-gfx] [PATCH igt v7 1/4] lib/tests: Add igt_assert_*() self-tests

Make sure our igt_assert variants are doing something that looks vaguely like the right thing. Signed-off-by: Daniel Stone --- lib/tests/Makefile.sources | 1 + lib/tests/igt_simple.c | 173 + 2 files changed, 174 insertions(+) create mode 10064

[Intel-gfx] [PATCH igt v7 0/4] Assert tests, atomic, multi-blob

Hi, Following on from the previous few series, most of which have been merged ... Add some self-tests for igt-assert_*() to make sure they do the right thing, including for fds. This is a bit gross, but does work. Do a Cocci run through the tree. This doesn't actually pick up a lot of the changes

[Intel-gfx] [PATCH igt v7 3/4] tests/core_prop_blob: Add multiple blobs per connection

This should hit the bug fixed in: XXX FIXME INSERT SEANPAUL COMMIT CITE which was introduced with the initial blob support in: commit e2f5d2ea479b9b2619965d43db70939589afe43a Author: Daniel Stone Date: Fri May 22 13:34:51 2015 +0100 drm/mode: Add user blob-creation ioctl

[Intel-gfx] [PATCH igt v7 2/4] tests: Run igt.cocci

Signed-off-by: Daniel Stone --- tests/drm_import_export.c| 2 +- tests/gem_bad_reloc.c| 8 ++ tests/gem_concurrent_all.c | 6 ++-- tests/gem_ctx_exec.c | 9 ++ tests/gem_ctx_param_basic.c | 4 +-- tests/gem_mmap_gtt.c | 8 ++

Re: [Intel-gfx] (XEN) Fatal machine check

On 26/10/2015 13:04, John Doe wrote: > Hi, i'm getting this problem with linux 4.3.0-rcX branch. > Full log is attached. My hardware is based on intel skylake i7-6700k on > z170 chipset and it is working properly. It does boot correctly with > older kernels (3.12). > With mce=off on xen parameters

Re: [Intel-gfx] [PATCH] igt/kms_rotation_crc: Add a subtest to validate Y-tiled obj + Y fb modifier (v4)

On 29/10/15 01:48, Vivek Kasireddy wrote: The main goal of this subtest is to trigger the following warning in the function i915_gem_object_get_fence(): if (WARN_ON(!obj->map_and_fenceable)) To trigger this warning, the subtest first creates a Y-tiled object and an associated framebuffe

Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views (v3)

On 29/10/15 01:24, Vivek Kasireddy wrote: While pinning a fb object to the display plane, only install a fence if the object is using a normal view. This corresponds with the behavior found in i915_gem_object_do_pin() where the fencability criteria is determined only for objects with normal views

Re: [Intel-gfx] [PATCH v3 01/13] drm/i915/gen9: csr_init after runtime pm enable

On Thursday 29 October 2015 03:28 AM, Imre Deak wrote: From: Animesh Manna Skl is fully dependent on dmc for going to low power state (dc5/dc6). This requires a trigger from rpm. To ensure the dmc firmware is available for runtime pm support rpm-reference-count is used by not releasing the rpm

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Add Backlight Control using DPCD for eDP connectors

On Wed, 30 Sep 2015, Yetunde Adebisi wrote: > This patch adds support for eDP backlight control using DPCD registers to > backlight hooks in intel_panel. > > It checks for backlight control over AUX channel capability and sets up > function pointers to get and set the backlight brightness level if

Re: [Intel-gfx] [PATCH v3 12/13] drm/i915/gen9: flush DMC fw loading work during system suspend

On 10/29/2015 3:29 AM, Imre Deak wrote: Currently during system s/r we enable/disable DC6, so before we do so make sure that the firmware loading is complete. Note that whether we need to enable DC6 for S3/S4 is still open. At least the firmware program is lost during S3 and we need to reprog

Re: [Intel-gfx] [PATCH v3 04/13] drm/i915/gen9: Remove csr.state, csr_lock and related code.

On 10/29/2015 3:28 AM, Imre Deak wrote: From: Daniel Vetter This removes two anti-patterns: - Locking shouldn't be used to synchronize with async work (of any form, whether callbacks, workers or other threads). This is what the mutex_lock/unlock seems to have been for in intel_csr_load_

[Intel-gfx] [PATCH] drm/dp: add eDP DPCD backlight control bit definitions

Cc: Yetunde Adebisi Signed-off-by: Jani Nikula --- include/drm/drm_dp_helper.h | 36 1 file changed, 36 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index bb9d0deca07c..1252108da0ef 100644 --- a/include/drm/drm_dp_help

Re: [Intel-gfx] [PATCH v3 00/13] drm/i915: Redesign dmc firmware loading.

On Wed, 28 Oct 2015, Imre Deak wrote: > This is a rebased version of [1], addressing the review comments. It > depends on Mika's FW version blacklisting/capture patchset [2]. > > I have added my Reviewed-by to those patches that I only rebased or > updated the commit message, patches 1,4,12 have c

Re: [Intel-gfx] HDMI 4k modes VIC

Actually we should update the cea_modedb in drm layer with 4k modes and appropriate VIC, coz the AVI infoframe functions are not getting proper VICs for cea modes. Or while processing alternative cea modes, we should check and return VICs. I was planning to add 4k@60 modes, I will probably add

Re: [Intel-gfx] intel i915 driver crashes: drivers/gpu/drm/i915/intel_display.c:11293 intel_check_page_flip+0xf4/0x100

On Thu, 29 Oct 2015, Serhiy Int wrote: > Adding debug info, collected with drm.debug=14 Looks like https://bugs.freedesktop.org/show_bug.cgi?id=91717, please attach your dmesg there. Thanks for the report. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _