There was a wonderful period after
commit 6dda730e55f412a6dfb181cae6784822ba463847
Author: Jani Nikula
Date: Tue Jun 24 18:27:40 2014 +0300
drm/i915: respect the VBT minimum backlight brightness
The backlight class 0 brightness means the PWM min and it does not turn
off the backlight. Aft
From: "Boyer, Wayne"
Beginning with SKL the DP Aux channel communication can be protected
using a built in HW mutex.
When PSR is enabled the HW takes control on AUX and uses it to
control panel exit/entry states.
When validating PSR with automated tests, grabbing CRC from sink
revealed strange
On Tue, 2015-11-10 at 16:34 +, Daniel Stone wrote:
> Hi,
>
> On 5 November 2015 at 18:49, Rodrigo Vivi
> wrote:
> > /**
> > + * intel_ips_disable_if_alone - Disable IPS if alone in the pipe.
> > + * @crtc: intel crtc
> > + *
> > + * This function should be called when primary plane is being
Since commit
commit aed242ff7ebb697e4dff912bd4dc7ec7192f7581
Author: Chris Wilson
Date: Wed Mar 18 09:48:21 2015 +
drm/i915: Relax RPS contraints to allows setting minfreq on idle
it is now possible that the current frequency will drop below the user
specified minimum frequenc
On Tue, 10 Nov 2015 11:04:22 +0200
Mika Kuoppala wrote:
> Bob Paauwe writes:
>
> > Signed-off-by: Bob Paauwe
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92768
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff
Many reasons here:
- Hardware tracking also has hidden corner cases
- Frontbuffer tracking is mature and reliable now
- Our sw exit by unseting bit 31 is really fast and reliable.
Also frontbuffer tracking flush means invalidate and flush.
So, let's rely more and do the proper meaning of flush f
This is wrong since my commit (89251b17). The intention of that
commit was to remove this one here that is also wrong anyway,
but it was forgotten.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ps
Proceeding with the big series split here goes the general PSR
improvements and stabilization work.
There is no critical fix on this series although I believe it is
good to have all of them before we can enable PSR back by default.
Rodrigo Vivi (4):
drm/i915: Force PSR exit when IRQ_HPD is dete
According to VESA spec: "If a Source device receives and IRQ_HPD
while in a PSR active state, and cannot identify what caused the
IRQ_HPD to be generated, based on Sink device status registers,
the Source device can take implementation-specific action.
One such action can be to exit and then re-ent
At the beginning it was masked to allow PSR at all.
Than it got removed later by my
commit 09108b90f040 ("drm/i915: PSR: Remove Low Power HW tracking mask.")
in order to trying fixing one case reported at intel-gfx mailing list
where we were missing screen updates when runtime_pm was enabled.
Howe
Let's split critical PSR fixes from the series that contains other
reworks, stabilization and improvements.
The second patch in this series isn't considered critical in terms
of functionality, but it depends on the first one and it can be consider
a fix for PSR residency on VLV/CHV.
Thanks,
Rodri
With 'commit 30886c5a ("drm/i915: VLV/CHV PSR: Increase wait delay
time before active PSR.")' we fixed a blank screen when first
activation was happening immediately after PSR being enabled.
There we gave more time for idleness by increasing the delay
between re-activating sequences.
However, com
When debuging the frozen screen caused by HW tracking with low
power state I noticed that if we keep moving the mouse non stop
you will miss the screen updates for a while. At least
until we stop moving the mouse for a small time and move again.
The actual enabling should happen immediately after
On the commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")'
we already had identified that DP_PSR_NO_TRAIN_ON_EXIT
doesn't mean we shouldn't send TPS patterns, however we start sending the
minimal TP1 as possible and no TP2.
For most of the panels this is ok, but we found a re
Since the beginning there is a confusion on the meaning of this bit.
A previous patch had identified this already and fixed it partially:
'commit 3301d409 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")
DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the
training, but it doesn't
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will
> prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Signed-off-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index e6d88f5..31b3a84 100644
> ---
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> We need a power domain for disabling DC5/DC6 around modesets to
> prevent
> confusing the DMC.
>
> Signed-off-by: Patrik Jakobsson
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
> drivers/gpu/drm/i915/i915_d
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> We never make use of the distinction between 2 vs 4 lanes so combine
> them into a per port domain instead. This saves us a few bits in the
> power domain mask. Change suggested by Ville.
>
> Signed-off-by: Patrik Jakobsson
Reviewed-by:
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Move call to gen9_set_dc_state_debugmask_memory_up() into
> gen9_set_dc_state() to prevent us missing it somewhere.
>
> Signed-off-by: Patrik Jakobsson
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 35 ++
Let's start spliting that big series that enables PSR with this sink crc
stabilization.
Also I'm adding Wayne's mutex that stabilizes sink CRC on Skylake.
All patches already reviewed and ready to merge.
Thank you very much Paulo for the review and Thank you Wayne for the
SKL aux mutex.
Thanks,
It was created at 'commit aabc95dcf20 (drm/i915: Dont -ETIMEDOUT
on identical new and previous (count, crc).")' becase the counter
wasn't reliable.
Now that we properly wait for the counter to be reset we can rely
a bit more in the counter.
Also that patch stopped to return -ETIMEDOUT so the test
According to VESA DP spec TEST_CRC_COUNT (Bits 3:0) at
TEST_SINK_MISC (00246h) is "Reset to 0 when TEST_SINK bit 0 = 0;
So let's give few vblanks so we are really sure that this counter
is really zeroed on the next sink_crc read.
v2: Use DRM_DEBUG_KMS instead of DRM_ERROR as Paulo suggested.
Sig
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Replaces "drm/i915: Force loading of csr program at boot" in the old
> series.
>
> Previously we called blindly into intel_csr_load_program() and
> depended
> on a check of whether the CSR program memory was cleared or not.
> This check i
From: "Boyer, Wayne"
Beginning with SKL the DP Aux channel communication can be protected
using a built in HW mutex.
When PSR is enablabled the HW takes control on AUX and uses it to
control panel exit/entry states.
When validating PSR with automated tests, grabbing CRC from sink
revealed stran
Signed-off-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dp.c | 14 ++
drivers/gpu/drm/i915/intel_drv.h | 5 -
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 150
According to VESA DP Spec, setting TEST_SINK_START (bit 0)
of TEST_SINK (00270h) "Stop/Start calculating CRC on the next frame"
So let's wait at least 1 vblank to really say the calculation
stopped or started.
Signed-off-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel
On 11/11/2015 01:07 AM, Chris Wilson wrote:
On Tue, Nov 10, 2015 at 03:27:36PM -0800, yu@intel.com wrote:
> From: Alex Dai
>
> We keep a copy of GuC fw in a GEM obj. However its content is lost
> if the GEM obj is swapped (igt/gem_evict_*). Therefore, the later
> fw loading during GPU rese
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> v2: Use _unsafe (Jani)
>
> Signed-off-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_params.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> 3 files change
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will
> prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is
From: Ville Syrjälä
The setcrtc ioctl ignores the fb_id when there's no mode specified.
So passing -1 doens't make much sense. When there is a more, -1 means
to preserve the current fb.
Signed-off-by: Ville Syrjälä
---
lib/igt_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
From: Ville Syrjälä
Currently kms_flip leaks the state of the pipes from one subtest to the
next. Meaning a single pipe test can actually have two or more pipes
actually up and running, and similarly a two pipe test can have three
pipes running.
This is particularly nasty on IVB since one of the
On Wed, Nov 11, 2015 at 08:22:03PM +0200, Imre Deak wrote:
> On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > From: Ville Syrjälä
> >
> > Introduce intel_display_port_aux_power_domain() which simply returns
> > the appropriate AUX power domain for a specific port, and then
> > replac
From: Ville Syrjälä
Use kasprintf() to generate the "DPDDC-" name for the aux helper.
To deal with errors properly make intel_dp_aux_init() return something,
and adjust the caller to match. It seems we were also missing a
intel_dp_mst_encoder_cleanup() call on edp (non-port A) init failures,
so
From: Ville Syrjälä
v2: Split up the ctl vs. data reg handling like in the normal AUX code
Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_psr.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/d
From: Ville Syrjälä
Rather than computing on demand, store also the aux data reg
offsets under intel_dp.
v2: Duplicate some code to make things less magic (Jani)
v3: Use PORT_B registers for invalid ports in g4x_aux_data_reg()
Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
---
driver
From: Ville Syrjälä
Instead of checking what aux_ch_ctl_reg is, we can simply check the port
when determining the right timeout value to program.
v2: Reorder patches to reduce churn (Chris)
Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson (v1)
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
From: Ville Syrjälä
Chris requested that I try to reorder the DP AUX patches in the last
register type safety series [1] to form a better story. Here is the
result. The final code is exactly the same as before (apart from the
kasprintf() changes), so I kept the previous r-b's in place, with
some
From: Ville Syrjälä
Currently we determine the location of the AUX registers in a confusing
way. First we assume the PCH registers are used always, but then we
override it for everything but HSW/BDW to use DP+0x10. Very confusing.
Let's just make it straightforward and simply add a few functions
From: Ville Syrjälä
v2: Keep some MISSING_CASE() stuff (Jani)
s/-1/-PIPE_B/ in the register macro
Fix typo in patch subject
v3: Use PORT_B registers for invalid ports in g4x_aux_ctl_reg() (Jani)
v4: Reorder patches (Chris)
Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula (v3)
Revi
From: Ville Syrjälä
Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
under dev_priv, like we for DSI and GPIO for example.
TODO: could probably move a bunch of this kind of stuff into the device
info instead...
v2: Drop the spurious whitespace change (Jani)
Reviewed-by: Ja
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> From: Ville Syrjälä
>
> Introduce intel_display_port_aux_power_domain() which simply returns
> the appropriate AUX power domain for a specific port, and then
> replace
> the intel_display_port_power_domain() with calls to the new functio
On 11.11.2015 16:21, Jani Nikula wrote:
On Wed, 11 Nov 2015, Ander Conselvan De Oliveira wrote:
On Tue, 2015-11-10 at 14:53 +0200, Jani Nikula wrote:
Ander, Maarten, where are we with this? Is it horribly wrong to merge
the original patch in this ever-growing and diverging thread?
I think
On Wed, Nov 11, 2015 at 07:49:40PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 11, 2015 at 03:41:16PM -0200, Paulo Zanoni wrote:
> > 2015-11-11 15:32 GMT-02:00 :
> > > From: Ville Syrjälä
> > >
> > > Currently kms_flip leaks the state of the pipes from one subtest to the
> > > next. Meaning a singl
On Wed, Nov 11, 2015 at 03:41:16PM -0200, Paulo Zanoni wrote:
> 2015-11-11 15:32 GMT-02:00 :
> > From: Ville Syrjälä
> >
> > Currently kms_flip leaks the state of the pipes from one subtest to the
> > next. Meaning a single pipe test can actually have two or more pipes
> > actually up and running
2015-11-11 15:32 GMT-02:00 :
> From: Ville Syrjälä
>
> Currently kms_flip leaks the state of the pipes from one subtest to the
> next. Meaning a single pipe test can actually have two or more pipes
> actually up and running, and similarly a two pipe test can have three
> pipes running.
>
> This i
On Wed, Nov 11, 2015 at 07:24:40PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 11, 2015 at 05:20:10PM +, Chris Wilson wrote:
> > On Wed, Nov 11, 2015 at 07:11:28PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > We try to convert the old way of of specifyi
From: Ville Syrjälä
To make more multi-pipe tests run on IVB, do the modesets in the reverse
order (ie. pipe C first, pipe A last). This way pipe B can't reserve the
2 shared FDI lanes before pipe C is set up.
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 2 +-
1 file changed, 1 insertio
From: Ville Syrjälä
Print the pipes and connectors in a human readable form instead of using
the integer IDs.
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
From: Ville Syrjälä
Currently kms_flip leaks the state of the pipes from one subtest to the
next. Meaning a single pipe test can actually have two or more pipes
actually up and running, and similarly a two pipe test can have three
pipes running.
This is particularly nasty on IVB since one of the
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
tests/kms_flip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 23dadad..af1ccfb 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -1449,6 +1449,7 @@ static void run_test_on_crtc_set(struct
On Wed, Nov 11, 2015 at 05:20:10PM +, Chris Wilson wrote:
> On Wed, Nov 11, 2015 at 07:11:28PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We try to convert the old way of of specifying fb tiling (obj->tiling)
> > into the new fb modifiers. We store the result
On Wed, Nov 11, 2015 at 07:11:28PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We try to convert the old way of of specifying fb tiling (obj->tiling)
> into the new fb modifiers. We store the result in the passed in mode_cmd
> structure. But that structure comes directly
From: Ville Syrjälä
We try to convert the old way of of specifying fb tiling (obj->tiling)
into the new fb modifiers. We store the result in the passed in mode_cmd
structure. But that structure comes directly from the addfb2 ioctl, and
gets copied back out to userspace, which means we're clobberi
From: Ville Syrjälä
Make sure the kernel doesn't clobber the modifiers when the user didn't
pass any.
Signed-off-by: Ville Syrjälä
---
tests/kms_addfb_basic.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index d466e4d..73000d
From: Ville Syrjälä
Drivers shouldn't clobber the passed in addfb ioctl parameters.
i915 was doing just that. To prevent it from happening again,
pass the struct around as const, starting all the way from
internal_framebuffer_create().
Signed-off-by: Ville Syrjälä
---
I tried to cross-compile e
When this option is 0 (so the power well support is disabled) we are
supposed to enable all power wells once and don't disable them unless we
system suspend the device. Currently if the option is 0, we can call the
power well enable handlers multiple times, whenever their refcount
changes from 0->1
From: Tim Gore
when checking to make sure that the driver has performed
the expected number of resets, this test looks at the
reset_count, which is incremented each time the GPU is
reset. Upcoming changes in the way GPU hangs are handled
mean that in most cases (and in all the cases in this
test)
Clear the pipe's dpll_hw_state when choosing the PLL for CRT on DDI
platforms. Otherwise stale values might cause the state checker to
complain.
Should fix errors like below:
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.wrpll
Cc: Gabriel Feceoru
Cc: Daniel Vetter
Cc:
On Thu, 05 Nov 2015, Lukas Wunner wrote:
> Minor fixup to d0669d007542 ("drm/i915: Clean up LVDS register
> handling") which intended to read lvds_reg just once at the
> beginning of intel_lvds_init() and use that throughout the rest
> of the function but accidentally missed one register readout.
Em Qua, 2015-11-11 às 16:27 +0200, Ville Syrjälä escreveu:
> On Tue, Nov 10, 2015 at 02:04:48PM +0100, Maarten Lankhorst wrote:
> > Op 10-11-15 om 13:20 schreef Zanoni, Paulo R:
> > > Em Ter, 2015-11-10 às 11:22 +0100, Maarten Lankhorst escreveu:
> > > > Op 04-11-15 om 20:10 schreef Paulo Zanoni:
>
Hi,
On 10/11/15 16:02, Vinay Belgaumkar wrote:
v1: These tests exercise the userptr ioctl to create shared buffers
Normally we don't put v1 at the beginning of the commit message.
between CPU and GPU. They contain error and normal usage scenarios.
They also contain a couple of stress tests
Reduced the Sleep period to 200mS and reduced the repetition count to 7
to decrease the test run time significantly.
v2: Changed uS to us
v3: removed the output formatting change as the issue will be addressed
in a seperate patch from Thomas Wood.
v4: mS -> ms
Signed-off-by: Derek Morton
---
te
When disable_noatomic is called plane_mask is not reliable yet,
and plane_state->visible = true even after disabling the primary plane.
Fix this by unsetting plane->visible if it was visible, and calling
disable_planes with the primary plane as mask.
The other planes are already disabled in intel
On Tue, Nov 10, 2015 at 02:04:48PM +0100, Maarten Lankhorst wrote:
> Op 10-11-15 om 13:20 schreef Zanoni, Paulo R:
> > Em Ter, 2015-11-10 às 11:22 +0100, Maarten Lankhorst escreveu:
> >> Op 04-11-15 om 20:10 schreef Paulo Zanoni:
> >>> In function find_compression_threshold() we try to over-allocat
Op 11-11-15 om 14:39 schreef Zanoni, Paulo R:
> Em Ter, 2015-11-10 às 14:04 +0100, Maarten Lankhorst escreveu:
>> Op 10-11-15 om 13:20 schreef Zanoni, Paulo R:
>>> Em Ter, 2015-11-10 às 11:22 +0100, Maarten Lankhorst escreveu:
Op 04-11-15 om 20:10 schreef Paulo Zanoni:
> In function find_c
On Wed, 11 Nov 2015, Ander Conselvan De Oliveira wrote:
> On Tue, 2015-11-10 at 14:53 +0200, Jani Nikula wrote:
>> Ander, Maarten, where are we with this? Is it horribly wrong to merge
>> the original patch in this ever-growing and diverging thread?
>
> I think the patch as is will cause problems
There was a wonderful period after
commit 6dda730e55f412a6dfb181cae6784822ba463847
Author: Jani Nikula
Date: Tue Jun 24 18:27:40 2014 +0300
drm/i915: respect the VBT minimum backlight brightness
However everything is changed after
commit e6755fb78e8f20ecadf2a4080084121336624ad9
Author: J
Em Ter, 2015-11-10 às 14:04 +0100, Maarten Lankhorst escreveu:
> Op 10-11-15 om 13:20 schreef Zanoni, Paulo R:
> > Em Ter, 2015-11-10 às 11:22 +0100, Maarten Lankhorst escreveu:
> > > Op 04-11-15 om 20:10 schreef Paulo Zanoni:
> > > > In function find_compression_threshold() we try to over-
> > > >
On Wed, 11 Nov 2015, Derek Morton wrote:
> Reduced the Sleep period to 200mS and reduced the repetition count to 7
> to decrease the test run time significantly.
>
> v2: Changed uS to us
The electrical engineer in me insists on v4 changing mS to ms, as we're
talking about time, not conductance. ;
The i_boost level in the DDI translation tables are stored per level.
However, skl_ddi_set_iboos() would choose an entry of that table based
on the port argument.
Cc: Jim Bride
Signed-off-by: Ander Conselvan de Oliveira
---
I noticed this while reviewing Jim's patch that updates Skylake's DDI
On Wed, Nov 11, 2015 at 02:05:57PM +0200, Jani Nikula wrote:
> On Wed, 11 Nov 2015, "Shih-Yuan Lee (FourDollars)"
> wrote:
> > Take Dell XPS 13 (2015) as an example. The vbt min 10 out of [0..255].
> > The PWM max is 937 so the corresponding PWM min is 37 (10*937/256).
> > This commit makes the s
On Fri, 2015-11-06 at 15:30 -0800, Jim Bride wrote:
> While comparing the B-Spec with the code I noticed that several
> values in these tables have been updated in the spec, so I
> changed the code to match..
>
> Cc: Rodrigo Vivi
> Signed-off-by: Jim Bride
Reviewed-by: Ander Conselvan de Olivei
On Wed, Nov 11, 2015 at 04:06:10PM +0530, ankitprasad.r.sha...@intel.com wrote:
> @@ -4399,14 +4399,15 @@ struct drm_i915_gem_object
> *i915_gem_alloc_object(struct drm_device *dev,
> struct drm_i915_gem_object *obj;
> struct address_space *mapping;
> gfp_t mask;
> + int ret
On Wed, 11 Nov 2015, "Shih-Yuan Lee (FourDollars)" wrote:
> Take Dell XPS 13 (2015) as an example. The vbt min 10 out of [0..255].
> The PWM max is 937 so the corresponding PWM min is 37 (10*937/256).
> This commit makes the sysfs brightness 1 map to the PWM brightness 37
> and 100 map to the PWM
Hi,
On Tue, Sep 29, 2015 at 04:33:07PM +0100, Damien Lespiau wrote:
> Hi all,
>
> You may have noticed already, patchwork.freedesktop.org looks different.
>
> That new version includes:
> - Some re-design. Design is very much an iterative process, thoughts
> and comments are welcome,
> - S
On Tue, Nov 10, 2015 at 05:27:55PM +0100, Lukas Wunner wrote:
> Hi Ville,
>
> On Mon, Nov 09, 2015 at 01:00:50PM +0200, Ville Syrjälä wrote:
> > On Sun, Nov 08, 2015 at 05:44:37PM +0100, Lukas Wunner wrote:
> > > Hi Ville,
> > >
> > > On Fri, Nov 06, 2015 at 03:08:33PM +0200, ville.syrj...@linux.
On Wed, Nov 11, 2015 at 04:06:09PM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> Extend the drm_i915_gem_create structure to add support for
> creating Stolen memory backed objects. Added a new flag through
> which user can specify the preference to allocate the obje
On Wed, Nov 11, 2015 at 04:06:08PM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> This patch adds support for clearing buffer objects via CPU/GTT. This
> is particularly useful for clearing out the non shmem backed objects.
> Currently intend to use this only for buff
Hi Dave, I seem to be off-sync with your pulls to Linus... anyway,
here's one uapi build fix I've picked up.
BR,
Jani.
The following changes since commit f36203be608a38a5b5523a7aa52cc72f757b9679:
drm/dp: Add dp_aux_i2c_speed_khz module param to set the assume i2c bus speed
(2015-09-02 16:13:
On Wed, Nov 11, 2015 at 04:06:13PM +0530, ankitprasad.r.sha...@intel.com wrote:
> +swap_pages:
> + stolen_pages = obj->pages;
> + obj->pages = NULL;
> +
> + obj->base.filp = file;
> + obj->base.read_domains = I915_GEM_DOMAIN_CPU;
> + obj->base.write_domain = I915_GEM_DOMAIN_CPU;
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
From: Ankitprasad Sharma
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface. This will cover objects backed by stolen memory as well
as other non-shmem backed objects.
v2: Drop locks around slow_user
From: Ankitprasad Sharma
Propagating correct error codes to userspace by using ERR_PTR and
PTR_ERR macros for stolen memory based object allocation. We generally
return -ENOMEM to the user whenever there is a failure in object
allocation. This patch helps user to identify the correct reason for t
From: Chris Wilson
Ville reminded us that stolen memory is not preserved across
hibernation, and a result of this was that context objects now being
allocated from stolen were being corrupted on S4 and promptly hanging
the GPU on resume.
We want to utilise stolen for as much as possible (nothing
From: Ankitprasad Sharma
This patch series adds support for creating/using Stolen memory backed
objects.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the
From: Ankitprasad Sharma
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify the preference to allocate the object from
stolen memory, which if set, an attempt will be made to allocate
the object from s
From: Ankitprasad Sharma
This patch adds support for clearing buffer objects via CPU/GTT. This
is particularly useful for clearing out the non shmem backed objects.
Currently intend to use this only for buffers allocated from stolen
region.
v2: Added kernel doc for i915_gem_clear_object(), corre
Reduced the Sleep period to 200mS and reduced the repetition count to 7
to decrease the test run time significantly.
v2: Changed uS to us
v3: removed the output formatting change as the issue will be addressed
in a seperate patch from Thomas Wood.
Signed-off-by: Derek Morton
---
tests/gem_exec_
Hi Thomas,
I have ran with your patches on android. The IGT_PLAIN_OUTPUT environment
variable works fine for me. My only comment would be that it should be
documented somewhere.
I will remove the formatting change from my gem_exec_nop patch as with this I
don't think it is needed.
//Derek
--
On Tue, 2015-11-10 at 14:53 +0200, Jani Nikula wrote:
> On Wed, 14 Oct 2015, Daniel Vetter wrote:
> > On Wed, Oct 14, 2015 at 04:58:55PM +0300, Ander Conselvan De Oliveira wrote:
> > > On Wed, 2015-10-14 at 14:44 +0200, Daniel Vetter wrote:
> > > > On Wed, Oct 14, 2015 at 11:21:46AM +0300, Ander C
On Tue, Nov 10, 2015 at 03:27:36PM -0800, yu@intel.com wrote:
> From: Alex Dai
>
> We keep a copy of GuC fw in a GEM obj. However its content is lost
> if the GEM obj is swapped (igt/gem_evict_*). Therefore, the later
> fw loading during GPU reset will fail. Mark the obj dirty after
> copying
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