== Series Details ==
Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
(rev3)
URL : https://patchwork.freedesktop.org/series/4446/
State : warning
== Summary ==
Series 4446v3 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno
write
http://patchwork.
On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> is enabled when the cdclk is less then require
On Tue, 2016-03-15 at 14:26 +0100, Daniel Vetter wrote:
> On Tue, Mar 15, 2016 at 01:38:58PM +0200, Mika Kahola wrote:
> > Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326
> > DP to VGA adapter. Having said that, I haven't noticed a need for
> > additional delay between DPCD r
== Series Details ==
Series: drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs (rev3)
URL : https://patchwork.freedesktop.org/series//
State : failure
== Summary ==
Series v3 drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs
http://patchwork.freedesktop.org/api/1.0/series//
== Series Details ==
Series: drm/i915/bxt: add dsi transcoders
URL : https://patchwork.freedesktop.org/series/4483/
State : failure
== Summary ==
Series 4483v1 drm/i915/bxt: add dsi transcoders
http://patchwork.freedesktop.org/api/1.0/series/4483/revisions/1/mbox/
Test drv_module_reload_basic
It was noticed on bug #94087 that module parameter
i915.edp_vswing=2 that should override the VBT setting
to use default voltage swing (400 mV) was not applied
for Broadwell.
This patch provides a fix for this by checking if default
i.e. higher voltage swing is requested to be used and
applies the
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä
>
> All the values in the DSI PLL LFSR seed table fit into 9bits, so change
> the type to u16 from u32 to save a bit of space.
>
> drivers/gpu/drm/i915/i915.ko:
> -.rodata90824
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä
>
> On VLV at least, the BIOS may leave the DSI PLL enabled in some wonky
> state where it just refuses to lock. Simply disabling the PLL before
> reconfiguring it is not enough to fix it, but power ga
Tomi, noticed two things that maybe infrastructure related, see below:
On Wed, 2016-03-16 at 07:31 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs (rev3)
> URL : https://patchwork.freedesktop.org/series//
> State : failure
>
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Compute the DSI PLL parameters during .compute_config() rather than
> .pre_pll_enable() so that we can fail gracefully if we can't find
> suitable parameters.
>
> In order to do that we need to store the DSI PLL pa
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Use the proper refclock frequency (100MHz) when reading out the
> current DSI clock on CHV.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
> 1 fi
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> pgm_ratios in stored as a register value in pipe config, so let's dump
> this one as hex as well.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä
>
> Fold the DSI PLL configuration functions into the DSI PLL
> enable functions since they are small and not called from anywhere else.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
>
On Tue, 2016-03-15 at 16:37 -0700, Dongwon Kim wrote:
> For BXT, Polarity of PORT_PLL_REF_SEL is reversed in
> its description in Bspec. This bit should be set for
> "Non-SSC".
Thanks for the patch.
In the future please also mention where the change originates from, in
this case it is a recent up
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> These BUGs don't serve any purpose IMO. Throw them out.
>
> Signed-off-by: Ville Syrjälä
For some other things I might insist on replacing them with warns, but I
don't think these ones warrant that.
Reviewed-by:
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Avoid redundant crtc->pipe lookups by giving vlv_enable_pll() a local
> pipe variable. Also makes it look more like the corresponding CHV code.
>
> While at is change the CHV code to enum pipe from int,
>
> Signed-
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Supposedly the power sequencer still locks out the DPLL registers on
> CHV, so let's issue a warning if it's still locked when enabling the
> DPLL.
>
> Also drop the redundant IS_MOBILE() check for VLV when we chec
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> VLV DPLL is somewhat sane and doesn't run on luck.
>
> Signed-off-by: Ville Syrjälä
Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 11 ---
> 1 file changed, 11 deletions(-)
>
> di
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Check whether the DPLL is even enabled before readoing out the dividers
> and trying to derive port_clock on CHV. We already did this on VLV.
>
> Also remove the comment "MIPI" comment from the VLV code since we ca
On ti, 2016-03-15 at 14:14 +, Chris Wilson wrote:
> On Tue, Mar 15, 2016 at 04:01:14PM +0200, Imre Deak wrote:
> >
> > I'm not sure if you want to check all failure paths, I think for that
> > the existing failslab etc. mechanisms are better suited. This new
> > option would be used at relativ
On Wed, Mar 16, 2016 at 11:18:04AM +0200, Joonas Lahtinen wrote:
> On ti, 2016-03-15 at 14:14 +, Chris Wilson wrote:
> > On Tue, Mar 15, 2016 at 04:01:14PM +0200, Imre Deak wrote:
> > >
> > > I'm not sure if you want to check all failure paths, I think for that
> > > the existing failslab etc.
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä
>
> DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
> chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
> to either pipe B or C. So do that to make pixel repeat wor
On Wed, 2016-03-16 at 09:24 +, Chris Wilson wrote:
> On Wed, Mar 16, 2016 at 11:18:04AM +0200, Joonas Lahtinen wrote:
> > On ti, 2016-03-15 at 14:14 +, Chris Wilson wrote:
> > > On Tue, Mar 15, 2016 at 04:01:14PM +0200, Imre Deak wrote:
> > > >
> > > > I'm not sure if you want to check all
On Wed, 16 Mar 2016, Mika Kahola wrote:
> [ text/plain ]
> It was noticed on bug #94087 that module parameter
> i915.edp_vswing=2 that should override the VBT setting
> to use default voltage swing (400 mV) was not applied
> for Broadwell.
>
> This patch provides a fix for this by checking if defa
On Wed, Mar 16, 2016 at 11:43:14AM +0200, Imre Deak wrote:
> On Wed, 2016-03-16 at 09:24 +, Chris Wilson wrote:
> > On Wed, Mar 16, 2016 at 11:18:04AM +0200, Joonas Lahtinen wrote:
> > > On ti, 2016-03-15 at 14:14 +, Chris Wilson wrote:
> > > > On Tue, Mar 15, 2016 at 04:01:14PM +0200, Imre
On Tue, Mar 15, 2016 at 07:29:22PM -0500, Chris wrote:
> On Tue, 2016-03-15 at 19:17 -0400, Felix Miata wrote:
> > Chris composed on 2016-03-15 17:43 (UTC-0500):
> >
> > > On Tue, 2016-03-15 at 16:37 -0400, Felix Miata wrote:
> >
> > >> Chris composed on 2016-03-15 14:50 (UTC-0500):
> >
> > >> >
On Wed, 2016-03-16 at 10:04 +, Chris Wilson wrote:
> On Wed, Mar 16, 2016 at 11:43:14AM +0200, Imre Deak wrote:
> > On Wed, 2016-03-16 at 09:24 +, Chris Wilson wrote:
> > > On Wed, Mar 16, 2016 at 11:18:04AM +0200, Joonas Lahtinen wrote:
> > > > On ti, 2016-03-15 at 14:14 +, Chris Wilso
A small step moving us closer to DRM MIPI DSI code. Use enum
mipi_dsi_pixel_format instead of our own. The first benefit is being
able to use common mipi_dsi_pixel_format_to_bpp().
There's a little back and forth conversion with the VBT -> enum ->
register, since we have just shoved the VBT value
The enum mipi_dsi_pixel_format defines MIPI_DSI_FMT_RGB666 for the
"loose" 24 bpp format and MIPI_DSI_FMT_RGB666_PACKED for the 18 bpp
format. We have this the other way round, defining a loose version for
24 bpp.
Follow suit with what's in enum mipi_dsi_pixel_format to avoid future
confusion. Ren
== Series Details ==
Series: drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev10)
URL : https://patchwork.freedesktop.org/series/1609/
State : failure
== Summary ==
Series 1609v10 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
http://patchwork.freedesktop.org/api/1.0/series/1
On Wed, Mar 16, 2016 at 12:17:51PM +0200, Imre Deak wrote:
> On Wed, 2016-03-16 at 10:04 +, Chris Wilson wrote:
> > On Wed, Mar 16, 2016 at 11:43:14AM +0200, Imre Deak wrote:
> > > On Wed, 2016-03-16 at 09:24 +, Chris Wilson wrote:
> > > > On Wed, Mar 16, 2016 at 11:18:04AM +0200, Joonas La
Hide knowledge about VBT child devices in intel_bios.c.
v2: also move int_tv_support check to intel_bios.c (Sivakumar)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 41 ++
drivers/gpu/drm/i915/intel_t
Favor a single point of truth instead of duplicating the information.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_bios.c | 12 +++-
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/dr
We've been accumulating code across the driver that depends on the VBT
specific structures and defines. The VBT is an uncontrollable
beast. Encourage encapsulation of the VBT data by hiding the structures
and defines in a private header only to be included from intel_bios.c.
Signed-off-by: Jani Ni
Hide knowledge about VBT child devices in intel_bios.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 33 +
drivers/gpu/drm/i915/intel_dp.c | 21 +
3 files changed, 35 insertions(
Hide knowledge about VBT child devices in intel_bios.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 50
drivers/gpu/drm/i915/intel_lvds.c | 53 +--
3 files ch
Use the connector type instead of VBT directly to decide which backlight
mechanism to use on VLV/CHV. (Indirectly, this is the same thing, but
hides the VBT use.)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Hide knowledge about VBT child devices in intel_bios.c.
v2: Move port check to intel_bios.c (Sivakumar)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_bios.c | 39 ++-
drivers/gpu/drm/i915/intel_dsi.c | 1
On Wed, 2016-03-16 at 11:49 +0200, Jani Nikula wrote:
> On Wed, 16 Mar 2016, Mika Kahola wrote:
> > [ text/plain ]
> > It was noticed on bug #94087 that module parameter
> > i915.edp_vswing=2 that should override the VBT setting
> > to use default voltage swing (400 mV) was not applied
> > for Bro
The moves a couple of functions programming the gamma LUT and CSC
units into their own file.
On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
either
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor degamma/
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
v3: Refactor degamma/gamma LUTs load into a single function
v4: Remove unused variable
Signed-off-by: Shashank Sharma
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
Signed-off-by: Lionel Landwerlin
Rev
This series introduces pipe level color management for Intel platforms
on CherryView and Broadwell on.
This series is based of a previous set of patches by Shashank Sharma.
Cheers,
Lionel
v9: Rebase on nightly
v10: Mask GAMMA_MODE register value (Matt Roper)
Cleanup legacy LUT helper (Emi
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.
v2: Read GAMMA_MODE register value at init (Matt Roper's comment)
v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
with other registers (Matt Roper's comment).
v4: Mask GAMMA_MODE
From: Tvrtko Ursulin
Some trivial ones, first pass done with Coccinelle:
@@
@@
(
- I915_NUM_RINGS
+ I915_NUM_ENGINES
|
- intel_ring_flag
+ intel_engine_flag
|
- for_each_ring
+ for_each_engine
|
- i915_gem_request_get_ring
+ i915_gem_request_get_engine
|
- intel_ring_idle
+ intel_engine_idle
|
-
From: Tvrtko Ursulin
This time using only sed and a few by hand.
v2: Rename also intel_ring_id and intel_ring_initialized.
v3: Fixed typo in intel_ring_initialized.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_dma.c
From: Tvrtko Ursulin
From ring to engine, by the virtue of Coccinelle patch
below and a couple manual fixups.
@@
identifier I, J;
@@
struct I {
...
- struct intel_engine_cs *J;
+ struct intel_engine_cs *engine;
...
}
@@
identifier I, J;
@@
struct I {
...
- struct intel_engine_cs J;
+ struct inte
Hi Dave, I'll just flush this one out of the way.
BR,
Jani.
The following changes since commit f2c488212b511f7eadef78c564f1bff8f64db231:
Merge branch 'linux-4.6' of git://github.com/skeggsb/linux into drm-next
(2016-03-14 10:49:40 +1000)
are available in the git repository at:
git://anon
On Wed, Mar 16, 2016 at 11:00:40AM +, Tvrtko Ursulin wrote:
> if (!i915.enable_execlists) {
> dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
> - dev_priv->gt.init_rings = i915_gem_init_rings;
> - dev_priv->gt.cleanup_ring = intel_cleanu
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