It's a little overkill?
They just need to know if the cache tables have changed and to be able to sync
their indexes to the KMD.
Also you have to decode the L3CC (two 16 bit values in a 32 bit register) and
seems a bit unfriendly. Also you will need to know what the bits mean to detect
where th
On Wed, May 04, 2016 at 03:22:51PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Report command parser version 0 if disabled
> URL : https://patchwork.freedesktop.org/series/6736/
> State : failure
>
> == Summary ==
>
> Series 6736v1 drm/i915: Report command parser versi
On 5/3/2016 9:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling reasier for the plane code
typo "easier" :) otherwise fine. thanks for upl
On 5/3/2016 9:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling reasier for the plane code
typo "easier" :) thanks for uploading again.
Re
Reviewed-by: Sivakumar Thulasimani
On 5/3/2016 9:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
intel_compute_page_offset() can dig up the correct pitch from the fb
itself, no need for the caller to pass it in.
A bit of extra care is needed for the lower level
_intel_compute
On Sun, May 01, 2016 at 09:15:03AM +0100, Chris Wilson wrote:
> This effectively reverts
>
> commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
> Author: Chris Wilson
> Date: Wed Jun 10 15:58:01 2015 +0100
>
> drm: Avoid the double clflush on the last cache line in
> drm_clflush_virt_range()
Reviewed-by: Sivakumar Thulasimani
On 5/3/2016 9:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
We repeat the SKL stride register value calculations a several places.
Move it into a small helper function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display
Reviewed-by: Sivakumar Thulasimani
On 5/3/2016 9:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
intel_compute_tile_offset() and intel_add_fb_offsets() get passed the fb
and the rotation. As both of those come from the plane state we can just
pass that in instead.
For extra
On 04/05/16 13:38, Maarten Lankhorst wrote:
It turns out that preserving framebuffers after the rmfb call breaks
vmwgfx userspace. This was originally introduced because it was thought
nobody relied on the behavior, but unfortunately it seems there are
exceptions.
drm_framebuffer_remove may fai
Hi,
On 04/05/16 13:10, Maarten Lankhorst wrote:
Add some tests to BAT to ensure rmfb/lastclose handling doesn't break again.
The test will set framebuffers on each crtc, and then try rmfb or close.
Afterwards it rechecks to make sure the framebuffers are removed.
Signed-off-by: Maarten Lankho
We can forgo queuing the hangcheck from the start of every request to
until we wait upon a request. This reduces the overhead of every
request, but may increase the latency of detecting a hang. Howeever, if
nothing every waits upon a hang, did it ever hang? It also improves the
robustness of the wa
We have testcases to ensure that seqno wraparound works fine, so we can
forgo forcing everyone to encounter seqno wraparound during early
uptime. seqno wraparound incurs a full GPU stall so not forcing it
will eliminate one jitter from the early system. Using the testcases, we
have very determinist
The queue only ever contains at most one item and has no special flags.
It is just a very simple wrapper around the system-wq - a complication
with no benefits.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_dma.c | 8
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i9
On Ironlake, there is no command nor register to ensure that the write
from a MI_STORE command is completed (and coherent on the CPU) before the
command parser continues. This means that the ordering between the seqno
write and the subsequent user interrupt is undefined (like gen6+). So to
ensure t
As we inspect obj->active to decide how many objects we can shrink (we
only shrink idle objects), it helps to flush the active lists first
in order to have a more accurate count of available objects.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 ++
1 file changed,
This effectively reverts
commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
Author: Chris Wilson
Date: Wed Jun 10 15:58:01 2015 +0100
drm: Avoid the double clflush on the last cache line in
drm_clflush_virt_range()
as we have observed issues with serialisation of the clflush operations
on B
Move all of the constant assignments up front and into a common
function. This is primarily to ensure the backpointers are set as early
as possible for later use during initialisation.
v2: Use a constant struct so that all the similar values are set
together.
v3: Sanitize the engine's IMR to disab
By using the same address for storing the HWS on every platform, we can
remove the platform specific vfuncs and reduce the get-seqno routine to
a single read of a cached memory location.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_
If we flag the seqno as potentially stale upon receiving an interrupt,
we can use that information to reduce the frequency that we apply the
heavyweight coherent seqno read (i.e. if we wake up a chain of waiters).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 15
If we have multiple waiters, we may find that many complete on the same
wake up. If we first inspect the seqno from the CPU cache, we may reduce
the number of heavyweight coherent seqno reads we require.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 14 ++
1 file
Borrow the idea from intel_lrc.c to precompute the mask of interrupts we
wish to always enable to avoid having lots of conditionals inside the
interrupt enabling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +++--
drivers/gpu/drm/i915/
If we convert the tracing over from direct use of ring->irq_get() and
over to the breadcrumb infrastructure, we only have a single user of the
ring->irq_get and so we will be able to simplify the driver routines
(eliminating the redundant validation and irq refcounting).
v2: Move to a signaling fr
Since the function is a small wrapper around schedule_delayed_work(),
move it inline to remove the function call overhead for the principle
caller.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 17 -
drivers/gpu/drm/i915/i915_irq.c | 16
2 fil
With only a single callsite for intel_engine_cs->irq_get and ->irq_put,
we can reduce the code size by moving the common preamble into the
caller, and we can also eliminate the reference counting.
For completeness, as we are no longer doing reference counting on irq,
rename the get/put vfunctions
Now that we have split out the seqno-barrier from the
engine->get_seqno() callback itself, we can move the users of the
seqno-barrier to the required callsites simplifying the common code and
making the required workaround handling much more explicit.
Signed-off-by: Chris Wilson
---
drivers/gpu/
One particularly stressful scenario consists of many independent tasks
all competing for GPU time and waiting upon the results (e.g. realtime
transcoding of many, many streams). One bottleneck in particular is that
each client waits on its own results, but every client is woken up after
every batch
Since the tests can and do explicitly check debugfs/i915_ring_missed_irqs
for the handling of a "missed interrupt", adding it to the dmesg at INFO
is just noise. When it happens for real, we still class it as an ERROR.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 3 ---
1 fi
Avoid the two calls to ktime_get_raw_ns() (at best it reads the TSC) as
we only need to compute the elapsed time for a timed wait.
v2: Eliminate the unused local variable reducing the function size by 64
bytes (using the storage space on the callers stack rather than adding
to our stack frame)
Si
If we fail to setup the debugfs we lose debugging convenience, but we
should still endeavour to enable modesetting so that we can control the
outputs and enable use of the system to debug the issue. In all
likelihood if we can not create our debugfs files then there is a larger
underlying issue tha
Reviewed-by: Sivakumar Thulasimani
On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
If there's a fence on the object it will be aligned to the start
of the object, and hence CPU rendering to any fb that straddles
the fence edge will come out wrong due
Allowing register copies where the source and destination are both
whitelisted should be safe, and is useful. For example, Mesa uses
this to load the command streamer math registers with data from the
pipeline statistics counters.
Signed-off-by: Kenneth Graunke
---
drivers/gpu/drm/i915/i915_cmd
Hi,
On 05/05/16 10:15, Chris Wilson wrote:
Move all of the constant assignments up front and into a common
function. This is primarily to ensure the backpointers are set as early
as possible for later use during initialisation.
v2: Use a constant struct so that all the similar values are set
t
As i915_ppgtt_init() is not used outside of i915_gem_gtt.c we can make
it static.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt
== Series Details ==
Series: drm: Continue after failure to setup debugfs
URL : https://patchwork.freedesktop.org/series/6770/
State : success
== Summary ==
Series 6770v1 drm: Continue after failure to setup debugfs
http://patchwork.freedesktop.org/api/1.0/series/6770/revisions/1/mbox/
Test d
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, May 05, 2016 at 11:18:41AM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 05/05/16 10:15, Chris Wilson wrote:
> >Move all of the constant assignments up front and into a common
> >function. This is primarily to ensure the backpointers are set as early
> >as possible for later use during init
== Series Details ==
Series: drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers.
URL : https://patchwork.freedesktop.org/series/6774/
State : success
== Summary ==
Series 6774v1 drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted
registers.
http://patchwork.freedesktop.or
On Thu, May 05, 2016 at 03:06:49AM -0700, Kenneth Graunke wrote:
> Allowing register copies where the source and destination are both
> whitelisted should be safe, and is useful. For example, Mesa uses
> this to load the command streamer math registers with data from the
> pipeline statistics coun
== Series Details ==
Series: drm/i915: Unexport i915_ppgtt_init()
URL : https://patchwork.freedesktop.org/series/6775/
State : success
== Summary ==
Series 6775v1 drm/i915: Unexport i915_ppgtt_init()
http://patchwork.freedesktop.org/api/1.0/series/6775/revisions/1/mbox/
bdw-nuci7-2 tota
On 05/05/16 11:33, Chris Wilson wrote:
On Thu, May 05, 2016 at 11:18:41AM +0100, Tvrtko Ursulin wrote:
Hi,
On 05/05/16 10:15, Chris Wilson wrote:
Move all of the constant assignments up front and into a common
function. This is primarily to ensure the backpointers are set as early
as possibl
On Thu, May 05, 2016 at 12:15:40PM +0100, Tvrtko Ursulin wrote:
>
> On 05/05/16 10:15, Chris Wilson wrote:
> >@@ -3186,7 +3181,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> > if (i915_gem_request_completed(from_req, true))
> > return 0;
> >
> >-if (!i915_semaph
On Thu, May 05, 2016 at 10:11:27AM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 04/05/16 13:10, Maarten Lankhorst wrote:
> >Add some tests to BAT to ensure rmfb/lastclose handling doesn't break again.
> >
> >The test will set framebuffers on each crtc, and then try rmfb or close.
> >Afterwards it
On Thu, May 05, 2016 at 10:07:57AM +0100, Tvrtko Ursulin wrote:
>
> On 04/05/16 13:38, Maarten Lankhorst wrote:
> >It turns out that preserving framebuffers after the rmfb call breaks
> >vmwgfx userspace. This was originally introduced because it was thought
> >nobody relied on the behavior, but u
On Thu, May 05, 2016 at 10:47:10AM +0100, Chris Wilson wrote:
> If we fail to setup the debugfs we lose debugging convenience, but we
> should still endeavour to enable modesetting so that we can control the
> outputs and enable use of the system to debug the issue. In all
> likelihood if we can no
On 26/04/2016 14:20, Daniel Vetter wrote:
On Mon, Apr 25, 2016 at 10:54:27AM +0100, Chris Wilson wrote:
As each batch buffer completes, it raises an interrupt which wakes up
the scheduler. Note that it is possible for multiple buffers to
complete before the IRQ handler gets to run. Further, the
On 05/05/16 12:17, Tvrtko Ursulin wrote:
On 05/05/16 11:33, Chris Wilson wrote:
On Thu, May 05, 2016 at 11:18:41AM +0100, Tvrtko Ursulin wrote:
Hi,
On 05/05/16 10:15, Chris Wilson wrote:
Move all of the constant assignments up front and into a common
function. This is primarily to ensure t
On Thu, May 05, 2016 at 01:53:57PM +0200, Daniel Vetter wrote:
> On Thu, May 05, 2016 at 10:47:10AM +0100, Chris Wilson wrote:
> > If we fail to setup the debugfs we lose debugging convenience, but we
> > should still endeavour to enable modesetting so that we can control the
> > outputs and enable
On Thu, May 05, 2016 at 11:12:36AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Unexport i915_ppgtt_init()
> URL : https://patchwork.freedesktop.org/series/6775/
> State : success
>
> == Summary ==
>
> Series 6775v1 drm/i915: Unexport i915_ppgtt_init()
> http://patchwor
On 26/04/2016 10:11, Peter Antoine wrote:
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_guc_reg.h | 5 +++--
drivers/gpu/drm
The attached version still does not explain that the WOPCM_TOP is to tell the
GuC not to use that space.
The extra information does not aid anybody as the information is used
internally within the GuC.
But, I have not actual objection to the patch.
Peter.
-Original Message-
From: Gordo
On 04/05/16 15:30, Ville Syrjälä wrote:
On Wed, May 04, 2016 at 02:40:34PM +0100, Lionel Landwerlin wrote:
We are currently missing the color management update condition to
commit planes on crtc.
v2: add comment about moving the commit of color management registers
to an async worker
v3:
Command parser version 7 introduces the ability to copy between
regsiters from the Haswell RCS with MI_LOAD_REGISTER_REG. This provides
a quick smoketest of that ability.
Signed-off-by: Chris Wilson
---
tests/gem_exec_parse.c | 76 ++
1 file change
Fixed a rebase mistake where I dropped the use of the igt_ioctl wrapper in
do_ioctl().
I'm not entirely sure a.t.m whether the assertion change from ret == 0 to
ret >= 0 will break anything, though comparing run-tests.sh -s -t basic
before/after didn't seem to highlight a problem for me.
--- >8
On 05/05/2016 15:02, Antoine, Peter wrote:
The attached version still does not explain that the WOPCM_TOP is to tell the
GuC not to use that space.
That's NOT what WOPCM_TOP means. The GuC is allowed to use the space up
to the value stored in the GUC_WOPCM_SIZE register (as the comment above
I would Cc it to stable just in case tbh. I picked up on this one since KASAN
was picking up on some of the memcpy() calls around here going out of bounds. I
can include some of the backtraces from that if needed.
On Wed, 2016-05-04 at 19:11 +0200, Daniel Vetter wrote:
> On Wed, May 04, 2016 at 11
On Thu, May 05, 2016 at 04:06:02PM +0100, Robert Bragg wrote:
> Fixed a rebase mistake where I dropped the use of the igt_ioctl wrapper in
> do_ioctl().
>
> I'm not entirely sure a.t.m whether the assertion change from ret == 0 to
> ret >= 0 will break anything, though comparing run-tests.sh -s -t
On Thu, May 5, 2016 at 4:59 PM, Chris Wilson
wrote:
> On Thu, May 05, 2016 at 04:06:02PM +0100, Robert Bragg wrote:
> > Fixed a rebase mistake where I dropped the use of the igt_ioctl wrapper
> in
> > do_ioctl().
> >
> > I'm not entirely sure a.t.m whether the assertion change from ret == 0 to
>
arch/x86/kernel/early-quirks.c: In function ‘intel_graphics_stolen’:
arch/x86/kernel/early-quirks.c:539:9: warning: format ‘%llx’ expects
argument of type ‘long long unsigned int’, but argument 2 has type
‘phys_addr_t’ [-Wformat=]
"0x%llx-0x%llx\n", base, base + size - 1);
^
arch
== Series Details ==
Series: x86: Silence 32bit compiler warning in intel_graphics_stolen()
URL : https://patchwork.freedesktop.org/series/6788/
State : success
== Summary ==
Series 6788v1 x86: Silence 32bit compiler warning in intel_graphics_stolen()
http://patchwork.freedesktop.org/api/1.0/s
Hi Dave, Daniel,
This is a regression causing many failures in intel-gfx CI.
[ 295.164523] [drm:drm_debugfs_init] *ERROR* Cannot create
/sys/kernel/debug/dri/0
[ 295.164531] [drm:drm_minor_register] *ERROR* DRM: Failed to
initialize /sys/kernel/debug/dri.
[ 295.167544] i915: probe of 000
I am running a computer based on the i3-6100 and trying to address
overscan on a HDMI-connected TV that does not have overscan correction
capability. Does kms_panel_fitting offer similar capability to the
intel_panel_fitter? If so, how is it used? Thanks.
On 29/04/2016 16:44, Tvrtko Ursulin wrote:
On 27/04/16 19:03, Dave Gordon wrote:
Mostly little optimisations; for instance, if the driver is correctly
following the submission protocol, the "out of space" condition is
impossible, so the previous runtime WARN_ON() is promoted to a
GEM_BUG_ON() f
Em Qui, 2016-05-05 às 19:45 +0200, Stefan Richter escreveu:
> On Apr 30 Stefan Richter wrote:
> >
> > On Apr 29 Stefan Richter wrote:
> > >
> > > On Apr 26 Stefan Richter wrote:
> > > >
> > > > v4.6-rc solidly hangs after a short while after boot, login to
> > > > X11, and
> > > > doing nothin
On Fri, Apr 29, 2016 at 06:13:33PM -0700, Manasi Navare wrote:
> This is the userspace component of the Displayport Compliance testing
> software required for compliance testing of the I915 Display Port
> driver. This must be running in order to successfully complete Display
> Port compliance t
On Thu, May 05, 2016 at 06:50:14PM +, Zanoni, Paulo R wrote:
> Em Qui, 2016-05-05 às 19:45 +0200, Stefan Richter escreveu:
> > On Apr 30 Stefan Richter wrote:
> > >
> > > On Apr 29 Stefan Richter wrote:
> > > >
> > > > On Apr 26 Stefan Richter wrote:
> > > > >
> > > > > v4.6-rc solidly han
dma-buf new API consists of:
- mmap(dma_buf_fd, ...): the ability to map a dma-buf file-descriptor of a
graphics buffer to the userspace, and more importantly, to actually write on
the mapped pointer (which was not possible before). It’s worth noting that the
Direct Rendering Manager (DRM) and the
Em Sex, 2016-05-06 às 00:54 +0200, Stefan Richter escreveu:
> On May 05 Zanoni, Paulo R wrote:
> >
> > Em Qui, 2016-05-05 às 19:45 +0200, Stefan Richter escreveu:
> > >
> > > Oh, and in case you - the person reading this commit message
> > > - found
> > > this commit through git bisect, p
This stores a known value to a register, copies it using
MI_LOAD_REGISTER_REG, then stores from the second register back to
memory, and verifies the value. This ensures that MI_LOAD_REGISTER_REG
is allowed by the command parser, and actually takes effect.
Cc: Chris Wilson
Signed-off-by: Kenneth
On Thu, May 05, 2016 at 10:45:31PM +0200, Stefan Richter wrote:
> On May 05 Stefan Richter wrote:
> > Quoting the changelog of the commit:
> [...]
> > - Download intel-gpu-tools, compile it, and run:
> >$ sudo ./tests/kms_frontbuffer_tracking --run-subtest '*fbc-*' 2>&1
> > | tee fbc.
69 matches
Mail list logo
