On Thu, Jul 28, 2016 at 05:36:14PM -0700, Manasi Navare wrote:
> On Thu, Jul 28, 2016 at 11:15:22PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 28, 2016 at 12:48:53PM -0700, Manasi Navare wrote:
> > > On Thu, Jul 28, 2016 at 05:50:43PM +0300, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From
On Fri, Jul 29, 2016 at 12:52:55PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 28, 2016 at 05:36:14PM -0700, Manasi Navare wrote:
> > On Thu, Jul 28, 2016 at 11:15:22PM +0300, Ville Syrjälä wrote:
> > > On Thu, Jul 28, 2016 at 12:48:53PM -0700, Manasi Navare wrote:
> > > > On Thu, Jul 28, 2016 at 05:
On Tue, Jul 26, 2016 at 12:39 PM, Ville Syrjälä
wrote:
> On Tue, Jul 26, 2016 at 05:24:42PM +0100, Chris Wilson wrote:
>> On Tue, Jul 26, 2016 at 07:06:56PM +0300, ville.syrj...@linux.intel.com
>> wrote:
>> > From: Ville Syrjälä
>> >
>> > Passing negative width/hight to scale factor calculations
On Fri, Jul 29, 2016 at 10:26:20PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 29, 2016 at 02:48:09PM -0400, Lyude wrote:
> > So I've been working on trying to fix this entirely again (e.g. writing
> > the ddb properly), since from bug reports it still doesn't sound like
> > we've got enough workarou
On Thu, Jul 28, 2016 at 05:50:43PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> DP link retraining needs to grab some modeset locks to not race with
> modesets, so we can't really do it safely from the hpd_pulse, lest we
> risk deadlocking due to MST sideband stuff.
>
>
On Fri, Jul 29, 2016 at 12:39:05PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 28, 2016 at 05:03:52PM -0700, Matt Roper wrote:
> > This is completely untested (and probably horribly broken/buggy), but
> > here's a quick mockup of the general approach I was thinking for
> > ensuring DDB & WM's can be
On Sun, 2016-06-05 at 16:42 -0500, Chris wrote:
> In an effort to try and figure out why the video on my Dell Optiplex 780
> keeps freezing I've been advised to run the latest kernel to see if it
> may fix the problem. Today I installed 4.6.0-997.20160502_amd64.deb
> and when booting it would n
On Fri, 2016-07-29 at 22:26 +0300, Ville Syrjälä wrote:
> On Fri, Jul 29, 2016 at 02:48:09PM -0400, Lyude wrote:
> >
> > So I've been working on trying to fix this entirely again (e.g.
> > writing
> > the ddb properly), since from bug reports it still doesn't sound
> > like
> > we've got enough wo
On Fri, Jul 29, 2016 at 08:50:05AM +0300, Joonas Lahtinen wrote:
> Only property creation uses the rotation as an index, so convert the
> to figure the index when needed.
>
> v2: Use the new defines to build the _MASK defines (Sean)
>
> Cc: intel-gfx@lists.freedesktop.org
> Cc: linux-arm-...@vger
On Fri, Jul 29, 2016 at 02:48:09PM -0400, Lyude wrote:
> So I've been working on trying to fix this entirely again (e.g. writing
> the ddb properly), since from bug reports it still doesn't sound like
> we've got enough workarounds to make this tolerable. I've shown this to
> matt roper, but I shou
On Fri, Jul 29, 2016 at 12:10:30PM +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 10:57:49AM +0200, Daniel Vetter wrote:
> > On Fri, Jul 29, 2016 at 11:42:24AM +0300, Joonas Lahtinen wrote:
> > > On pe, 2016-07-29 at 00:45 +0100, Chris Wilson wrote:
> > > > It appears that we never told Pinev
So I've been working on trying to fix this entirely again (e.g. writing
the ddb properly), since from bug reports it still doesn't sound like
we've got enough workarounds to make this tolerable. I've shown this to
matt roper, but I should probably post what I've been trying to do for
you as well.
On Fri, Jul 29, 2016 at 02:36:23PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 29, 2016 at 11:22:32AM +0200, Daniel Vetter wrote:
> > On Thu, Jul 28, 2016 at 05:50:41PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > s/active_mst_links/active_streams/ and use
On Thu, Jul 28, 2016 at 04:34:54PM +0300, Ander Conselvan de Oliveira wrote:
> From: "R, Durgadoss"
>
> Split out of bxt_ddi_pll_select() the logic that calculates the pll
> dividers and dpll_hw_state into a new function that doesn't depend on
> crtc state. This will be used for enabling the port
On Fri, Jul 29, 2016 at 05:57:02PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> According to Bspec FW_BLC_SELF exists on 915G also. Let's program it.
Indeed, it is there, and looks mostly the same as 915gm.
> The only open question is whether there's is a memory self-re
On Fri, Jul 29, 2016 at 05:57:01PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Bspec says:
> "FW_BLC_SELF
> ...
> Programming Note [DevALV] and [DevCST]: When calculating watermark
> values for 15/16bpp, assume 32bpp for purposes of calculation using
> the high prior
On Sun, 2016-06-05 at 16:42 -0500, Chris wrote:
> In an effort to try and figure out why the video on my Dell Optiplex 780
> keeps freezing I've been advised to run the latest kernel to see if it
> may fix the problem. Today I installed 4.6.0-997.20160502_amd64.deb
> and when booting it would n
On Fri, Jul 29, 2016 at 05:06:13PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 28, 2016 at 12:12:17PM -0700, Carlos Santa wrote:
> > Based on the GEN7_FEATURES changes from Ben W.
> >
> > Use it for snb.
> >
> > Signed-off-by: Carlos Santa
> > Reviewed-by: Rodrigo Vivi
> > ---
> > drivers/gpu/dr
On Fri, Jul 29, 2016 at 05:51:43AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add missing ring_mask to Pineview
> URL : https://patchwork.freedesktop.org/series/10368/
> State : failure
>
> == Summary ==
>
> Series 10368v1 drm/i915: Add missing ring_mask to Pineview
>
== Series Details ==
Series: series starting with [1/2] drm/i915: Always use cpp==4 for FW_BLC_SELF
on 915GM/945GM
URL : https://patchwork.freedesktop.org/series/10392/
State : failure
== Summary ==
Series 10392v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/103
== Series Details ==
Series: drm/i915: Move DP link retraining to hotplug work etc. (rev3)
URL : https://patchwork.freedesktop.org/series/10354/
State : failure
== Summary ==
Series 10354v3 drm/i915: Move DP link retraining to hotplug work etc.
http://patchwork.freedesktop.org/api/1.0/series/1
From: Ville Syrjälä
According to Bspec FW_BLC_SELF exists on 915G also. Let's program it.
The only open question is whether there's is a memory self-refresh
enable bit somewhere as well. For 945G/GM it's in FW_BLC_SELF, for
915GM it's in INSTPM. For 915G I can't find one in the docs. Let's drop
a
From: Ville Syrjälä
Bspec says:
"FW_BLC_SELF
...
Programming Note [DevALV] and [DevCST]: When calculating watermark
values for 15/16bpp, assume 32bpp for purposes of calculation using
the high priority bandwidth analysis spreadsheet."
Let's do that.
Perhaps this might even help with the pro
On Thu, Jul 28, 2016 at 12:12:32PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Signed-off-b
On Thu, Jul 28, 2016 at 12:12:18PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Signe
On Thu, Jul 28, 2016 at 12:12:31PM -0700, Carlos Santa wrote:
> Based on the GEN7_FEATURES changes from Ben W.
>
> Use it for 830, 845g, i85x, i865g.
>
> Signed-off-by: Carlos Santa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 33 ++---
> 1 file changed, 14 insertions(+
On Thu, Jul 28, 2016 at 12:12:27PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Signe
On Thu, Jul 28, 2016 at 12:12:19PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Signe
On Thu, Jul 28, 2016 at 12:12:17PM -0700, Carlos Santa wrote:
> Based on the GEN7_FEATURES changes from Ben W.
>
> Use it for snb.
>
> Signed-off-by: Carlos Santa
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_pci.c | 26 --
> 1 file changed, 12 insertion
On Thu, Jul 28, 2016 at 12:12:16PM -0700, Carlos Santa wrote:
> [patch series] Moving all GPU features to the platform struct definition
> allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct definition
>
>
On Thu, Jul 28, 2016 at 12:12:15PM -0700, Carlos Santa wrote:
> This patchset includes the following changes:
>
> - organize most GPU features so that they are easy to group by platforms.
>It seems some of the ground work was already done for Gen7 features.
>Reuse some of that work for th
From: Ville Syrjälä
Currently we re-read a bunch of static eDP panel caps from the DPCD
over and over again. Let's do it only once to save some time and effort.
v2: Make thing less confusing with intel_edp_init_dpcd() (Chris)
Move no_aux_handshake setup in there as well
v3: Move tps3/rate pr
From: Ville Syrjälä
With HSW + Dell UP2414Q (at least) drm_probe_ddc() occasionally fails,
and then we'll assume that the entire display has been disconnected.
We don't need the EDID from the main link, so we can simply check if
the sink is MST capable, and if so treat is as connected.
v2: Skip
On 29/07/16 12:33, Dave Gordon wrote:
On 06/07/16 15:24, Peter Antoine wrote:
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-i
On 06/07/16 15:24, Peter Antoine wrote:
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if
On Fri, Jul 29, 2016 at 11:35:27AM +0200, Daniel Vetter wrote:
> On Thu, Jul 28, 2016 at 05:50:46PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Let's make rate_to_index() return the highest rate available that's
> > less than or equal to the rate requested by the c
On Fri, Jul 29, 2016 at 11:29:56AM +0200, Daniel Vetter wrote:
> On Thu, Jul 28, 2016 at 05:50:42PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > With HSW + Dell UP2414Q (at least) drm_probe_ddc() occasionally fails,
> > and then we'll assume that the entire display
On Fri, Jul 29, 2016 at 11:22:32AM +0200, Daniel Vetter wrote:
> On Thu, Jul 28, 2016 at 05:50:41PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > s/active_mst_links/active_streams/ and use it also for SST. We can then
> > use this information in the hpd handling to s
On 06/07/16 15:24, Peter Antoine wrote:
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
Signed-off-by: Alex Dai
On 06/07/16 15:24, Peter Antoine wrote:
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if
On Fri, Jul 29, 2016 at 11:19:18AM +0200, Daniel Vetter wrote:
> On Thu, Jul 28, 2016 at 05:50:40PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We can't mix MST with SST/HDMI on the same physical port, so we'll need
> > to reject such configurations in check_digita
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/guc: Make the GuC fw loading
helper functions general (rev2)
URL : https://patchwork.freedesktop.org/series/9564/
State : failure
== Summary ==
Applying: drm/i915/guc: Make the GuC fw loading helper functions general
fatal: s
On 06/07/16 15:24, Peter Antoine wrote:
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such a
On Fri, Jul 29, 2016 at 10:57:49AM +0200, Daniel Vetter wrote:
> On Fri, Jul 29, 2016 at 11:42:24AM +0300, Joonas Lahtinen wrote:
> > On pe, 2016-07-29 at 00:45 +0100, Chris Wilson wrote:
> > > It appears that we never told Pineview it has a RENDER_RING. This was
> > > all fine until we started usi
On Fri, Jul 29, 2016 at 01:28:19PM +0300, Joonas Lahtinen wrote:
> On pe, 2016-07-29 at 11:19 +0100, Chris Wilson wrote:
> > As we always allocate in chunks of 4096 (that being both the PAGE_SIZE
> > and our own GTT_PAGE_SIZE), we know that all results from the drm_mm are
>
> That GTT_PAGE_SIZE de
On pe, 2016-07-29 at 11:19 +0100, Chris Wilson wrote:
> As we always allocate in chunks of 4096 (that being both the PAGE_SIZE
> and our own GTT_PAGE_SIZE), we know that all results from the drm_mm are
That GTT_PAGE_SIZE define would be sweet to introduce finally :P
Reviewed-by: Joonas Lahtinen
== Series Details ==
Series: series starting with [01/22] drm/i915: Combine loops within
i915_gem_evict_something (rev2)
URL : https://patchwork.freedesktop.org/series/10315/
State : failure
== Summary ==
Applying: drm/i915: Combine loops within i915_gem_evict_something
Using index info to re
As we always allocate in chunks of 4096 (that being both the PAGE_SIZE
and our own GTT_PAGE_SIZE), we know that all results from the drm_mm are
aligned to at least 4096. The drm_mm allocator itself is optimised for
alignment == 0, and so by converting alignments of 4096 to 0 we can
satisfy our own
On Fri, Jul 29, 2016 at 11:16:19AM +0200, Daniel Vetter wrote:
> On Thu, Jul 28, 2016 at 05:50:39PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The MST vs. SST selection should depend purely on the choice of the
> > connector/encoder. So don't try to determine the
On Thu, Jul 28, 2016 at 05:36:14PM -0700, Manasi Navare wrote:
> On Thu, Jul 28, 2016 at 11:15:22PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 28, 2016 at 12:48:53PM -0700, Manasi Navare wrote:
> > > On Thu, Jul 28, 2016 at 05:50:43PM +0300, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From
Please Ignore this patch.
Finger trouble.
Peter.
-Original Message-
From: Antoine, Peter
Sent: Friday, July 29, 2016 10:35 AM
To: intel-gfx@lists.freedesktop.org
Cc: ch...@chris-wilson.co.uk; Antoine, Peter
Subject: [I-G-T 2/3] igt/gem_mocs_settings: adding RC6 testings
This change add
On Fri, Jul 29, 2016 at 05:54:23AM +, Yang, Libin wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Thursday, July 28, 2016 3:42 PM
> > To: libin.y...@linux.intel.com
> > Cc: intel-gfx@lists.freedesktop.org; jani.nik...
On Fri, Jul 29, 2016 at 10:43:17AM +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 09:49:54AM +0100, Chris Wilson wrote:
> > On Fri, Jul 29, 2016 at 10:41:14AM +0200, Daniel Vetter wrote:
> > > I guess it doesn't hurt to make this really, really clear. Perfect! Well
> > > almost, one nit:
> >
On Fri, Jul 29, 2016 at 09:49:54AM +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 10:41:14AM +0200, Daniel Vetter wrote:
> > I guess it doesn't hurt to make this really, really clear. Perfect! Well
> > almost, one nit:
> >
> > >
> > > /* What stops the following rcu_derefere
On Thu, Jul 28, 2016 at 05:50:48PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We cache a bunch of state under the encoders (eg. link freq and
> lane count for DP). We need to refresh that cached state on
> init/resume during hardware readout. Since we have already read
On Thu, Jul 28, 2016 at 05:03:52PM -0700, Matt Roper wrote:
> This is completely untested (and probably horribly broken/buggy), but
> here's a quick mockup of the general approach I was thinking for
> ensuring DDB & WM's can be updated together while ensuring the
> three-step pipe flushing process
On Thu, Jul 28, 2016 at 05:50:47PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> My ASUS PB278 at least doesn't seem to appreciate when you try to
> ack sink irqs when there are none. Results in thus sort of dmesg spam
> [drm:drm_dp_dpcd_access] too many retries, giving up
On Thu, Jul 28, 2016 at 05:50:46PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Let's make rate_to_index() return the highest rate available that's
> less than or equal to the rate requested by the caller. The function
> can then be used to filter out rates higher than a
On pe, 2016-07-29 at 09:10 +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 09:04:48AM +0100, Chris Wilson wrote:
> >
> > On Fri, Jul 29, 2016 at 10:40:09AM +0300, Joonas Lahtinen wrote:
> > >
> > > _is_active() does not really fit to be assigned to _mask. maybe have
> > > object_active_mask(
These changes fix several problems with the MOCS tests.
The RC6 save/restore is not the same on all platforms and does not save restore
the same registers on all platforms. The testing relied on the fact that it
always restored all the MOCS registers. This patchset removes that assumption.
Also as
This change adds a RC6 test for the MOCS. The MOCS registers are loaded
and saved as part of the RC6 cycle but not all the registers are
saved/restored. This tests that those registers are correctly restored.
Signed-off-by: Peter Antoine
---
tests/gem_mocs_settings.c | 56 +++
On some platforms the MOCS values are not always saved and restored
on RC6 enter/exit. The rational is that the context with restore
these values. On these platforms the test will fail as it tests the
values by directly reading the MOCS registers.
So this change removes the direct testing of the v
This change adds a RC6 test for the MOCS. The MOCS registers are loaded
and saved as part of the RC6 cycle but not all the registers are
saved/restored. This tests that those registers are correctly restored.
Signed-off-by: Peter Antoine
---
tests/gem_mocs_settings.c | 56 +++
If one of the previous tests fails then the following tests fail.
This patch means that the following tests do not fail when the previous
test fails (for some cases).
Signed-off-by: Peter Antoine
---
lib/igt_aux.c | 67 +++
lib/igt_aux.h
On Thu, Jul 28, 2016 at 05:50:45PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> No need to iterate the rates array in intel_dp_max_link_rate(). We know
> the max rate will be the last entry, and we already know the size.
>
> Cc: Ander Conselvan de Oliveira
> Cc: Jim Bri
On Thu, Jul 28, 2016 at 05:50:42PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> With HSW + Dell UP2414Q (at least) drm_probe_ddc() occasionally fails,
> and then we'll assume that the entire display has been disconnected.
> We don't need the EDID from the main link, so we
On Thu, Jul 28, 2016 at 05:50:41PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> s/active_mst_links/active_streams/ and use it also for SST. We can then
> use this information in the hpd handling to see if the link is active
> or not, and thus whether we may need to retrai
On Thu, Jul 28, 2016 at 05:50:40PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We can't mix MST with SST/HDMI on the same physical port, so we'll need
> to reject such configurations in check_digital_port_conflicts(). Nothing
> else will prevent this as MST has its fake
On Thu, Jul 28, 2016 at 05:50:39PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The MST vs. SST selection should depend purely on the choice of the
> connector/encoder. So don't try to determine the correct DDI mode
> based on the intel_dp->is_mst, which simply tells us w
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Don't pass crtc_state to
intel_dp_set_link_params()
URL : https://patchwork.freedesktop.org/series/10349/
State : failure
== Summary ==
Series 10349v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/seri
On to, 2016-07-28 at 17:12 +0100, Chris Wilson wrote:
> Do you want i915_gem_obj_lookup_or_create_ggtt_vma() to inherit the
> BUG_ON(!view) removed from i915_gem_object_ggtt_pin() by this patch?
Yes, as intermediary step.
Regards, Joonas
> -Chris
>
--
Joonas Lahtinen
Open Source Technology Cen
On Fri, Jul 29, 2016 at 11:42:24AM +0300, Joonas Lahtinen wrote:
> On pe, 2016-07-29 at 00:45 +0100, Chris Wilson wrote:
> > It appears that we never told Pineview it has a RENDER_RING. This was
> > all fine until we started using the ring_mask for determining all the
> > available rings to initial
On pe, 2016-07-29 at 09:08 +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 10:59:26AM +0300, Joonas Lahtinen wrote:
> >
> > On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> > >
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -727,11 +727,15 @@
On Fri, Jul 29, 2016 at 10:41:14AM +0200, Daniel Vetter wrote:
> On Thu, Jul 28, 2016 at 09:49:58PM +0100, Chris Wilson wrote:
> > On Thu, Jul 28, 2016 at 12:23:40PM +0200, Daniel Vetter wrote:
> > > I think we have a race here still: The issue is that the
> > > kref_get_unless_zero is an unordered
On pe, 2016-07-29 at 00:45 +0100, Chris Wilson wrote:
> It appears that we never told Pineview it has a RENDER_RING. This was
> all fine until we started using the ring_mask for determining all the
> available rings to initialise for legacy ringbuffer submission in commit
> 88d2ba2e95c8 ("drm/i915:
On Thu, Jul 28, 2016 at 09:49:58PM +0100, Chris Wilson wrote:
> On Thu, Jul 28, 2016 at 12:23:40PM +0200, Daniel Vetter wrote:
> > I think we have a race here still: The issue is that the
> > kref_get_unless_zero is an unordered atomic, and the rcu_dereference is
> > only an smb_read_barrier_depend
On Thu, Jul 28, 2016 at 12:02:01PM +0200, Daniel Vetter wrote:
> On Wed, Jul 27, 2016 at 12:14:54PM +0100, Chris Wilson wrote:
> > We only need a very lightweight mechanism here as the locking is only
> > used for co-ordinating a bitfield.
> >
> > v2: Move the cheap unlikely tests into the caller
On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> + if (i915_vma_misplaced(vma, size, alignment, flags)) {
> + if (flags & PIN_NONBLOCK &&
> + (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
> + return -ENOSPC;
Why ENOSPC when active
On Fri, Jul 29, 2016 at 09:04:48AM +0100, Chris Wilson wrote:
> On Fri, Jul 29, 2016 at 10:40:09AM +0300, Joonas Lahtinen wrote:
> > _is_active() does not really fit to be assigned to _mask. maybe have
> > object_active_mask() and then
> >
> > _is_idle/inactive/whatever() { return !object_active_m
On Fri, Jul 29, 2016 at 10:59:26AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -727,11 +727,15 @@ struct drm_i915_gem_exec_object2 {
> > #define EXEC_OBJECT_WRITE
On Fri, Jul 29, 2016 at 10:40:09AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> > +static inline void
> > +i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
> > +{
> > + obj->flags |= 1 << (engine + I915_BO_ACTIVE_SHIFT);
>
> BIT(e
On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -727,11 +727,15 @@ struct drm_i915_gem_exec_object2 {
> #define EXEC_OBJECT_WRITE (1<<2)
> #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
> #define EXEC
On Fri, Jul 29, 2016 at 10:30:26AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> > @@ -2979,7 +2980,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
> > alignment, u64 flags)
> > u64 min_alignment;
> > int ret;
> >
> > - GEM_BUG_ON(vma-
On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> +static inline void
> +i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
> +{
> + obj->flags |= 1 << (engine + I915_BO_ACTIVE_SHIFT);
BIT(engine) << I915_BO_ACTIVE_SHIFT would be more readable to my taste,
but I gues
On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> @@ -2979,7 +2980,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
> alignment, u64 flags)
> u64 min_alignment;
> int ret;
>
> - GEM_BUG_ON(vma->bound);
> + GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA
On Fri, Jul 29, 2016 at 09:59:31AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> > @@ -3810,10 +3810,11 @@ i915_gem_object_ggtt_unpin_view(struct
> > drm_i915_gem_object *obj,
> > {
> > struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
> >
On Fri, Jul 29, 2016 at 09:53:11AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-27 at 12:14 +0100, Chris Wilson wrote:
> > -uint32_t
> > -i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int
> > tiling_mode);
> > -uint32_t
> > -i915_gem_get_gtt_alignment(struct drm_device *dev, uint3
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