Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

On Thu, Oct 13, 2016 at 08:45:45AM -0700, Jeff McGee wrote: > On Mon, Oct 03, 2016 at 11:42:56AM -0700, Anusha Srivatsa wrote: > > From: Peter Antoine > > > > HuC firmware css header has almost exactly same definition as GuC > > firmware except for the sw_version. Also,

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

Tested-by: Libin Yang Regards, Libin > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Dhinakaran Pandiyan > Sent: Friday, October 14, 2016 2:04 AM > To: intel-...@freedesktop.org > Cc: Nikula, Jani

Re: [Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > This patch will allow for getparams to return the status of the HuC. > As the HuC has to be validated by the GuC this patch uses the validated > status to show when the HuC is

Re: [Intel-gfx] [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams

On Fri, Oct 07, 2016 at 09:11:03AM +0200, Daniel Vetter wrote: > On Wed, Oct 05, 2016 at 01:51:14PM -0700, Rodrigo Vivi wrote: > > > > > > Reviewed-by: Rodrigo Vivi > > This is new uabi. Where's the userspace? > > Checking this is part of the review. > -Daniel > I'm

Re: [Intel-gfx] [PATCH 6/8] drm/i915/huc: Add BXT HuC Loading Support

On Mon, Oct 03, 2016 at 11:43:00AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > This patch adds the HuC Loading for the BXT. > Version 1.7 of the HuC firmware. > > v2: rebased. > v3: rebased. > changed file name to match the install package format. > v7:

Re: [Intel-gfx] [PATCH 5/8] drm/i915/huc: Support HuC authentication

On Mon, Oct 03, 2016 at 11:42:59AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > The HuC authentication is done by host2guc call. The HuC RSA keys > are sent to GuC for authentication. > > v2: rebased on top of drm-intel-nightly. > changed name format and

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/gen9: Get rid of redundant watermark values

Your is SAGV related, and when we don't make the SAGV happy people's machines usually hang. So I'm definitely for your patches getting merged first On Thu, 2016-10-13 at 17:07 -0300, Paulo Zanoni wrote: > Em Qui, 2016-10-13 às 17:04 -0300, Paulo Zanoni escreveu: > > > > Em Qui, 2016-10-13 às

Re: [Intel-gfx] [PATCH 09/10] drm/i915/gen9: Actually verify WM levels in verify_wm_state()

Em Qui, 2016-10-13 às 18:15 -0300, Paulo Zanoni escreveu: > Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > > > > Thanks to Paulo Zanoni for indirectly pointing this out. > > > > Looks like we never actually added any code for checking whether or > > not > > we actually wrote watermark

Re: [Intel-gfx] [PATCH 10/10] drm/i915/gen9: Don't wrap strings in verify_wm_state()

Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: Bikesheding: it would be nice to write a commit message explaining why, even if the message just tells the user to read Documentation/CodingStyle. Reviewed-by: Paulo Zanoni > Signed-off-by: Lyude >

Re: [Intel-gfx] [PATCH 09/10] drm/i915/gen9: Actually verify WM levels in verify_wm_state()

Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > Thanks to Paulo Zanoni for indirectly pointing this out. > > Looks like we never actually added any code for checking whether or > not > we actually wrote watermark levels properly. Let's fix that. Thanks for doing this! Reviewed-by: Paulo

Re: [Intel-gfx] Problem with emgd on fedora 18

On Thu, Oct 13, 2016 at 03:28:05PM +0300, Jani Nikula wrote: > On Thu, 13 Oct 2016, Anteja Vuk Macek wrote: > > Hi, > > I work with Fedora 18 and I'm new in linux world. I have problem with emgd > > driver. I put emgd driver in kernel and build kernel. Moduled is build

Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

On Thu, Oct 13, 2016 at 10:42:42AM -0700, Jeff McGee wrote: > On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote: > > From: Peter Antoine > > > > The HuC loading process is similar to GuC. The intel_uc_fw_fetch() > > is used for both cases. > > > > HuC

Re: [Intel-gfx] [PATCH 08/10] drm/i915/gen9: Add skl_wm_level_equals()

Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > Helper we're going to be using for implementing verification of the > wm > levels in skl_verify_wm_level(). > > Signed-off-by: Lyude Reviewed-by: Paulo Zanoni > Cc: Maarten Lankhorst

Re: [Intel-gfx] [PATCH 07/10] drm/i915/gen9: Make skl_pipe_wm_get_hw_state() reusable

Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > There's not much of a reason this should have the locations to read > out > the hardware state hardcoded, so allow the caller to specify the > location and add this function to intel_drv.h. As well, we're going > to > need this function to be

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/edid: Only print the bad edid when aborting

== Series Details == Series: drm/edid: Only print the bad edid when aborting URL : https://patchwork.freedesktop.org/series/13747/ State : warning == Summary == Series 13747v1 drm/edid: Only print the bad edid when aborting

Re: [Intel-gfx] [PATCH v2 06/10] drm/i915/gen9: Add ddb changes to atomic debug output

Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > Finally, add some debugging output for ddb changes in the atomic > debug > output. This makes it a lot easier to spot bugs from incorrect ddb > allocations. > > Signed-off-by: Lyude > Reviewed-by: Maarten Lankhorst

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/gen9: Get rid of redundant watermark values

Em Qui, 2016-10-13 às 17:04 -0300, Paulo Zanoni escreveu: > Em Qui, 2016-10-13 às 15:39 +0200, Maarten Lankhorst escreveu: > > > > Op 08-10-16 om 02:11 schreef Lyude: > > > > > > > > > Now that we've make skl_wm_levels make a little more sense, we > > > can > > > remove all of the redundant wm

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/gen9: Get rid of redundant watermark values

Em Qui, 2016-10-13 às 15:39 +0200, Maarten Lankhorst escreveu: > Op 08-10-16 om 02:11 schreef Lyude: > > > > Now that we've make skl_wm_levels make a little more sense, we can > > remove all of the redundant wm information. Up until now we'd been > > storing two copies of all of the skl

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev3)

On Thu, Oct 13, 2016 at 06:47:24PM +, Saarinen, Jani wrote: > > > == Series Details == > > > > > > Series: drm/i915: Allocate intel_engine_cs structure only for the enabled > > engines (rev3) > > > URL : https://patchwork.freedesktop.org/series/13435/ > > > State : warning > > > > > > ==

[Intel-gfx] [PATCH] drm/edid: Only print the bad edid when aborting

Currently, if drm.debug is enabled, we get a DRM_ERROR message on the intermediate edid reads. This causes transient failures in CI which flags up the sporadic EDID read failures, which are recovered by rereading the EDID automatically. This patch combines the reporting done by drm_do_get_edid()

Re: [Intel-gfx] [RFC PATCH v2 4/8] drm/i915: Add support for enabling/disabling hdmi audio interrupts

+/* Added for HDMI Audio */ +int i915_enable_hdmi_audio_int(struct drm_i915_private *dev_priv) +{ + unsigned long irqflags; + u32 imr, int_bit; + int pipe = -1; + + spin_lock_irqsave(_priv->irq_lock, irqflags); + + imr = I915_READ(VLV_IMR); + + if

Re: [Intel-gfx] [RFC PATCH v2 1/8] drm/i915: setup bridge for HDMI LPE audio driver

Thanks Ville for the review. A lot of the comments are related to the initial VED code we took pretty much as is, no issues to clean-up further. BTW, it looks like Jerome's patches were stuck for 10+ days on the intel-gfx server for some reason so not everyone saw the initial post? @@

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

== Series Details == Series: drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2 URL : https://patchwork.freedesktop.org/series/13745/ State : success == Summary == Series 13745v1 drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev3)

> > == Series Details == > > > > Series: drm/i915: Allocate intel_engine_cs structure only for the enabled > engines (rev3) > > URL : https://patchwork.freedesktop.org/series/13435/ > > State : warning > > > > == Summary == > > > > Series 13435v3 drm/i915: Allocate intel_engine_cs structure only

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Respect alternate_ddc_pin for all DDI ports

On Thu, Oct 13, 2016 at 11:06:55AM -0700, Jim Bride wrote: > On Tue, Oct 11, 2016 at 08:52:46PM +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > The VBT provides the platform a way to mix and match the DDI ports vs. > > GMBUS pins.

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

Em Qui, 2016-10-13 às 11:04 -0700, Dhinakaran Pandiyan escreveu: > According to BSpec, cdclk has to be not less than 432 MHz with DP > audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) This is just for pre-production hardware, and we don't implement workarounds for pre-prod. A quick

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Fix whitespace issues

On Tue, Oct 11, 2016 at 08:52:48PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Fix the poorly indented port parameters to the aux ctl and data > reg functions. This was fallout from the s/i915_mmio_reg_t/i915_reg_t/ > that happened during

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Clean up DDI DDC/AUX CH sanitation

On Tue, Oct 11, 2016 at 08:52:47PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Now that we use the AUX and GMBUS assignment from VBT for all ports, > let's clean up the sanitization of the port information a bit. > Previosuly we only did

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Respect alternate_ddc_pin for all DDI ports

On Tue, Oct 11, 2016 at 08:52:46PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The VBT provides the platform a way to mix and match the DDI ports vs. > GMBUS pins. Currently we only trust the VBT for DDI E, which I suppose > has no

Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

[Adding Matt] On Wed, 2016-10-12 at 14:08 +0300, Joonas Lahtinen wrote: > Bisecting the offending commit between v4.8 and v4.8.1 would be a good > start. 0) Why use a personal notebook when one can just post any half baked idea to lkml? 1) I stumbled on 

[Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

According to BSpec, cdclk has to be not less than 432 MHz with DP audio enabled, port width x4, and link rate HBR2 (5.4 GHz) Having a lower cdclk triggers pipe underruns, which then lead to displays continuously cycling off and on. This is essential for DP MST audio as the link is trained at HBR2

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Respect alternate_aux_channel for all DDI ports

On Tue, Oct 11, 2016 at 08:52:45PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The VBT provides the platform a way to mix and match the DDI ports vs. > AUX channels. Currently we only trust the VBT for DDI E, which has no > corresponding

Re: [Intel-gfx] [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check

Reviewed-by: Jeff McGee On Mon, Oct 03, 2016 at 11:42:58AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > Add debugfs entry for HuC loading status check. > > v2: rebase on-top of drm-intel-nightly. > v3: rebased again. > v7: rebased. >

Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > The HuC loading process is similar to GuC. The intel_uc_fw_fetch() > is used for both cases. > > HuC loading needs to be before GuC loading. The WOPCM setting must > be done early

Re: [Intel-gfx] [PATCH] drm: Print device information again in debugfs

On 13 October 2016 at 15:13, Daniel Vetter wrote: > I was a bit over-eager in my cleanup in > > commit 95c081c17f284de50eaca60d4d55643a64d39019 > Author: Daniel Vetter > Date: Tue Jun 21 10:54:12 2016 +0200 > > drm: Move master pointer from

Re: [Intel-gfx] [PATCH v2 4/4] drm: Add and handle new aspect ratios in DRM layer

On Tue, Aug 09, 2016 at 08:25:50PM +0530, Shashank Sharma wrote: > HDMI 2.0/CEA-861-F introduces two new aspect ratios: > - 64:27 > - 256:135 > > This patch: > - Adds new DRM flags for to represent these new aspect ratios. > - Adds new cases to handle these aspect ratios while converting > from

Re: [Intel-gfx] [PATCH v2 2/4] drm: Add aspect ratio parsing in DRM layer

On Tue, Aug 09, 2016 at 08:25:48PM +0530, Shashank Sharma wrote: > Current DRM layer functions don't parse aspect ratio information > while converting a user mode->kernel mode or vice versa. This > causes modeset to pick mode with wrong aspect ratio, eventually > causing failures in HDMI

Re: [Intel-gfx] [PATCH v2 1/4] drm: add picture aspect ratio flags

On Tue, Aug 09, 2016 at 08:25:47PM +0530, Shashank Sharma wrote: > This patch adds drm flag bits for aspect ratio information > > Currently drm flag bits don't have field for mode's picture > aspect ratio. This field will help the driver to pick mode with > right aspect ratio, and help in setting

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev4)

== Series Details == Series: drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev4) URL : https://patchwork.freedesktop.org/series/13435/ State : warning == Summary == Series 13435v4 drm/i915: Allocate intel_engine_cs structure only for the enabled engines

Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatched INIT power domain disabling during suspend

On to, 2016-10-13 at 15:21 +0300, Jani Nikula wrote: > On Thu, 13 Oct 2016, Imre Deak wrote: > > Currently the display INIT power domain disabling/enabling happens in a > > mismatched way in the suspend/resume_early hooks respectively. This can > > leave display power wells

[Intel-gfx] [PATCH v11] drm/i915: Allocate intel_engine_cs structure only for the enabled engines

From: Akash Goel With the possibility of addition of many more number of rings in future, the drm_i915_private structure could bloat as an array, of type intel_engine_cs, is embedded inside it. struct intel_engine_cs engine[I915_NUM_ENGINES]; Though this is still

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm: Print device information again in debugfs

== Series Details == Series: drm: Print device information again in debugfs URL : https://patchwork.freedesktop.org/series/13731/ State : warning == Summary == Series 13731v1 drm: Print device information again in debugfs

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev3)

On 13/10/2016 17:10, Goel, Akash wrote: On 10/10/2016 6:03 PM, Patchwork wrote: == Series Details == Series: drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev3) URL : https://patchwork.freedesktop.org/series/13435/ State : warning == Summary == Series

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev3)

On 10/10/2016 6:03 PM, Patchwork wrote: == Series Details == Series: drm/i915: Allocate intel_engine_cs structure only for the enabled engines (rev3) URL : https://patchwork.freedesktop.org/series/13435/ State : warning == Summary == Series 13435v3 drm/i915: Allocate intel_engine_cs

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Save megabytes of wasted sg entries

On 13/10/2016 16:33, Daniel Vetter wrote: On Thu, Oct 13, 2016 at 11:24:46AM +, Saarinen, Jani wrote: == Series Details == Series: Save megabytes of wasted sg entries URL : https://patchwork.freedesktop.org/series/13706/ State : failure == Summary == Series 13706v1 Save megabytes of

Re: [Intel-gfx] [PATCH v4 8/8] drm/i915/bxt: Enable IPC support

On Thu, Oct 13, 2016 at 06:31:37PM +0530, Mahesh Kumar wrote: > Hi, > > > On Thursday 13 October 2016 04:49 PM, Maarten Lankhorst wrote: > > Op 13-10-16 om 12:58 schreef Kumar, Mahesh: > > > From: Mahesh Kumar > > > > > > This patch adds IPC support for platforms. This

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use fence_write() from rpm resume

On Thu, Oct 13, 2016 at 05:28:13PM +0200, Daniel Vetter wrote: > On Thu, Oct 13, 2016 at 04:25:18PM +0100, Chris Wilson wrote: > > On Thu, Oct 13, 2016 at 05:10:21PM +0200, Daniel Vetter wrote: > > > On Wed, Oct 12, 2016 at 12:16:33PM +0100, Chris Wilson wrote: > > > > @@ -379,10 +389,17 @@ void

Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

On Mon, Oct 03, 2016 at 11:42:56AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > HuC firmware css header has almost exactly same definition as GuC > firmware except for the sw_version. Also, add a new member fw_type > into intel_uc_fw to indicate what kind of

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Save megabytes of wasted sg entries

On Thu, Oct 13, 2016 at 11:24:46AM +, Saarinen, Jani wrote: > > == Series Details == > > > > Series: Save megabytes of wasted sg entries > > URL : https://patchwork.freedesktop.org/series/13706/ > > State : failure > > > > == Summary == > > > > Series 13706v1 Save megabytes of wasted sg

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use fence_write() from rpm resume

On Thu, Oct 13, 2016 at 05:10:21PM +0200, Daniel Vetter wrote: > On Wed, Oct 12, 2016 at 12:16:33PM +0100, Chris Wilson wrote: > > @@ -379,10 +389,17 @@ void i915_gem_restore_fences(struct drm_device *dev) > > * Commit delayed tiling changes if we have an object still > >

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use RPM as the barrier for controlling user mmap access

On Thu, Oct 13, 2016 at 04:15:23PM +0100, Chris Wilson wrote: > On Thu, Oct 13, 2016 at 04:44:23PM +0200, Daniel Vetter wrote: > > On Tue, Oct 11, 2016 at 03:37:58PM +0100, Chris Wilson wrote: > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > > b/drivers/gpu/drm/i915/i915_gem.c > > > index

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use fence_write() from rpm resume

On Thu, Oct 13, 2016 at 04:25:18PM +0100, Chris Wilson wrote: > On Thu, Oct 13, 2016 at 05:10:21PM +0200, Daniel Vetter wrote: > > On Wed, Oct 12, 2016 at 12:16:33PM +0100, Chris Wilson wrote: > > > @@ -379,10 +389,17 @@ void i915_gem_restore_fences(struct drm_device *dev) > > >*

Re: [Intel-gfx] [CI 4/6] drm/i915: Always use the GTT for error capture

On Thu, Oct 13, 2016 at 05:02:50PM +0200, Daniel Vetter wrote: > On Wed, Oct 12, 2016 at 10:05:20AM +0100, Chris Wilson wrote: > > Since the GTT provides universal access to any GPU page, we can use it > > to reduce our plethora of read methods to just one. It also has the > > important

Re: [Intel-gfx] [RFC i-g-t PATCH 2/3] igt/gem_wait: Use new igt_dummyload api

On Thu, Oct 13, 2016 at 10:49:39AM +0100, Chris Wilson wrote: > On Thu, Oct 13, 2016 at 12:31:13PM +0300, Abdiel Janulgue wrote: > > > > > > On 10/12/2016 03:07 PM, Chris Wilson wrote: > > > On Wed, Oct 12, 2016 at 02:59:53PM +0300, Abdiel Janulgue wrote: > > >> Signed-off-by: Abdiel Janulgue

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use RPM as the barrier for controlling user mmap access

On Thu, Oct 13, 2016 at 04:44:23PM +0200, Daniel Vetter wrote: > On Tue, Oct 11, 2016 at 03:37:58PM +0100, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > b/drivers/gpu/drm/i915/i915_gem.c > > index 91910ffe0964..587a91af5a3f 100644 > > ---

Re: [Intel-gfx] [PATCH] drm/i915: Assert we hold the CRTC powerwell for generating vblank interrupts

On Thu, Oct 13, 2016 at 04:17:07PM +0200, Daniel Vetter wrote: > On Wed, Oct 12, 2016 at 07:21:44AM +0200, Maarten Lankhorst wrote: > > I don't see a nice way to do this, it probably means we shouldn't do this > > at all.. > > Maybe have a function look at > >

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use fence_write() from rpm resume

On Wed, Oct 12, 2016 at 12:16:33PM +0100, Chris Wilson wrote: > During rpm resume we restore the fences, but we do not have the > protection of struct_mutex. This rules out updating the activity > tracking on the fences, and requires us to rely on the rpm as the > serialisation barrier instead. >

Re: [Intel-gfx] [CI 3/6] drm/i915: Stop the machine whilst capturing the GPU crash dump

On Thu, Oct 13, 2016 at 04:57:39PM +0200, Daniel Vetter wrote: > On Wed, Oct 12, 2016 at 10:05:19AM +0100, Chris Wilson wrote: > > The error state is purposefully racy as we expect it to be called at any > > time and so have avoided any locking whilst capturing the crash dump. > > However, with

Re: [Intel-gfx] [CI 4/6] drm/i915: Always use the GTT for error capture

On Wed, Oct 12, 2016 at 10:05:20AM +0100, Chris Wilson wrote: > Since the GTT provides universal access to any GPU page, we can use it > to reduce our plethora of read methods to just one. It also has the > important characteristic of being exactly what the GPU sees - if there > are incoherency

Re: [Intel-gfx] [PATCH] drm: Print device information again in debugfs

On Thu, Oct 13, 2016 at 04:13:44PM +0200, Daniel Vetter wrote: > I was a bit over-eager in my cleanup in > > commit 95c081c17f284de50eaca60d4d55643a64d39019 > Author: Daniel Vetter > Date: Tue Jun 21 10:54:12 2016 +0200 > > drm: Move master pointer from drm_minor

Re: [Intel-gfx] [PATCH] drm/i915: Skip unbinding large unmappable global buffers

On Thu, Oct 13, 2016 at 03:13:51PM +0100, Tvrtko Ursulin wrote: > > On 13/10/2016 13:59, Chris Wilson wrote: > >On Thu, Oct 13, 2016 at 12:29:44PM +0100, Tvrtko Ursulin wrote: > >>On 13/10/2016 09:55, Chris Wilson wrote: > >>>If the user requests a mappable binding to the global GTT, we will

Re: [Intel-gfx] [CI 3/6] drm/i915: Stop the machine whilst capturing the GPU crash dump

On Wed, Oct 12, 2016 at 10:05:19AM +0100, Chris Wilson wrote: > The error state is purposefully racy as we expect it to be called at any > time and so have avoided any locking whilst capturing the crash dump. > However, with multi-engine GPUs and multiple CPUs, those races can > manifest into

Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

Reviewed-by: Jeff McGee On Mon, Oct 03, 2016 at 11:42:55AM -0700, Anusha Srivatsa wrote: > From: Peter Antoine > > Rename some of the GuC fw loading code to make them more general. We > will utilise them for HuC loading as well. >

Re: [Intel-gfx] [maintainer-tools PATCH 6/6] dim: add command to check for dim updates

On Tue, Oct 11, 2016 at 04:07:30PM +0300, Jani Nikula wrote: > On Tue, 11 Oct 2016, Daniel Vetter wrote: > > On Tue, Oct 11, 2016 at 11:47:32AM +0300, Jani Nikula wrote: > >> Add a command to check if the user is running an up-to-date version of > >> dim. > >> > >>

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove superfluous locking around userfault_list

On Tue, Oct 11, 2016 at 03:37:59PM +0100, Chris Wilson wrote: > Now that we have reduced the access to the list to either (a) under the > struct_mutex whilst holding the RPM wakeref (so that concurrent writers to > the list are serialised by struct_mutex) and (b) under the atomic > runtime suspend

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Use RPM as the barrier for controlling user mmap access

On Tue, Oct 11, 2016 at 03:37:58PM +0100, Chris Wilson wrote: > We can remove the false coupling between RPM and struct mutex by the > observation that we can use the RPM wakeref as the barrier around user > mmap access. That is as we tear down the user's PTE atomically from > within rpm suspend

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Move user fault tracking to a separate list

On Tue, Oct 11, 2016 at 03:37:57PM +0100, Chris Wilson wrote: > We want to decouple RPM and struct_mutex, but currently RPM has to walk > the list of bound objects and remove userspace mmapping before we > suspend (otherwise userspace may continue to access the GTT whilst it is > powered down).

Re: [Intel-gfx] [PATCH] drm: Print device information again in debugfs

On Thu, Oct 13, 2016 at 10:13 AM, Daniel Vetter wrote: > I was a bit over-eager in my cleanup in > > commit 95c081c17f284de50eaca60d4d55643a64d39019 > Author: Daniel Vetter > Date: Tue Jun 21 10:54:12 2016 +0200 > > drm: Move master pointer

Re: [Intel-gfx] [PATCH v2] drm/i915: Allow compaction upto SWIOTLB max segment size

On Wed, Oct 12, 2016 at 10:51:57PM +0100, Chris Wilson wrote: > On Wed, Oct 12, 2016 at 05:19:14PM -0400, Konrad Rzeszutek Wilk wrote: > > On Mon, Oct 10, 2016 at 11:27:00PM +0100, Chris Wilson wrote: > > > commit 1625e7e549c5 ("drm/i915: make compact dma scatter lists creation > > > work with

[Intel-gfx] [PATCH] drm: Print device information again in debugfs

I was a bit over-eager in my cleanup in commit 95c081c17f284de50eaca60d4d55643a64d39019 Author: Daniel Vetter Date: Tue Jun 21 10:54:12 2016 +0200 drm: Move master pointer from drm_minor to drm_device Noticed by Chris Wilson. Fixes: 95c081c17f28 ("drm: Move

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Merge duplicate gen4 and vlv/chv enable vblank callbacks

On Fri, Oct 07, 2016 at 08:49:52PM +0100, Chris Wilson wrote: > gen4/vlv/chv all use the same bits in pipestat to enable the vblank > interrupt, so they can share the same callbacks to enable/disable. > > Signed-off-by: Chris Wilson > Cc: Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915: Assert we hold the CRTC powerwell for generating vblank interrupts

On Wed, Oct 12, 2016 at 07:21:44AM +0200, Maarten Lankhorst wrote: > Op 11-10-16 om 10:32 schreef Ville Syrjälä: > > On Tue, Oct 11, 2016 at 09:45:45AM +0200, Maarten Lankhorst wrote: > >> Op 11-10-16 om 08:55 schreef Ville Syrjälä: > >>> On Tue, Oct 11, 2016 at 08:17:22AM +0200, Maarten Lankhorst

Re: [Intel-gfx] [PATCH] drm/i915: Skip unbinding large unmappable global buffers

On 13/10/2016 13:59, Chris Wilson wrote: On Thu, Oct 13, 2016 at 12:29:44PM +0100, Tvrtko Ursulin wrote: On 13/10/2016 09:55, Chris Wilson wrote: If the user requests a mappable binding to the global GTT, we will first unbind an existing mapping if it doesn't match. We will unbind even if

Re: [Intel-gfx] [i-g-t PATCH 1/3] tests: add more checks for finding the debugfs in script based tests

On Thu, Oct 13, 2016 at 04:55:49PM +0300, Jani Nikula wrote: > For whatever reason, I got a machine here where that file is empty (not > talking about the size, but cating the file actually produces > nothing). And I've got another machine where that is not the > case. *scratches head*. Appears

Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

On Fri, Oct 07, 2016 at 10:15:19AM +0300, Joonas Lahtinen wrote: > On to, 2016-10-06 at 16:36 +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > debugfs_wedged and drm_lib.sh are already using bashism so switch > > over > > to using

Re: [Intel-gfx] [i-g-t PATCH 1/3] tests: add more checks for finding the debugfs in script based tests

On Thu, Oct 13, 2016 at 04:55:49PM +0300, Jani Nikula wrote: > On Thu, 13 Oct 2016, Chris Wilson wrote: > >> + if [ -f $debugfs_path/dri/$minor/i915_error_state ] ; then > >> + i915_dfs_path=$debugfs_path/dri/$minor > > > > Thinking of how to wean ourselves off

Re: [Intel-gfx] [PATCH 02/22] drm/i915: Shrink sdvo_cmd_names

On Wed, Oct 05, 2016 at 01:33:29PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Pack the struct _sdvo_cmd_name to save 736 bytes of .rodata. > > This is fine since the name pointers are used only for debug. > > Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH igt 1/2] lib/igt_aux: Add support for various system suspend/resume options

On Wed, Oct 05, 2016 at 12:04:52PM +0300, Imre Deak wrote: > /* suspend/hibernate and auto-resume system */ > -void igt_system_suspend_autoresume(void); > -void igt_system_hibernate_autoresume(void); > + > +enum igt_suspend_state { > + SUSPEND_STATE_FREEZE, > + SUSPEND_STATE_MEM, > +

[Intel-gfx] [PATCH igt] intel-ci: CI is missing any wait tests in BAT

Add the two basic gem_wait tests to the fast list, together they take a total of 1s (when correctly functioning). Signed-off-by: Chris Wilson --- tests/intel-ci/fast-feedback.testlist | 2 ++ 1 file changed, 2 insertions(+) diff --git

Re: [Intel-gfx] [PATCH] drm/i915/guc: Sanitory checks for platform that dont have GuC

Em Qua, 2016-10-12 às 16:13 -0700, Anusha Srivatsa escreveu: > i915.enable_guc_loading/submission=2 forces the usage of GuC. > For platforms that do not have a GuC, asking the kernel to > use a GuC should not result in an error state. Do extra checks > to see if the platform even has a GuC or not,

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Add entrypoints for mapping dplls to encoders and crtcs

On Tue, Oct 04, 2016 at 03:32:17PM +0300, Ander Conselvan de Oliveira wrote: > Abstract the platform specific bits of mapping the dplls under a > platform independ entrypoints so the differences between platforms are > contained in the dpll code. I.e., it removes IS_PLATFORM() macros from > other

Re: [Intel-gfx] [i-g-t PATCH 1/3] tests: add more checks for finding the debugfs in script based tests

On Thu, 13 Oct 2016, Chris Wilson wrote: > On Thu, Oct 13, 2016 at 03:59:55PM +0300, Jani Nikula wrote: >> While at it, make debugfs_path point at the debugfs root, not >> dri. This'll be handy in future work. >> >> Signed-off-by: Jani Nikula >>

[Intel-gfx] ✗ Fi.CI.BAT: warning for New DDB Algo and WM fixes (rev4)

== Series Details == Series: New DDB Algo and WM fixes (rev4) URL : https://patchwork.freedesktop.org/series/1/ State : warning == Summary == Series 1v4 New DDB Algo and WM fixes https://patchwork.freedesktop.org/api/1.0/series/1/revisions/4/mbox/ Test gem_exec_suspend:

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Add dpll entrypoint for dumping hw state

On Tue, Oct 04, 2016 at 03:32:16PM +0300, Ander Conselvan de Oliveira wrote: > Remove the IS_PLATFORM() macros from intel_dump_pipe_config() and split > that logic in platform specific implementations inside the dpll code, > accessed through a platform independent interface. > > Signed-off-by:

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Update kerneldoc for intel_dpll_mgr.c

On Tue, Oct 04, 2016 at 03:32:15PM +0300, Ander Conselvan de Oliveira wrote: > The documentation for most of the non-static members and structs were > missing. Fix that. > > v2: Fix typos (Durga) > > v3: Rebase. > Fix make docs warnings. > Document more. > > Signed-off-by: Ander

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/gen9: Get rid of redundant watermark values

Op 08-10-16 om 02:11 schreef Lyude: > Now that we've make skl_wm_levels make a little more sense, we can > remove all of the redundant wm information. Up until now we'd been > storing two copies of all of the skl watermarks: one being the > skl_pipe_wm structs, the other being the global wm struct

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Rename intel_shared_dpll->mode_set() to prepare()

On Tue, Oct 04, 2016 at 03:32:14PM +0300, Ander Conselvan de Oliveira wrote: > The hook is called from intel_prepare_shared_dpll(). The name doesn't > make sense after all the changes to modeset code. So just call it > prepare. > > Signed-off-by: Ander Conselvan de Oliveira >

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state

On Tue, Oct 04, 2016 at 03:32:13PM +0300, Ander Conselvan de Oliveira wrote: > Struct intel_shared_dpll_config is used to hold the state of the DPLL in > the "atomic" sense, so call it state like everything else atomic. > > Signed-off-by: Ander Conselvan de Oliveira >

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Rename intel_shared_dpll_commit() to _swap_state()

On Tue, Oct 04, 2016 at 03:32:12PM +0300, Ander Conselvan de Oliveira wrote: > The function intel_shared_dpll_commit() performs the equivalent of > drm_atomic_helper_swap_state() for the shared dpll state, which is not > handled by the helpers. So rename it for consistency. > > v2: Fix typo in

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Introduce intel_release_shared_dpll()

On Tue, Oct 04, 2016 at 03:32:11PM +0300, Ander Conselvan de Oliveira wrote: > While the details of getting a shared dpll are wrapped by > intel_get_shared_dpll(), the release was still hand rolled into the > modeset code. Fix that by creating an entry point for releasing the > pll and move that

Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatched INIT power domain disabling during suspend

On to, 2016-10-13 at 15:43 +0300, Ville Syrjälä wrote: > On Thu, Oct 13, 2016 at 02:34:06PM +0300, Imre Deak wrote: > > Currently the display INIT power domain disabling/enabling happens in a > > mismatched way in the suspend/resume_early hooks respectively. This can > > leave display power wells

Re: [Intel-gfx] [i-g-t PATCH 1/3] tests: add more checks for finding the debugfs in script based tests

On Thu, Oct 13, 2016 at 03:59:55PM +0300, Jani Nikula wrote: > While at it, make debugfs_path point at the debugfs root, not > dri. This'll be handy in future work. > > Signed-off-by: Jani Nikula > --- > tests/drm_lib.sh | 16 ++-- > 1 file changed, 10

Re: [Intel-gfx] [PATCH] kms_atomic : Added subtest for Single Pipe DBUF validation

On Tue, Oct 04, 2016 at 10:17:58AM +0530, meghanelogal wrote: > Existing DDB algorithm divide the DDB wrt data rate, > hence the planes with the less height but same width > will be allocated less blocks and watermark are based > on width which requires more DDB. With this data the flip > may

Re: [Intel-gfx] [PATCH] drm/i915: Unalias obj->phys_handle and obj->userptr

On Mon, Oct 03, 2016 at 10:18:03AM +0300, Joonas Lahtinen wrote: > On pe, 2016-09-30 at 18:31 +0100, Chris Wilson wrote: > > We use obj->phys_handle to choose the pread/pwrite path, but as > > obj->phys_handle is a union with obj->userptr, we then mistakenly use > > the phys_handle path for

Re: [Intel-gfx] [PATCH 0/8] HuC Loading Patches

On Thu, Sep 29, 2016 at 11:03:57AM -0700, Anusha Srivatsa wrote: > These patches add HuC loading support. The userspace > patches that check for a fully loaded HuC firmware and use > it can be found at: > https://lists.freedesktop.org/archives/libva/2016-September/004554.html >

Re: [Intel-gfx] port intel-gpu-tools to Wayland

On Thu, Sep 29, 2016 at 04:45:34PM +0300, Jani Nikula wrote: > > Oh, the list and Petri seem to have been dropped off the distribution, > adding back. I don't have an answer on the rest. Petri? > > On Thu, 29 Sep 2016, cornel panceac wrote: > > 2016-09-29 14:53 GMT+02:00

Re: [Intel-gfx] [patch] drm/i915: fix a read size argument

Am 13.10.2016 10:55, schrieb Dan Carpenter: > We want to read 3 bytes here, but because the parenthesis are in the > wrong place we instead read: > > sizeof(intel_dp->edp_dpcd) == sizeof(intel_dp->edp_dpcd) > > which is one byte. > > Fixes: fe5a66f91c88 ("drm/i915: Read PSR

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Fix HDMI DPLL configuration

On Mon, Sep 26, 2016 at 06:02:20PM +0300, Jani Nikula wrote: > On Mon, 26 Sep 2016, Imre Deak wrote: > > a277ca7dc01d should've been a no-functional-change commit, but it > > removed the initialization of the dpll_hw_state for HDMI outputs, > > resulting in state mismatches

  1   2   3   >